2/11/2019 v0x43a Stat_reg base address is 0x40000000 0-2 unchanged 3 bit 11-0 sfp_tx_fault[11:0](i.e.SFP12-SFP1) bit 27-16 sfp_rx_lost[11:0](i.e.SFP12-SFP1) 4 bit 0 fmc_l12_pg_m2c bit 1 not fmc_l12_prsnt_l bit 2 fmc_l8_pg_m2c bit 3 not fmc_l8_prsnt_l bit 4 cdce_pll_lock_i bit 5 BC0_missing bit 6 fabric_clk_locked bit 7 ipb_rst_i bit 19-8 sfp_abs[11:0](i.e.SFP12-SFP1) bit 31-20 ngccm_dv[11:0](i.e.SFP12-SFP1) 5 bit 11-0 rx_frameclk_locked[11:0](i.e.SFP12-SFP1) bit 27-16 rx_wordclk_locked[11:0](i.e.SFP12-SFP1) 6 bit 11-0 sfp_rx_ready[11:0](i.e.SFP12-SFP1) bit 27-16 mgt_ready[11:0](i.e.SFP12-SFP1) 7 clkrate0 8 clkrate1 9 clkrate2 10 clkrate_rx_wordclk[SFP1] ...... 21 clkrate_rx_wordclk[SFP12] 22 TTC_counters(0) ...... 30 TTC_counters(8) 31 PRBS_rx_pattern_error_cnt[SFP1] ...... 42 PRBS_rx_pattern_error_cnt[SFP12] 43 ngccm_rx_down_counter[SFP1] ...... 54 ngccm_rx_down_counter[SFP12] 55 ngccm_bkp_regs[SFP1] ...... 66 ngccm_bkp_regs[SFP12] 67 bit 15-0 TimeoutErrorCounter_o[SFP1] bit 31-16 TimeoutErrorCounter_o[SFP2] ...... 72 bit 15-0 TimeoutErrorCounter_o[SFP11] bit 31-16 TimeoutErrorCounter_o[SFP12] 74-80 unchanged 81 bit 15-0 fabric_clk_lock_lost_counter 82 bit 15-0 number of cdce_pll_lock_lost detected bit 31-16 cdce_pll_lock_lost duration in unit of fabric_clk cycles 83 bit 15-0 rx_frameclk_lock_lost_counter[SFP1] ...... 94 bit 15-0 rx_frameclk_lock_lost_counter[SFP12] 95 bit 15-0 tx_ready_lost_counter[SFP1] ...... 106 bit 15-0 tx_ready_lost_counter[SFP12] 107 bit 15-0 bkp_pwr_flip_counter[SFP1] ...... 118 bit 15-0 bkp_pwr_flip_counter[SFP12] 119 bit 15-0 rx_rs_err_cnt[SFP1] ...... 130 bit 15-0 rx_rs_err_cnt[SFP12] 131 bit 31-16 TCK_outCounter[SFP1] bit 15-0 TCK_inCounter[SFP1] ...... 142 bit 31-16 TCK_outCounter[SFP12] bit 15-0 TCK_inCounter[SFP12] 143 bit 8-0 minimum phase between rising edges of fabric_clock and tx_wordclk of SFP1 bit 24-16 maximum phase between rising edges of fabric_clock and tx_wordclk of SFP1 ...... 154 bit 8-0 minimum phase between rising edges of fabric_clock and tx_wordclk of SFP12 bit 24-16 maximum phase between rising edges of fabric_clock and tx_wordclk of SFP12 note: phase in ns = phase*8.317/336 155 bit 15-0 percentage of time when SYS_MASTER of SFP1 = '1', 0x8000 equals 100% 156 bit 15-0 percentage of time when SYS_REFCLK of SFP1 = '1', 0x8000 equals 100% 157 bit 15-0 percentage of time when EPCS_CDR_LOCKED of SFP1 = '1', 0x8000 equals 100% 158 bit 15-0 percentage of time when RXPLL_LOCKED of SFP1 = '1', 0x8000 equals 100% 159 bit 15-0 percentage of time when RX_HEADER_LOCKED of SFP1 = '1', 0x8000 equals 100% 160 bit 31-24 all '1' after ngCCM_status reset, reset to '0' if corresponging status bit is '0' when test_comm is '1' bit 31 RX_DATA_VALID of SFP1 bit 30 RX_READY of SFP1 bit 29 RX_IS_DATA of SFP1 bit 28 RX_HEADER_LOCKED of SFP1 bit 27 RXPLL_LOCKED of SFP1 bit 26 EPCS_CDR_LOCKED of SFP1 bit 25 SYS_REFCLK of SFP1 bit 24 SYS_MASTER of SFP1 bit 23-16 current ngCCM_status bit 23 RX_DATA_VALID of SFP1 bit 22 RX_READY of SFP1 bit 21 RX_IS_DATA of SFP1 bit 20 RX_HEADER_LOCKED of SFP1 bit 19 RXPLL_LOCKED of SFP1 bit 18 EPCS_CDR_LOCKED of SFP1 bit 17 SYS_REFCLK of SFP1 bit 16 SYS_MASTER of SFP1 bit 15-0 percentage of time when test_comm of SFP1 = '1', 0x8000 equals 100% 161 bit 24 RX_COMM_HBGOOD of SFP1, '1' after ngCCM_status reset, reset to '0' if RX_COMM_HBGOOD is '0' when test_comm is '1' bit 16 current state of bit RX_COMM_HBGOOD bit 15-0 percentage of time when RX_READY of SFP1 = '1', 0x8000 equals 100% 162 bit 31-16 percentage of time when RX_COMM_HBGOOD of SFP1 = '1', 0x8000 equals 100% bit 15-0 percentage of time when RX_DATA_VALID of SFP1 = '1', 0x8000 equals 100% 163 bit 15-0 percentage of time when SYS_MASTER of SFP2 = '1', 0x8000 equals 100% ...... 249 bit 24 RX_COMM_HBGOOD of SFP12, '1' after ngCCM_status reset, reset to '0' if RX_COMM_HBGOOD is '0' when test_comm is '1' bit 16 current state of bit RX_COMM_HBGOOD bit 15-0 percentage of time when RX_READY of SFP12 = '1', 0x8000 equals 100% 250 bit 31-16 percentage of time when RX_COMM_HBGOOD of SFP12 = '1', 0x8000 equals 100% bit 15-0 percentage of time when RX_DATA_VALID of SFP12 = '1', 0x8000 equals 100% 251 bit 11-0 tx_ready(SFP12-SFP1) ctrl_reg base address 0x40000100 1 bit 0 reset all TX_wordclk to fabric_clk phase monitor(stat_reg 143-154) bit 1 reset GBT_bank_l12_118 TX and RX bit 2 reset GBT_bank_l12_117 TX and RX bit 3 reset GBT_bank_l12_116 TX and RX bit 4 reset GBT_bank_l8_112 TX and RX bit 5 reset ngCCM_status bit 8 if set, cdce_pll_lock lost will not cause reset bit 9 reset dmtd bit 10 reset fabric_clk MMCM 2-4 unchanged 5 ngCCM error counter reset bit 1 reset error counter for SFP1 bit 2 reset error counter for SFP2 ...... bit 12 reset error counter for SFP12 6 ngCCM and ngFEC_module reset[SFP1] ...... 17 ngCCM and ngFEC_module reset[SFP12] 18 qie_delay control[SFP1] ...... 29 qie_delay control[SFP1] 30 bit 11-0 SFP TX_DISBALE[SFP12-SFP1] 31 bit 11-0 GBT_RX_RESET[SFP12-SFP1] 31 bit 27-16 GBT_TX_RESET[SFP12-SFP1] ipb_miso, ipb_mosi 1 SFP1 ...... 12 SFP12 13 user_ipb_stat_regs 14 user_ipb_ctrl_regs