System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
Path D:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
D:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
D:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;
D:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
D:\Xilinx\14.7\ISE_DS\common\bin\nt64;
D:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;
c:\xilinx\13.1\ise_ds\ise\bin\nt;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\Altium Designer Summer 09\System;
C:\Program Files\TortoiseSVN\bin;
C:\Program Files (x86)\Silicon Laboratories\ClockBuilder Pro\Bin
D:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
D:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
D:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;
D:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
D:\Xilinx\14.7\ISE_DS\common\bin\nt64;
D:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;
c:\xilinx\13.1\ise_ds\ise\bin\nt;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\Altium Designer Summer 09\System;
C:\Program Files\TortoiseSVN\bin;
C:\Program Files (x86)\Silicon Laboratories\ClockBuilder Pro\Bin
D:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
D:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
D:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;
D:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
D:\Xilinx\14.7\ISE_DS\common\bin\nt64;
D:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;
c:\xilinx\13.1\ise_ds\ise\bin\nt;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\Altium Designer Summer 09\System;
C:\Program Files\TortoiseSVN\bin;
C:\Program Files (x86)\Silicon Laboratories\ClockBuilder Pro\Bin
D:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
D:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
D:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;
D:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
D:\Xilinx\14.7\ISE_DS\common\bin\nt64;
D:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;
c:\xilinx\13.1\ise_ds\ise\bin\nt;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\Altium Designer Summer 09\System;
C:\Program Files\TortoiseSVN\bin;
C:\Program Files (x86)\Silicon Laboratories\ClockBuilder Pro\Bin
XILINX D:\Xilinx\14.7\ISE_DS\ISE\ D:\Xilinx\14.7\ISE_DS\ISE\ D:\Xilinx\14.7\ISE_DS\ISE\ D:\Xilinx\14.7\ISE_DS\ISE\
XILINXD_LICENSE_FILE c:\xilinx\vivado\xilinx.lic c:\xilinx\vivado\xilinx.lic c:\xilinx\vivado\xilinx.lic c:\xilinx\vivado\xilinx.lic
XILINX_DSP D:\Xilinx\14.7\ISE_DS\ISE D:\Xilinx\14.7\ISE_DS\ISE D:\Xilinx\14.7\ISE_DS\ISE D:\Xilinx\14.7\ISE_DS\ISE
XILINX_EDK D:\Xilinx\14.7\ISE_DS\EDK D:\Xilinx\14.7\ISE_DS\EDK D:\Xilinx\14.7\ISE_DS\EDK D:\Xilinx\14.7\ISE_DS\EDK
XILINX_PLANAHEAD D:\Xilinx\14.7\ISE_DS\PlanAhead D:\Xilinx\14.7\ISE_DS\PlanAhead D:\Xilinx\14.7\ISE_DS\PlanAhead D:\Xilinx\14.7\ISE_DS\PlanAhead
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   glib_top.prj  
-ofn   glib_top  
-ofmt   NGC NGC
-p   xc6vlx130t-1-ff1156  
-top   glib_top  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 2 1
-power Power Reduction NO No
-iuc Use synthesis Constraints File NO No
-keep_hierarchy Keep Hierarchy Soft No
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes No
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES Yes
-sd Cores Search Directories {"src/system/cdce/cdce_phase_mon_v2/dpram" "src/system/ethernet/ipcore_dir/basex" "src/system/ethernet/ipcore_dir/sgmii" "src/system/pcie/sys_pcie/ezdma2_ipbus_int/cores/ezdma2_ctrl_dpram" "src/system/pcie/sys_pcie/ezdma2_ipbus_int/cores/ipbus_ctrl_dpram" "src/system/pcie/sys_pcie/ezdma2_ipbus_int/cores/slv_rd_fifo" "src/system/pcie/sys_pcie/ezdma2_ipbus_int/cores/slv_wr_fifo" "src/system/cdce/cdce_phase_mon_v2/pll" "src/system/pll" }  
-write_timing_constraints Write Timing Constraints NO No
-cross_clock_analysis Cross Clock Analysis NO No
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100
-bram_utilization_ratio BRAM Utilization Ratio 100 100
-dsp_utilization_ratio DSP Utilization Ratio 100 100
-reduce_control_sets   Auto Auto
-fsm_extract   YES Yes
-fsm_encoding   Auto Auto
-safe_implementation   No No
-fsm_style   LUT LUT
-ram_extract   Yes Yes
-ram_style   Auto Auto
-rom_extract   Yes Yes
-shreg_extract   YES Yes
-rom_style   Auto Auto
-auto_bram_packing   NO No
-resource_sharing   YES Yes
-async_to_sync   NO No
-use_dsp48   Auto Auto
-iobuf   YES Yes
-max_fanout   100000 100000
-bufg   32 32
-register_duplication   YES Yes
-register_balancing   No No
-optimize_primitives   NO No
-use_clock_enable   Auto Auto
-use_sync_set   Auto Auto
-use_sync_reset   Auto Auto
-iob   Auto Auto
-equivalent_register_removal   NO Yes
-slice_utilization_ratio_maxmargin   5 0
 
Translation Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise None
-dd   _ngo None
-p   xc6vlx130t-ff1156-1 None
-sd Macro Search Path src/system/pll None
-uc   src/system/sys/system.ucf None
 
Map Property Settings
Switch Name Property Name Value Default Value
-ol Place & Route Effort Level (Overall) high high
-xe Placer Extra Effort Map NORMAL  
-xt Extra Cost Tables 0 0
-ir Use RLOC Constraints OFF OFF
-ignore_keep_hierarchy Allow Logic Optimization Across Hierarchy TRUE FALSE
-logic_opt Combinatorial Logic Optimization TRUE FALSE
-mt Enable Multi-Threading 2 0
-t Starting Placer Cost Table (1-100) Map 1 0
-r Register Ordering 4 4
-register_duplication Register Duplication Map TRUE FALSE
-intstyle   ise None
-lc LUT Combining off off
-o   glib_top_map.ncd None
-w   true false
-pr Pack I/O Registers/Latches into IOBs off off
-p   xc6vlx130t-ff1156-1 None
 
Place and Route Property Settings
Switch Name Property Name Value Default Value
-xe   n None
-intstyle   ise  
-mt Enable Multi-Threading 4 off
-ol Place & Route Effort Level (Overall) high std
-w   true false
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3340 MHz Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3340 MHz Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3340 MHz Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3340 MHz
Host wusx-PC wusx-PC wusx-PC wusx-PC
OS Name Microsoft Windows 7 , 64-bit Microsoft Windows 7 , 64-bit Microsoft Windows 7 , 64-bit Microsoft Windows 7 , 64-bit
OS Release Service Pack 1 (build 7601) Service Pack 1 (build 7601) Service Pack 1 (build 7601) Service Pack 1 (build 7601)