Dec.11 2015 v0x12 added register 0x4 to set the limit of number trigger can be accepted during one shutter opening. (256 max since MPASA can only store up to 96 hits) Buffers for storing trigger time stamp have been reduced to 256 as well, the ipbus address for time stamp buffer has been changed, so software needs be updated. Dec.1 2015 v0x11 Fixed a bug in acquistion module state machine Nov.30 2015 v0x10 A lot of changes in this new version: bit shift in readout data is supposed to be fixed.(can't test it yet) MPA counter data for multiple MPAs are stored in consecutive locations so that one ipbus block read can read them out all. MPA data readout always follows an acquisition(shutter open), no separate command for MPA read any more. acquisition is started either by writing to 0x80 or by beam trigger in test beam mode. calibration, test beam mode, read all/counters only are all setup by reg 0x2 Unfortunately, some python script in the software may need modification too Nov.8 2015 v0xd fixed a bug in MPAread.vhd which caused readout data error. Nov.6 2015 v0xc added bit 2 to register 0x2 Nov.5 2015 v0xb time stamp for triggers received and accepted during one shutter opening expanded to up to 2K Nov.4 2015 v0xa allow for up to one million of triggers, but it requires to read out the trigger offset time together with data from that trigger. Nov.4 2015 v0x9 moved the time at which buffer_avl is decremented to avoid premature read out of data via ipbus Nov.3 2015 v0x8 Fixed a bug in clock generation. Disabling further trigger until data read and free data buffer is available for next triggerOct.26 2015 v0x7 shutter opening is set by the timeout register 0x205 In test beam mode, the shutter is started by beam trigger command now. The length of the Oct.6 2015 v0x6 fixed a bug in strip_out Oct.6 2015 v0x5 fixed a bug with ip address and mac address setting Oct.3 2015 v0x4 beam clock frequency changed from 53 to 26.5MHz added reg 0x5 as spill end time. Oct.2 2015 v0x3 Fixed bugs in acquisition modules Oct.1 2015 v0x2 beam test trigger logic added. Fixed two bugs in SPIutil and acquisition modules GLIB-MPA spec general control 0x0 r/w reset and firmware version write: bit 31-2 not used bit 1 write 1 armes glib to accept one beam cycle(start,triggers and halt) bit 0 write 1 will reset all the logic(not buffer contents) read: bit 31-16 firmware version(0x0002 now) bit 15-0 not used 0x1 r/w strip-out clock phase shift bit 31-9 not used bit 8-0 optimized phase shift of the clock(maximum value is 0x117) 0x2 r/w control register bit 31-6 not used bit 5 if 0, beam cycles are always accepted. Otherwise, glib needs be armed bit 4 if 1, both memory and counter will be read out bit 3 if 1, calstrobes will be generated during shutter open bit 2 if 1, clock to MPA light is generated from test beam 26.5 MHz clock, otherwise from Glib 125MHz clock bit 1 if 1, test beam mode. bit 0 if 1, enable MPA clock output 0x3 read only trigger counter in test beam mode (clocked by test beam clock) bit 31-20 not used bit 19-0 number of trigger received and accepted between start and halt commands 0x4 r/w Maximum trigger to accept during shutter openning. bit 31-9 not used bit 8 if set to 1, number of trigger to be accepted is unlimited bit 7-0 number of trigger to be accepted, when reached, shutter will be closed. 0x5 read only time stamp of halt command in test beam mode (clocked by test beam clock) bit 31-0 time stamp of halt command 0x8 read only accepted trigger count corresponding to data in buffer 0 bit 31-8 not used bit 7-0 number of trigger received and accepted during one shutter opening 0x9 read only accepted trigger count corresponding to data in buffer 1 0xa read only accepted trigger count corresponding to data in buffer 2 0xb read only accepted trigger count corresponding to data in buffer 3 0x80 r/w write to this register start the sequencer. write: bit 31-9 not used bit 8 if 1, beam spill going bit 7-5 number of free buffers(maximum of 4) bit 4 if 1, start an infinite daq loop. If 0, only once. bit 3-2 specify which of the four buffers to be used to store data bit 1-0 not used read: bit 31 readout busy bit 30-12 not used bit 11-10 current reading buffer number bit 9 MPA chip busy(shutter opened or data being read) bit 8 beam_start received, beam_halt yet to arrive bit 7-5 number of free buffer available bit 4 if 1, infinite daq loop started. bit 3-2 last buffer used bit 1-0 always reads 0 Utility SPI registers 0x100 r/w CLKUTIL frequency divider setting bit 31-4 not used bit 3-0 Utility clock frequency is 31.25/(1+N) N is bit 3-0 contents 0x101 r/w DAC data register write: bit 31-16 not used bit 15-0 data to be written to the DAC read: bit 31-16 data read back from the DAC bit 15-0 last data written to the DAC 0x102 r/w MPA setting write: bit 31 If 1, MPA setting does not change, reads back MPA status only bit 30-11 not used bit 10 VBIAS_EN bit 9 PVDD_EN bit 8 AVDD_EN bit 7 DVDD_EN bit 6 VDDPST_EN bit 5-0 If 1, strip data direction is from FPGA to MPA read: What was last written bit 31-11 not used bit 10 VBIAS_EN bit 9 PVDD_EN bit 8 AVDD_EN bit 7 DVDD_EN bit 6 VDDPST_EN bit 5-0 If 1, strip data direction is from FPGA to MPA 0x103 read only bit 31-1 not used bit 0 if 1, utility SPI is busy. 0x104 read only MPA setting read back from the registers bit 31-11 not used bit 10 VBIAS_EN bit 9 PVDD_EN bit 8 AVDD_EN bit 7 DVDD_EN bit 6 VDDPST_EN bit 5-0 If 1, strip data direction is from FPGA to MPA 0x105 read only MPA status bit 31-12 not used bit 11-6 MPA_HITOR bit 5-0 MPA_empty shutter control 0x201 R/W number of pulse to be sent bit 31-16 not used bit 15-0 number of pulse to be sent 0x202 R/W pulse length bit 31-16 not used bit 15-0 pulse length in unit of 1/320MHz 0x203 R/W pulse distance bit 31-16 not used bit 15-0 pulse distance in unit of 1/320MHz 0x204 R/W shutter open to calibration pulse delay bit 31-16 not used bit 15-0 shutter open to calibration pulse delay in unit of 1/320MHz 0x205 r/w shutter open time upper limit bit 31-0 maximum shutter open time in unit of one 320MHz clock cycle If all 0, shutter can remain open infintely strip-in buffer 0x2000-0x23ff buffer for MPA1, can store up to 256 strip data words(read only) bit 31-16 Always 0 bit 15-0 strip data 0x2400-0x27ff buffer for MPA2, can store up to 256 strip data words(read only) 0x2800-0x2bff buffer for MPA3, can store up to 256 strip data words(read only) 0x2c00-0x2fff buffer for MPA4, can store up to 256 strip data words(read only) 0x3000-0x33ff buffer for MPA5, can store up to 256 strip data words(read only) 0x3400-0x37ff buffer for MPA6, can store up to 256 strip data words(read only) 0x3800 current write address of buffer for MPA1(read only) bit 31-12 Always 0 bit 11-0 write address in unit of nibble 0x3801 current write address of buffer for MPA2(read only) 0x3802 current write address of buffer for MPA3(read only) 0x3803 current write address of buffer for MPA4(read only) 0x3804 current write address of buffer for MPA5(read only) 0x3805 current write address of buffer for MPA6(read only) 0x3806 Strip-in enable register R/W bit 31-6 Always 0 bit 5 if 1, enables to receive MPA6 strip data bit 4 if 1, enables to receive MPA5 strip data bit 3 if 1, enables to receive MPA4 strip data bit 2 if 1, enables to receive MPA3 strip data bit 1 if 1, enables to receive MPA2 strip data bit 0 if 1, enables to receive MPA1 strip data strip-out buffer 0x4000 r/w strip data to be sent to MPA1 bit 31-16 Always 0 bit 15-0 strip data 0x4001 r/w strip data to be sent to MPA2 0x4002 r/w strip data to be sent to MPA3 0x4003 r/w strip data to be sent to MPA4 0x4004 r/w strip data to be sent to MPA5 0x4005 r/w strip data to be sent to MPA6 0x4006 write only strip data write command register bit 31-6 Always 0 bit 5 if 1, write strip data to MPA6 bit 4 if 1, write strip data to MPA5 bit 3 if 1, write strip data to MPA4 bit 2 if 1, write strip data to MPA3 bit 1 if 1, write strip data to MPA2 bit 0 if 1, write strip data to MPA1 configuration SPI registers 0x6000 r/w write: bit 31-5 not used bit 4-0 selecting the starting configuration, normally that of MPA6.(this sets the five MSBs of DataConf memory read address of the SPI chain and that of the OutConf memory write address) read: bit 31-1 not used bit 0 if 1, configuration is busy. 0x6001 r/w bit 31-3 not used bit 2-0 number of MPAlights in the Daisy chain(default is 6) 0x6002 r/w CLKCONF frequency divider setting bit 31-4 not used bit 3-0 configuration clock frequency is 31.25/(2xN) N is bit 3-0 contents 0x6003 read only bit 31-15 not used bit 14-0 DataConf memory read address of the SPI chain 0x6004 read only bit 31-15 not used bit 14-0 OutConf memory write address of the SPI chain 0x6400-0x67ff r/w DataConf memory accessed via ipbus, no reordering of row2 pixels configuration data for each MPA is stored in 25 locations defined by the 5 LSBs of the ipbus address. Pixels48-47 is stored at 24, ..., Pixels 2-1 at 1 and Periphery at 0 Periphery data are 32 bit word, pixel data only use 20 bit LSB and the top 12 MSB are not used. ipbus address bit 9-5 can be used to define up to 32 different configurations Six consecutive address locations are needed to configure siz MPAlight chips. So up to five sets of configuration can be stored in the memory. Configuration memory must be loaded via ipbus before configuration can be started. Configuration always starts at the highest numbered MPA, normally MPA6 0x6800-0x6bff read only OutConf memory accessed via ipbus, no reordering of row2 pixels The organization of this meory is exactly the same as DataConf memory. This one is used to stored data read back from the MPAs and is read only. MPA readout buffers (all in 32-bit words) 0x8000-0x80d7 buf 0 of MPA1 memory data 0x80d7 bit71-40 of word 1 0x80d6 bit39-8 of word 1 0x80d5 bit7-0 of word 1, bit71-48 of word2 0x80d4 bit47-16 of word 2 0x80d3 bit15-0 of word 2, bit71-56 of word 3 0x80d2 bit55-24 of word 3 0x80d1 bit23-0 of word 3, bit71-64 of word 4 0x80d0 bit63-32 of word 4 0x80cf bit31-0 of word 4 .......... 0x8002 bit55-24 of word 95 0x8001 bit23-0 of word 95, bit71-64 of word 96 0x8000 bit63-32 of word 96 0x8000 bit31-0 of word 96 0x8100-0x81d7 buf 1 of MPA1 memory data 0x8200-0x82d7 buf 2 of MPA1 memory data 0x8300-0x83d7 buf 3 of MPA1 memory data 0x8400-0x87ff MPA2 memory data 0x8800-0x8bff MPA3 memory data 0x8c00-0x8fff MPA4 memory data 0x9000-0x93ff MPA5 memory data 0x9400-0x97ff MPA6 memory data 0x9800-0x9895 buf 0 of counter data 0x9800-0x9818 MPA1 counter data 0x9800 MPA1 header word(default x"ffffffff", can be changed by writing to 0x9c10) 0x9801 bit31-16 pixel2, bit 15-0 pixel1 0x9802 bit31-16 pixel4, bit 15-0 pixel3 ......... 0x9808 bit31-16 pixel16, bit 15-0 pixel15 0x9809 bit31-16 pixel31, bit 15-0 pixel32 0x980a bit31-16 pixel29, bit 15-0 pixel30 ......... 0x9810 bit31-16 pixel17, bit 15-0 pixel18 0x9811 bit31-16 pixel34, bit 15-0 pixel33 0x9812 bit31-16 pixel36, bit 15-0 pixel35 ......... 0x9818 bit31-16 pixel48, bit 15-0 pixel47 0x9819-0x9831 MPA2 counter data 0x9832-0x984a MPA3 counter data 0x984b-0x9863 MPA4 counter data 0x9864-0x987c MPA5 counter data 0x987d-0x9895 MPA6 counter data 0x9900-0x9995 buf 1 of counter data 0x9a00-0x9a95 buf 2 of counter data 0x9b00-0x9b95 buf 3 of counter data 0x9c02 R/W CLKOR frequency divider bit 31-4 not used bit 3-0 CLKOR frequency = 31MHz/(1+N) N is contents of bit 3-0 if N is 0, it will be taken as 1 0x9c10 R/W MPA1 counter data header bit 31-0 header word (default x"ffffffff") 0x9c11 R/W MPA2 counter data header bit 31-0 header word (default x"ffffffff") 0x9c12 R/W MPA3 counter data header bit 31-0 header word (default x"ffffffff") 0x9c13 R/W MPA4 counter data header bit 31-0 header word (default x"ffffffff") 0x9c14 R/W MPA5 counter data header bit 31-0 header word (default x"ffffffff") 0x9c15 R/W MPA6 counter data header bit 31-0 header word (default x"ffffffff") 0xa000-0xa0ff offset of trigger arrival time to start command, in unit of 26.5MHz beam clock for buffer0 bit 31-0 trigger arrival time 0xa100-0xa1ff offset of trigger arrival time to start command, in unit of 26.5MHz beam clock for buffer1 0xa200-0xa2ff offset of trigger arrival time to start command, in unit of 26.5MHz beam clock for buffer2 0xa300-0xa3ff offset of trigger arrival time to start command, in unit of 26.5MHz beam clock for buffer3 0xa400-0xa4ff offset of trigger arrival time to start command, in unit of 160MHz clock for buffer0 bit 31-0 trigger arrival time 0xa500-0xa5ff offset of trigger arrival time to start command, in unit of 160MHz clock for buffer0 0xa600-0xa6ff offset of trigger arrival time to start command, in unit of 160MHz clock for buffer0 0xa700-0xa7ff offset of trigger arrival time to start command, in unit of 160MHz clock for buffer0