Oct.2 2015 v0x3 Fixed bugs in acquisition modules Oct.1 2015 v0x2 beam test trigger logic added. Fixed two bugs in SPIutil and acquisition modules GLIB-MPA spec general control 0x0 r/w reset and firmware version write: bit 31-1 not used bit 0 write 1 will reset all the logic(not buffer contents) read: bit 31-16 firmware version(0x0002 now) bit 15-0 not used 0x1 r/w strip-out clock phase shift bit 31-9 not used bit 8-0 optimized phase shift of the clock(maximum value is 0x117) 0x2 r/w control register bit 31-2 not used bit 1 if 1, test beam mode. MPA clocks are generated from test beam 53.3 MHz clock bit 0 if 1, enable MPA clock output 0x3 read only trigger counter in test beam mode (clocked by test beam clock) bit 31-10 not used bit 9-0 number of trigger received between start and halt commands 0x4 read only trigger counter in test beam mode (clocked by 160MHz clock derived from 125MHz) bit 31-10 not used bit 9-0 number of trigger received between start and halt commands 0x80 r/w write to this register start the sequencer. write: bit 31-5 not used bit 4 if 1, start an infinite daq loop. If 0, only once. bit 3-2 specify which of the four buffers available to be used bit 1 if 1, reads both counter and memory data. Otherwise only counters are read. bit 0 if 1, is calibration read: bit 31 readout busy bit 30-8 not used bit 7-5 number of free buffer available bit 4 if 1, infinite daq loop started. bit 3-2 specify which of the four buffers available to be used bit 1 if 1, reads both counter and memory data. Otherwise only counters are read. bit 0 if 1, is calibration Utility SPI registers 0x100 r/w CLKUTIL frequency divider setting bit 31-4 not used bit 3-0 Utility clock frequency is 31.25/(1+N) N is bit 3-0 contents 0x101 r/w DAC data register write: bit 31-16 not used bit 15-0 data to be written to the DAC read: bit 31-16 data read back from the DAC bit 15-0 last data written to the DAC 0x102 r/w MPA setting write: bit 31 If 1, MPA setting does not change, reads back MPA status only bit 30-11 not used bit 10 VBIAS_EN bit 9 PVDD_EN bit 8 AVDD_EN bit 7 DVDD_EN bit 6 VDDPST_EN bit 5-0 If 1, strip data direction is from FPGA to MPA read: What was last written bit 31-11 not used bit 10 VBIAS_EN bit 9 PVDD_EN bit 8 AVDD_EN bit 7 DVDD_EN bit 6 VDDPST_EN bit 5-0 If 1, strip data direction is from FPGA to MPA 0x103 read only bit 31-1 not used bit 0 if 1, utility SPI is busy. 0x104 read only MPA setting read back from the registers bit 31-11 not used bit 10 VBIAS_EN bit 9 PVDD_EN bit 8 AVDD_EN bit 7 DVDD_EN bit 6 VDDPST_EN bit 5-0 If 1, strip data direction is from FPGA to MPA 0x105 read only MPA status bit 31-12 not used bit 11-6 MPA_HITOR bit 5-0 MPA_empty shutter control 0x200 R/W shutter control(no automatic MPA readout follows) write: bit 31-1 not used bit 0 If 1, open shutter with calibration pulses and then close If 0, open shutter and wait for HITOR signal read: bit 31-2 not used bit 1 if 1, shutter is open and it is busy. bit 0 if 1, last shutter open for sending calstrobes.(can be from either this ipbus command or from the sequencer) 0x201 R/W number of pulse to be sent bit 31-16 not used bit 15-0 number of pulse to be sent 0x202 R/W pulse length bit 31-16 not used bit 15-0 pulse length in unit of 1/320MHz 0x203 R/W pulse distance bit 31-16 not used bit 15-0 pulse distance in unit of 1/320MHz 0x204 R/W shutter to calibration pulse delay bit 31-16 not used bit 15-0 shutter to calibration pulse delay in unit of 1/320MHz 0x205 r/w shutter open time upper limit bit 31-0 maximum shutter open time in unit of one 320MHz clock cycle If all 0, shutter can remain open infintely strip-in buffer 0x2000-0x23ff buffer for MPA1, can store up to 256 strip data words(read only) bit 31-16 Always 0 bit 15-0 strip data 0x2400-0x27ff buffer for MPA2, can store up to 256 strip data words(read only) 0x2800-0x2bff buffer for MPA3, can store up to 256 strip data words(read only) 0x2c00-0x2fff buffer for MPA4, can store up to 256 strip data words(read only) 0x3000-0x33ff buffer for MPA5, can store up to 256 strip data words(read only) 0x3400-0x37ff buffer for MPA6, can store up to 256 strip data words(read only) 0x3800 current write address of buffer for MPA1(read only) bit 31-12 Always 0 bit 11-0 write address in unit of nibble 0x3801 current write address of buffer for MPA2(read only) 0x3802 current write address of buffer for MPA3(read only) 0x3803 current write address of buffer for MPA4(read only) 0x3804 current write address of buffer for MPA5(read only) 0x3805 current write address of buffer for MPA6(read only) 0x3806 Strip-in enable register R/W bit 31-6 Always 0 bit 5 if 1, enables to receive MPA6 strip data bit 4 if 1, enables to receive MPA5 strip data bit 3 if 1, enables to receive MPA4 strip data bit 2 if 1, enables to receive MPA3 strip data bit 1 if 1, enables to receive MPA2 strip data bit 0 if 1, enables to receive MPA1 strip data strip-out buffer 0x4000 r/w strip data to be sent to MPA1 bit 31-16 Always 0 bit 15-0 strip data 0x4001 r/w strip data to be sent to MPA2 0x4002 r/w strip data to be sent to MPA3 0x4003 r/w strip data to be sent to MPA4 0x4004 r/w strip data to be sent to MPA5 0x4005 r/w strip data to be sent to MPA6 0x4006 write only strip data write command register bit 31-6 Always 0 bit 5 if 1, write strip data to MPA6 bit 4 if 1, write strip data to MPA5 bit 3 if 1, write strip data to MPA4 bit 2 if 1, write strip data to MPA3 bit 1 if 1, write strip data to MPA2 bit 0 if 1, write strip data to MPA1 configuration SPI registers 0x6000 r/w write: bit 31-5 not used bit 4-0 selecting the starting configuration, normally that of MPA6.(this sets the five MSBs of DataConf memory read address of the SPI chain and that of the OutConf memory write address) read: bit 31-1 not used bit 0 if 1, configuration is busy. 0x6001 r/w bit 31-3 not used bit 2-0 number of MPAlights in the Daisy chain(default is 6) 0x6002 r/w CLKCONF frequency divider setting bit 31-4 not used bit 3-0 configuration clock frequency is 31.25/(2xN) N is bit 3-0 contents 0x6003 read only bit 31-15 not used bit 14-0 DataConf memory read address of the SPI chain 0x6004 read only bit 31-15 not used bit 14-0 OutConf memory write address of the SPI chain 0x6400-0x67ff r/w DataConf memory accessed via ipbus, no reordering of row2 pixels configuration data for each MPA is stored in 25 locations defined by the 5 LSBs of the ipbus address. Pixels48-47 is stored at 24, ..., Pixels 2-1 at 1 and Periphery at 0 Periphery data are 32 bit word, pixel data only use 20 bit LSB and the top 12 MSB are not used. ipbus address bit 9-5 can be used to define up to 32 different configurations Six consecutive address locations are needed to configure siz MPAlight chips. So up to five sets of configuration can be stored in the memory. Configuration memory must be loaded via ipbus before configuration can be started. Configuration always starts at the highest numbered MPA, normally MPA6 0x6800-0x6bff read only OutConf memory accessed via ipbus, no reordering of row2 pixels The organization of this meory is exactly the same as DataConf memory. This one is used to stored data read back from the MPAs and is read only. MPA readout buffers (all in 32-bit words) 0x8000-0x80d7 buf 0 of MPA1 memory data 0x8100-0x81d7 buf 1 of MPA1 memory data 0x8200-0x82d7 buf 2 of MPA1 memory data 0x8300-0x83d7 buf 3 of MPA1 memory data 0x8400-0x87ff MPA2 memory data 0x8800-0x8bff MPA3 memory data 0x8c00-0x8fff MPA4 memory data 0x9000-0x93ff MPA5 memory data 0x9400-0x97ff MPA6 memory data 0x9800-0x9818 MPA1 counter data 0x9820-0x9838 MPA2 counter data 0x9840-0x9858 MPA3 counter data 0x9860-0x9878 MPA4 counter data 0x9880-0x9898 MPA5 counter data 0x98a0-0x98b8 MPA6 counter data 0x9c00 R/W MPA readout control, write to this register will start a MPA readout bit 31 ready only, if set, readout is busy bit 30-3 not used bit 2-1 buffer number to be used to store the MPA data bit 0 if 1, reads both counter and memory data. Otherwise only counters are read. 0x9c02 R/W CLKOR frequency divider bit 31-4 not used bit 3-0 CLKOR frequency = 31MHz/(1+N) N is contents of bit 3-0 if N is 0, it will be taken as 1 0xa000-0xa3ff offset of trigger arrival time to start command, in unit of 53.3MHz clock bit 31-0 trigger arrival time 0xa400-0xa7ff offset of trigger arrival time to start command, in unit of 160MHz clock bit 31-0 trigger arrival time