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-- This module is the local control target logic
-- all accesses are 32-bit double word access, although not all bits are always used.
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-- flash memory access is in memory space and controlled by BAR0
-- BAR0 occupies 16 bytes of memory space
-- offset 0x0 of BAR0 is a write only FLASH address register, only bits 18-0 are implemented
-- offset 0x4 of BAR0 is a write/read FLASH data register, only bits 7-0 are implemented
-- Only byte accesses are accepted. Erase or program the flash need special commands as specified in the 
-- datasheets of the flash memory chip (29F002NB)
-- offset 0x8 and oxc of BAR0 are not used.
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-- BAR1 occupies 32 bytes of io space
-- offset 0x0 of BAR1 is used for communicating with the VTM PIC micro-controller
-- The protocol is specified in the VTM specs.
-- writing to it sends bits 7-0 to PIC and the data returned from PIC can be read back about 2 milliseconds
-- later. If bit 8 of the readback data is set, PIC failed to respond. Otherwise, bit 7-0 contains the data
-- access to this location before the previvious command has finished will cause a PCI retry 
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-- offset 0x4 of BAR1 is used for access the P3 backplane bus controller. It is a write/read register
-- read from it returns the status of the backplane bus controller. If the controller is not configured ( or
-- has an out-of-date firmware), it reads as 0xff. Otherwise, bits 3-2 are the controller firmware revision
-- (current version is 1), and bit 1 should be '1' if the motherboard has backplane bus pullup resistor networks
-- installed. Bit 0 powers up opposite to bit 1 and must be set to equal to bit 1 to enable the controller.
-- to set bit 0, write 0x3. To reset bit 0, write 0x2.
-- offset 0xc of BAR1 is write-only and used to start a local control chip reconfiguration
-- To start a reconfiguration, write a special data word to offset 0xc of BAR1
-- This special data word must have bit 18 = '1' and bits 15 downto 0 = "A5A5". Bits 17 and 16 specify the
-- set of configuration data to be used.
-- Each set has 64K bytes. Power-on always configures from set 0.
-- Set 3 is a backup set. Any failed configuration
-- attempt in other sets leads automatically to a set 3 reconfiguration. Normally one should not touch set 3.
-- if set 3 data are also corrupted, you have to configure from JTAG.
-- offset 0x10 of BAR1 is JTAG data register. It is a write/read register.
-- writing a 32-bit word to the JTAG data register causes 16 TCK being sent to the selected JTAG device together
-- with their corresponding TDI and TMS data. bits 31-16 are used as TMS data and bits 15-0 as TDI data.
-- the MSB goes out first. TDO data are read back following each falling edge of the TCK and are read back
-- as bits 15-0 from the JTAG data register. bits 31-16 are always read back as zeros.
-- offset 0x14 of BAR1 is JTAG control register. It is a write/read register.
-- bits 5-0 of the JTAG control register set the JTAG clock frequency. If bits 5-0 is set to n,
-- TCK frequency equals 16MHz/(1 + n)
-- bits 10-6 of the JTAG control register select the JTAG device:
-- 0x1 => log3		0x3 => bc		0xa => mip4		0xb => mip5		0xc => mip6
-- 0x9 => log2		0x11 => log1	0x12 => mip1	0x13 => mip2	0x14 => mip3		
-- bits 14-11 of the JTAG control register decide the number of JTAG cycles performed:
-- All zeros results in N = 1, and all ones results in N = 16
-- Jun.5.2002	S.X.Wu
-- July 29 2002 modified to add jtag_csr bits 14 thru 11