JDF G
// Created by Project Navigator ver 1.0
PROJECT dsat_v2
DESIGN dsat_v2
DEVFAM virtex2
DEVFAMTIME 0
DEVICE xc2v2000
DEVICETIME 1107532611
DEVPKG bg575
DEVPKGTIME 1107532611
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE ddrtx.vhd
SOURCE dsat_top.vhd
SOURCE lvdsrx.vhd
SOURCE lvdstx.vhd
SOURCE epp.vhd
SOURCE scl.vhd
SOURCE rwbus.vhd
SOURCE clocks.vhd
SOURCE sldbrx.vhd
SUBLIB dsat_lib VhdlLibrary vhdl
LIBFILE dsat.vhd dsat_lib vhdl
DEPASSOC dsat2_top dsat2.ucf
[Normal]
p_MapEffortLevel=xstvhd, virtex2, Implementation.t_map, 1107534636, High
p_xstEquivRegRemoval=xstvhd, virtex2, Schematic.t_synthesize, 1107615677, False
p_xstPackIORegister=xstvhd, virtex2, Schematic.t_synthesize, 1107615677, Yes
xilxBitgCfg_Rate=xstvhd, virtex2, Implementation.t_bitFile, 1107890894, 30
xilxMapAllowLogicOpt=xstvhd, virtex2, Implementation.t_map, 1107614644, True
xilxMapCoverMode=xstvhd, virtex2, Implementation.t_map, 1107534636, Speed
xilxMapTimingDrivenPacking=xstvhd, virtex2, Implementation.t_map, 1107534636, True
xilxNgdbldIOPads=xstvhd, virtex2, Implementation.t_ngdbuild, 1107534636, True
xilxPAReffortLevel=xstvhd, virtex2, Implementation.t_par, 1107534636, High
[STRATEGY-LIST]
Normal=True