-- -- Top-level DSAT for initial testing on real board -- Contains EPP block with some signals routed to J3 for scoping -- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library UNISIM; use UNISIM.VCOMPONENTS.all; library dsat_lib; use dsat_lib.dsat.all; entity dsat2_top is port ( -- g_rst : in std_logic; -- SIMULATION ONLY bp_a : out std_logic_vector(15 downto 0); -- backplane bus address bp_as, bp_clk : out std_logic; -- backplane clock, address stb bp_d : inout std_logic_vector(15 downto 0); -- backplane data I/O bp_den_n, bp_dout : out std_logic; -- backplane buffer enable, direction bp_dtack : in std_logic; -- backplane acknowledge bp_slot : out std_logic; -- backplane slot select strobe bp_write : out std_logic; epp_adxstb, epp_datastb : in std_logic; -- EPP address, data strobes epp_d : inout std_logic_vector(7 downto 0); -- EPP data I/O epp_ddir, epp_den : out std_logic; -- EPP buffer enable, direction epp_reset : in std_logic; -- EPP reset epp_wait : out std_logic; -- EPP wait handshake output epp_write : in std_logic; -- EPP write enable f_mclk, f_nrzc : out std_logic; -- SCL encoded outputs to backplane g_clk : in std_logic; -- on-board oscillator (53MHz) iso_in : out std_logic_vector(2 downto 1); -- ISO_IN LVDS bits iso_out : in std_logic_vector(2 downto 1); -- ISO_OUT LVDS bits lvds_shdn : out std_logic; -- LVDS serial driver shutdown (0=shutdown) rx_clk : in std_logic_vector(3 downto 0); rxd : in slv28by4; -- signals to SCL receiver DB (not needed if not installed!) scl_53mhz, scl_7mhz : in std_logic; scl_ack : in std_logic; scl_beam, scl_cosmic, scl_first : in std_logic; scl_dataerr, scl_syncerr, scl_ready : in std_logic; scl_bx : in std_logic_vector(7 downto 0); scl_l1_per, scl_l1a : in std_logic; scl_turn : in std_logic_vector(15 downto 0); -- serial link daughter board inputs sldb_refclk : out std_logic; sldb_d : in std_logic_vector(15 downto 0); sldb_dav_n, sldb_perr : in std_logic; sldb_rx_clk : in std_logic; sldb_lock : inout std_logic; sldb2_refclk : out std_logic; sldb2_d : in std_logic_vector(15 downto 0); sldb2_dav_n, sldb2_perr : in std_logic; sldb2_rx_clk : in std_logic; sldb2_lock : inout std_logic; -- test signals spare : out std_logic_vector(16 downto 1); tri_all : out std_logic; -- hi to disable backplane buffers -- LVDS transmitters tx_clk : out std_logic_vector(7 downto 0); txd : out slv28by4); end dsat2_top; architecture dsat2_a of dsat2_top is constant div_bit : integer := 22; -- divider for blinking LED, etc signal tx_clk_s : std_logic_vector(7 downto 0); signal txd_s : slv28by4; signal rxd_s : slv28by4; -- signal tx_clk_p : std_logic; -- mux for local bus reads type lb_mux_t is array (DEV_MAX-1 downto 0) of std_logic_vector(7 downto 0); signal lb_mux : lb_mux_t; signal epp_dout, epp_din : std_logic_vector(7 downto 0); signal epp_ds_sig, epp_as_sig : std_logic; signal epp_trst, epp_den_sig, epp_ddir_sig : std_logic; signal epp_wait_s : std_logic; signal lb_data_in_s, lb_data_out_s : std_logic_vector(7 downto 0); signal lb_addr_s : std_logic_vector(1 downto 0); signal lb_dev_s : std_logic_vector(DEV_BITS-1 downto 0); signal lb_byte_s : std_logic_vector(1 downto 0); signal lb_read_s, lb_write_s : std_logic; signal led1_s, led2_s, led3_s : std_logic; signal cntr : std_logic_vector(31 downto 0); -- local bus decoded enables signal lb_rwbus_ena, lb_scl_ena : std_logic; signal lb_tx_ena : std_logic_vector(7 downto 0); signal lb_rx_ena : std_logic_vector(3 downto 0); signal lb_sl_ena : std_logic_vector(1 downto 0); signal fc_s, bp_start_s : std_logic; -- first crossing from SCL; NRZC start -- bit from backplane block signal ctrl_bit : std_logic_vector(3 downto 0); signal g_trig : std_logic; -- global trigger from SCL signal clk : std_logic; -- inverted global clock signal clk_n : std_logic; -- inverted global clock signal clk90 : std_logic; -- inverted global clock signal clk270 : std_logic; -- inverted global clock signal g_reset : std_logic; signal g_pass : std_logic; signal g_pattern : std_logic; signal ram_test_addr_s : std_logic_vector(10 downto 0); signal ram_test_read_s, ram_test_write_s : std_logic; signal iso_outp : std_logic_vector(3 downto 0); begin -- dsat2_a ------------------------------------------------------------------------------- -- asynchronous logic ------------------------------------------------------------------------------- -- g_reset <= g_rst; -- simulation only -- drive output buffer controls epp_ddir <= not epp_ddir_sig; epp_den <= epp_den_sig; -- connect LED signals to outputs spare(1) <= led1_s; spare(2) <= led2_s; spare(3) <= led3_s; spare(11) <= txd_s(0)(0); epp_wait <= epp_wait_s; -- tx_clk_s <= (others => g_clk); txd <= txd_s; i_clocks: clocks PORT MAP( reset => '0', mclk => clk, mclkn => clk_n, mclk270 => clk270, mclk90 => clk90, clk_in => g_clk ); g_tx_clk: for i in tx_clk'range generate i_tx_clk : OFDDRCPE port map ( Q => tx_clk(i), C0 => clk90, C1 => clk270, CE => '1', CLR => '0', D0 => '0', D1 => '1', PRE => '0'); end generate; -- tx_clk(0) <= tx_clk_p; -- tx_clk(2) <= tx_clk_p; -- tx_clk(4) <= tx_clk_p; -- tx_clk(6) <= tx_clk_p; -- tx_clk(1) <= tx_clk_p; -- tx_clk(3) <= tx_clk_p; -- tx_clk(5) <= tx_clk_p; -- tx_clk(7) <= tx_clk_p; -- tx_clk <= tx_clk_s; -- generate 3-state control for I/O buffers epp_trst <= epp_den_sig or not epp_ddir_sig; -- blink LED to show we're alive led1_s <= cntr(div_bit); -- multiplex local bus inputs lb_data_in_s <= lb_mux( conv_integer( lb_dev_s)); -- local bus decoding lb_rwbus_ena <= '1' when ((lb_read_s = '1' or lb_write_s = '1') and lb_dev_s = ADX_BUS) else '0'; lb_scl_ena <= '1' when ((lb_read_s = '1' or lb_write_s = '1') and lb_dev_s = ADX_SCL) else '0'; te : for i in 0 to 7 generate lb_tx_ena(i) <= '1' when ((lb_read_s = '1' or lb_write_s = '1') and (lb_dev_s = (ADX_TX0+i))) else '0'; end generate te; re : for i in 0 to 3 generate lb_rx_ena(i) <= '1' when ((lb_read_s = '1' or lb_write_s = '1') and (lb_dev_s = (ADX_RX0+i))) else '0'; end generate re; sl : for i in 0 to 1 generate lb_sl_ena(i) <= '1' when ((lb_read_s = '1' or lb_write_s = '1') and (lb_dev_s = (ADX_SL0+i))) else '0'; end generate sl; -- SCL timing outputs i_f_mclk : OFDDRCPE port map ( Q => f_mclk, C0 => clk, C1 => clk_n, CE => '1', CLR => '0', D0 => '0', D1 => '1', PRE => '0'); tri_all <= '0'; lvds_shdn <= '1'; ------------------------------------------------------------------------------- -- synchronous processes ------------------------------------------------------------------------------- process(rx_clk(0)) begin if(rx_clk(0)'event and rx_clk(0) = '1')then rxd_s(0) <= rxd(0); end if; end process; process(rx_clk(1)) begin if(rx_clk(1)'event and rx_clk(1) = '1')then rxd_s(1) <= rxd(1); end if; end process; process(rx_clk(2)) begin if(rx_clk(2)'event and rx_clk(2) = '1')then rxd_s(2) <= rxd(2); end if; end process; process(rx_clk(3)) begin if(rx_clk(3)'event and rx_clk(3) = '1')then rxd_s(3) <= rxd(3); end if; end process; process (clk, g_reset) begin -- process if g_reset = '0' then -- asynchronous reset (active low) led1_s <= '0'; led2_s <= '0'; led3_s <= '0'; cntr <= (others => '0'); elsif clk'event and clk = '1' then -- rising clock edge cntr <= cntr + 1; -- update heartbeat counter if lb_write_s = '1' then -- latch LB signals to LEDS led2_s <= lb_addr_s(0); led3_s <= lb_data_out_s(0); end if; -- write to test ram address register if lb_write_s = '1' and lb_dev_s = ADX_RX0 and lb_addr_s = "00" then case lb_byte_s is when "00" => ram_test_addr_s(7 downto 0) <= lb_data_out_s; when "01" => ram_test_addr_s(10 downto 8) <= lb_data_out_s(2 downto 0); when others => null; end case; end if; end if; end process; ------------------------------------------------------------------------------- -- netlist logic (blocks) ------------------------------------------------------------------------------- -- ddrck : OFDDRCPE -- port map ( -- Q => tx_clk_p, -- C0 => g_clk, -- C1 => g_clk_n, -- CE => '1', -- CLR => '0', -- D0 => '0', -- D1 => '1', -- PRE => '0'); -- regular buffers for AS, DS so they don't use GCLK resources u2 : IBUF_LVCMOS33 port map (I => epp_adxstb, O => epp_as_sig); u3 : IBUF_LVCMOS33 port map (I => epp_datastb, O => epp_ds_sig); -- instantiate the EPP interface e1 : epp2 port map ( gclk => clk, grst => g_reset, debug_s => open, epp_din => epp_din, epp_dout => epp_dout, wr => epp_write, ds => epp_ds_sig, as => epp_as_sig, rst => epp_reset, ddir => epp_ddir_sig, den => epp_den_sig, epp_wait => epp_wait_s, lb_data_in => lb_data_in_s, lb_data_out => lb_data_out_s, lb_addr => lb_addr_s, lb_dev => lb_dev_s, lb_byte => lb_byte_s, lb_read => lb_read_s, lb_write => lb_write_s); -- generate IOBUFS for EPP port connection eppd_gen : for i in 7 downto 0 generate eppd1 : IOBUF_LVCMOS33 port map(I => epp_dout(i), O => epp_din(i), IO => epp_d(i), T => epp_trst ); end generate eppd_gen; -- backplane bus interface b1 : rwbus port map ( g_clk => clk, g_rst => g_reset, lb_data_in => lb_data_out_s, lb_data_out => lb_mux( conv_integer(ADX_BUS) ), lb_addr => lb_addr_s, lb_ena => lb_rwbus_ena, lb_byte => lb_byte_s, lb_read => lb_read_s, lb_write => lb_write_s, debug => open, bp_slot => bp_slot, bp_d => bp_d, bp_a => bp_a, bp_wr => bp_write, bp_as => bp_as, bp_clk => bp_clk, bp_den_n => bp_den_n, bp_dout => bp_dout, bp_dtack => bp_dtack, bp_start => bp_start_s); -- SCL simulator s1 : scl port map ( g_clk => clk, g_rst => g_reset, debug => spare(16 downto 13), nrzc => f_nrzc, fc => fc_s, ctrl_bit => ctrl_bit, iso_out => iso_in, global_trig => g_trig, g_pattern => g_pattern, g_pass => g_pass, bp_start => bp_start_s, lb_data_in => lb_data_out_s, lb_data_out => lb_mux( conv_integer(ADX_SCL)), lb_addr => lb_addr_s, lb_ena => lb_scl_ena, lb_byte => lb_byte_s, lb_read => lb_read_s, lb_write => lb_write_s); -- manually instantiate DDRTX so we can fix channel numbering -- Tx0, Tx1 dd1 : ddrtx port map ( gclk0 => clk, gclk1 => clk_n, rx_clk => rx_clk(0), grst => g_reset, lb_data_in => lb_data_out_s, lb_data_out0 => lb_mux(ADX_TX3), lb_data_out1 => lb_mux(ADX_TX4), lb_addr => lb_addr_s, lb_ena0 => lb_tx_ena(3), lb_ena1 => lb_tx_ena(4), lb_byte => lb_byte_s, lb_read => lb_read_s, lb_write => lb_write_s, t_debug => spare(12), g_trig => g_trig, g_pattern => g_pattern, g_pass => g_pass, ctrl_sel => "00", ctrl_bit => "0000", fc => fc_s, bp_start => bp_start_s, rx_data => rxd_s(0), tx_data => txd_s(0)); -- Tx2, Tx3 dd2 : ddrtx port map ( gclk0 => clk, gclk1 => clk_n, rx_clk => rx_clk(1), grst => g_reset, lb_data_in => lb_data_out_s, lb_data_out0 => lb_mux(ADX_TX5), lb_data_out1 => lb_mux(ADX_TX6), lb_addr => lb_addr_s, lb_ena0 => lb_tx_ena(5), lb_ena1 => lb_tx_ena(6), lb_byte => lb_byte_s, lb_read => lb_read_s, lb_write => lb_write_s, g_trig => g_trig, g_pattern => g_pattern, g_pass => g_pass, ctrl_sel => "10", ctrl_bit => ctrl_bit, fc => fc_s, bp_start => bp_start_s, rx_data => rxd_s(1), tx_data => txd_s(1)); -- Tx4, Tx5 dd3 : ddrtx port map ( gclk0 => clk, gclk1 => clk_n, rx_clk => rx_clk(2), grst => g_reset, lb_data_in => lb_data_out_s, lb_data_out0 => lb_mux(ADX_TX7), lb_data_out1 => lb_mux(ADX_TX0), lb_addr => lb_addr_s, lb_ena0 => lb_tx_ena(7), lb_ena1 => lb_tx_ena(0), lb_byte => lb_byte_s, lb_read => lb_read_s, lb_write => lb_write_s, g_trig => g_trig, g_pattern => g_pattern, g_pass => g_pass, ctrl_sel => "00", ctrl_bit => "0000", fc => fc_s, bp_start => bp_start_s, rx_data => rxd_s(2), tx_data => txd_s(2)); -- Tx6, Tx7 dd4 : ddrtx port map ( gclk0 => clk, gclk1 => clk_n, rx_clk => rx_clk(3), grst => g_reset, lb_data_in => lb_data_out_s, lb_data_out0 => lb_mux(ADX_TX1), lb_data_out1 => lb_mux(ADX_TX2), lb_addr => lb_addr_s, lb_ena0 => lb_tx_ena(1), lb_ena1 => lb_tx_ena(2), lb_byte => lb_byte_s, lb_read => lb_read_s, lb_write => lb_write_s, g_trig => g_trig, g_pattern => g_pattern, g_pass => g_pass, ctrl_sel => "01", ctrl_bit => ctrl_bit, fc => fc_s, bp_start => bp_start_s, rx_data => rxd_s(3), tx_data => txd_s(3)); iso_outp <= '0' & iso_out(2) & '0' & iso_out(1); rx : for i in 0 to 3 generate rx1 : lvdsrx port map ( gclk => clk, grst => g_reset, g_trig => g_trig, bp_start => bp_start_s, fc => fc_s, debug => open, lb_data_in => lb_data_out_s, lb_data_out => lb_mux(conv_integer(ADX_RX0+i)), lb_addr => lb_addr_s, lb_ena => lb_rx_ena(i), lb_byte => lb_byte_s, lb_read => lb_read_s, lb_write => lb_write_s, iso_out => iso_outp(i), rx_clk => rx_clk(i), rxd => rxd_s(i) ); end generate rx; i_sldb_rx: sldb_rx PORT MAP( gclk => clk, grst => g_reset, g_trig => g_trig, bp_start => bp_start_s, fc => fc_s, debug => open, lb_data_in => lb_data_out_s, lb_data_out => lb_mux(conv_integer(ADX_SL0)), lb_addr => lb_addr_s, lb_ena => lb_sl_ena(0), lb_byte => lb_byte_s, lb_read => lb_read_s, lb_write => lb_write_s, sldb_refclk => sldb_refclk, sldb_rx_clk => sldb_rx_clk, sldb_dav_n => sldb_dav_n, sldb_lock => sldb_lock, sldb_perr => sldb_perr, sldb_d => sldb_d ); i_sldb2_rx: sldb_rx PORT MAP( gclk => clk, grst => g_reset, g_trig => g_trig, bp_start => bp_start_s, fc => fc_s, debug => open, lb_data_in => lb_data_out_s, lb_data_out => lb_mux(conv_integer(ADX_SL1)), lb_addr => lb_addr_s, lb_ena => lb_sl_ena(1), lb_byte => lb_byte_s, lb_read => lb_read_s, lb_write => lb_write_s, sldb_refclk => sldb2_refclk, sldb_rx_clk => sldb2_rx_clk, sldb_dav_n => sldb2_dav_n, sldb_lock => sldb2_lock, sldb_perr => sldb2_perr, sldb_d => sldb2_d ); end dsat2_a;