--
-- package of components for DSAT
--

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;

library UNISIM;
use UNISIM.VCOMPONENTS.all;

package dsat is

  subtype slv28 is std_logic_vector(27 downto 0);
  type slv28by8 is array (7 downto 0) of slv28;
  type slv28by4 is array (3 downto 0) of slv28;

  constant REV : std_logic_vector(7 downto 0) := X"09";  -- Firmware Revision

-- bus addresses (device number, DEV_BITS bits of address)
-- note: highest device address bit currently unused

  constant DEV_MAX   : integer := 16;   -- number of devices
  constant DEV_BITS  : integer := 4;    -- bits required for device select
  constant CSR_WIDTH : integer := 8;    -- width of control/status registers

  constant ADX_SCL : integer := 0;      -- timing/control
  constant ADX_BUS : integer := 1;      -- R/W bus
  constant ADX_TX0 : integer := 2;      -- LVDS Transmitter 0
  constant ADX_TX1 : integer := 3;
  constant ADX_TX2 : integer := 4;
  constant ADX_TX3 : integer := 5;
  constant ADX_TX4 : integer := 6;
  constant ADX_TX5 : integer := 7;
  constant ADX_TX6 : integer := 8;
  constant ADX_TX7 : integer := 9;

  constant ADX_RX0 : integer := 10;     -- LVDS receiver 0
  constant ADX_RX1 : integer := 11;     -- LVDS receiver 1
  constant ADX_RX2 : integer := 12;     -- LVDS receiver 2
  constant ADX_RX3 : integer := 13;     -- LVDS receiver 3  

  constant ADX_SL0 : integer := 14;     -- SLDB receiver 0
  constant ADX_SL1 : integer := 15;     -- SLDB receiver 0  

-- address offsets within a device
  constant DEV_ADX : std_logic_vector(1 downto 0) := "00";  -- RAM address
  constant DEV_RAM : std_logic_vector(1 downto 0) := "01";  -- RAM read/write
  constant DEV_CSR : std_logic_vector(1 downto 0) := "10";  -- CSR
  constant DEV_AUX : std_logic_vector(1 downto 0) := "11";  -- other

	COMPONENT clocks
	PORT(
		reset : IN std_logic;
		clk_in : IN std_logic;          
		mclk : OUT std_logic;
		mclkn : OUT std_logic;
		mclk270 : OUT std_logic;
		mclk90 : OUT std_logic
		);
	END COMPONENT;

  component lvdsrx
    port (
      gclk, grst  : in  std_logic;
      lb_data_in  : in  std_logic_vector(7 downto 0);
      lb_data_out : out std_logic_vector(7 downto 0);
      lb_addr     : in  std_logic_vector(1 downto 0);
      lb_ena      : in  std_logic;
      lb_byte     : in  std_logic_vector(1 downto 0);
      lb_read     : in  std_logic;
      lb_write    : in  std_logic;
      debug       : out std_logic_vector(3 downto 0);
      g_trig      : in  std_logic;
      bp_start    : in  std_logic;
      fc          : in  std_logic;
      iso_out     : in  std_logic;
      rx_clk      : in  std_logic;
      rxd         : in  std_logic_vector(27 downto 0));
  end component;


  component ddrtx
    port (
      gclk0, gclk1, grst : in  std_logic;
      rx_clk             : in  std_logic;
      lb_data_in         : in  std_logic_vector(7 downto 0);
      lb_data_out0       : out std_logic_vector(7 downto 0);
      lb_data_out1       : out std_logic_vector(7 downto 0);
      lb_addr            : in  std_logic_vector(1 downto 0);
      lb_ena0, lb_ena1   : in  std_logic;
      lb_byte            : in  std_logic_vector(1 downto 0);
      lb_read            : in  std_logic;
      lb_write           : in  std_logic;
      t_debug            : out std_logic;
      g_pattern          : in  std_logic;
      g_pass             : in  std_logic;
      g_trig             : in  std_logic;
      ctrl_sel           : in  std_logic_vector(1 downto 0);
      ctrl_bit           : in  std_logic_vector(3 downto 0);
      fc                 : in  std_logic;
      bp_start           : in  std_logic;
      rx_data            : in std_logic_vector(27 downto 0);
      tx_data            : out std_logic_vector(27 downto 0));
  end component;

  component lvdstx
    port (
      gclk, grst  : in  std_logic;
      lb_data_in  : in  std_logic_vector(7 downto 0);
      lb_data_out : out std_logic_vector(7 downto 0);
      lb_addr     : in  std_logic_vector(1 downto 0);
      lb_ena      : in  std_logic;
      lb_byte     : in  std_logic_vector(1 downto 0);
      lb_read     : in  std_logic;
      lb_write    : in  std_logic;
      debug       : out std_logic;
      g_trig      : in  std_logic;
      fc          : in  std_logic;
      bp_start    : in  std_logic;
      txck        : out std_logic;
      tx_data     : out std_logic_vector(27 downto 0));
  end component;

  component epp2
    port (
      gclk, grst      : in  std_logic;
      debug_s         : out std_logic_vector(3 downto 0);
      epp_din         : in  std_logic_vector(7 downto 0);
      epp_dout        : out std_logic_vector(7 downto 0);
      wr, ds, as, rst : in  std_logic;
      ddir            : out std_logic;
      den             : out std_logic;
      epp_wait        : out std_logic;
      lb_data_in      : in  std_logic_vector(7 downto 0);
      lb_data_out     : out std_logic_vector(7 downto 0);
      lb_addr         : out std_logic_vector(1 downto 0);
      lb_dev          : out std_logic_vector(DEV_BITS-1 downto 0);
      lb_byte         : out std_logic_vector(1 downto 0);
      lb_read         : out std_logic;
      lb_write        : out std_logic);
  end component;

  component rwbus
    port (
      g_clk, g_rst      : in  std_logic;
      lb_data_in        : in  std_logic_vector(7 downto 0);
      lb_data_out       : out std_logic_vector(7 downto 0);
      lb_addr           : in  std_logic_vector(1 downto 0);
      lb_ena            : in  std_logic;
      lb_byte           : in  std_logic_vector(1 downto 0);
      lb_read           : in  std_logic;
      lb_write          : in  std_logic;
      debug             : out std_logic_vector(3 downto 0);
      bp_d              : inout std_logic_vector(15 downto 0);
      bp_a              : out std_logic_vector(15 downto 0);
      bp_wr, bp_as      : out std_logic;
      bp_clk            : out std_logic;
      bp_den_n, bp_dout : out std_logic;
      bp_dtack          : in  std_logic;
      bp_slot           : out std_logic;
      bp_start          : out std_logic);
  end component;


  component scl
    port (
      g_clk			 : in  std_logic;
      debug        : out std_logic_vector(3 downto 0);
      lb_data_in   : in  std_logic_vector(7 downto 0);
      lb_data_out  : out std_logic_vector(7 downto 0);
      lb_addr      : in  std_logic_vector(1 downto 0);
      lb_ena       : in  std_logic;
      lb_byte      : in  std_logic_vector(1 downto 0);
      lb_read      : in  std_logic;
      lb_write     : in  std_logic;
      bp_start     : in  std_logic;
      nrzc         : out std_logic;
      iso_out      : out std_logic_vector(1 downto 0);
      fc           : out std_logic;
      ctrl_bit     : out  std_logic_vector(3 downto 0);
      g_rst	       : out  std_logic;
      g_pattern    : out  std_logic;
      g_pass       : out  std_logic;
      global_trig  : out std_logic);
  end component;

component srlc16e
    generic(INIT : bit_vector := x"0000");
    port (
           d: in std_logic;
           clk: in std_logic;
           ce: in std_logic;
           a0: in std_logic;
           a1: in std_logic;
           a2: in std_logic;
           a3: in std_logic;
           q: out std_logic;
           q15: out std_logic);
end component;
COMPONENT srlc128e
	PORT(
		clk : IN std_logic;
		ce : IN std_logic;
		d : IN std_logic;
		a : IN std_logic_vector(6 downto 0);          
		qout : OUT std_logic
		);
END COMPONENT;

	COMPONENT sldb_rx
	PORT(
		gclk : IN std_logic;
		grst : IN std_logic;
		lb_data_in : IN std_logic_vector(7 downto 0);
		lb_addr : IN std_logic_vector(1 downto 0);
		lb_ena : IN std_logic;
		lb_byte : IN std_logic_vector(1 downto 0);
		lb_read : IN std_logic;
		lb_write : IN std_logic;
		g_trig : IN std_logic;
		bp_start : IN std_logic;
		fc : IN std_logic;
		sldb_rx_clk : IN std_logic;
		sldb_dav_n : IN std_logic;
		sldb_lock : IN std_logic;
		sldb_perr : IN std_logic;
		sldb_d : IN std_logic_vector(15 downto 0);          
		lb_data_out : OUT std_logic_vector(7 downto 0);
		debug : OUT std_logic_vector(3 downto 0);
		sldb_refclk : OUT std_logic
		);
	END COMPONENT;


end dsat;