--
-- DDR dual LVDS transmitter
--

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;

library UNISIM;
use UNISIM.VCOMPONENTS.all;

-- our private library
library dsat_lib;
use dsat_lib.dsat.all;


entity ddrtx is

  port (
    gclk0, gclk1, grst : in  std_logic;
	 rx_clk             : in  std_logic;
    lb_data_in         : in  std_logic_vector(7 downto 0);
    lb_data_out0       : out std_logic_vector(7 downto 0);
    lb_data_out1       : out std_logic_vector(7 downto 0);
    lb_addr            : in  std_logic_vector(1 downto 0);
    lb_ena0, lb_ena1   : in  std_logic;
    lb_byte            : in  std_logic_vector(1 downto 0);
    lb_read            : in  std_logic;
    lb_write           : in  std_logic;
-- txck0, txck1 : out std_logic;
    t_debug            : out std_logic;
    g_pass             : in  std_logic;
    g_pattern          : in  std_logic;
    g_trig             : in  std_logic;
    ctrl_sel           : in  std_logic_vector(1 downto 0);
    ctrl_bit           : in  std_logic_vector(3 downto 0);
    fc                 : in  std_logic;
    bp_start           : in  std_logic;
    rx_data            : in std_logic_vector(27 downto 0);
    tx_data            : out std_logic_vector(27 downto 0));

end ddrtx;





architecture ddrtx_a of ddrtx is

  signal txd0, txd1 : std_logic_vector(27 downto 0);
  signal d0, d1 : std_logic_vector(27 downto 0);
  signal ram_di : std_logic_vector(31 downto 0);
  signal ram_do : std_logic_vector(31 downto 0);
  signal pattern: std_logic_vector(31 downto 0);
  signal w_addr : std_logic_vector(8 downto 0);
  signal r_addr : std_logic_vector(8 downto 0);
  signal cntr : std_logic_vector(2 downto 0);
begin  -- ddrtx_a

  tx0 : lvdstx
    port map (
      gclk        => gclk0,
      grst        => grst,
      lb_data_in  => lb_data_in,
      lb_data_out => lb_data_out0,
      lb_addr     => lb_addr,
      lb_ena      => lb_ena0,
      lb_byte     => lb_byte,
      lb_read     => lb_read,
      lb_write    => lb_write,
      txck        => open,
      debug       => t_debug,
      g_trig      => g_trig,
		bp_start    => bp_start,
      fc          => fc,
      tx_dATA     => txd0);

  tx1 : lvdstx
    port map (
      gclk        => gclk0,
      grst        => grst,
      lb_data_in  => lb_data_in,
      lb_data_out => lb_data_out1,
      lb_addr     => lb_addr,
      lb_ena      => lb_ena1,
      lb_byte     => lb_byte,
      lb_read     => lb_read,
      lb_write    => lb_write,
      txck        => open,
      debug       => open,
      g_trig      => g_trig,
		bp_start    => bp_start,
      fc          => fc,
      tx_dATA     => txd1);

  g_d : for i in 27 downto 0 generate

    ddr1 : OFDDRCPE
      port map (
        Q   => tx_data(i),
        C0  => gclk0,
        C1  => gclk1,
        CE  => '1',
        CLR => '0',
        D0  => d0(i),
        D1  => d1(i),
        PRE => '0');
  end generate;
process(gclk0)
begin
  if gclk0'event and gclk0 = '1' then
    if(bp_start = '1')then
	   cntr <= "000";
	 else
	   cntr <= cntr + 1;
	 end if;
    if(g_pass = '1' or g_pattern = '1')then
	   d0 <= not ram_do(27 downto 0);
	 elsif(ctrl_sel(0) = '0')then
	   d0 <= txd0;
	 else
	   case cntr is
		  when "001" => d0 <= txd0(27 downto 2) & not ctrl_bit(0) & txd0(0);
		  when "010" => d0 <= txd0(27 downto 2) & not ctrl_bit(1) & txd0(0);
		  when "011" => d0 <= txd0(27 downto 2) & not ctrl_bit(3) & txd0(0);
		  when "101" => d0 <= txd0(27 downto 2) & not ctrl_bit(2) & txd0(0);
		  when others => d0 <= txd0;
		end case;
	 end if;
  end if;
end process;
process(gclk1)
begin
  if gclk1'event and gclk1 = '1' then
    if(g_pass = '1' or g_pattern = '1')then
		d1 <= d0;
	 elsif(ctrl_sel(1) = '0')then
	   d1 <= txd1;
	 else
	   case cntr is
		  when "001" => d1 <= txd1(27 downto 2) & not ctrl_bit(0) & txd1(0);
		  when "010" => d1 <= txd1(27 downto 2) & not ctrl_bit(1) & txd1(0);
		  when "011" => d1 <= txd1(27 downto 2) & not ctrl_bit(3) & txd1(0);
		  when "101" => d1 <= txd1(27 downto 2) & not ctrl_bit(2) & txd1(0);
		  when others => d1 <= txd1;
		end case;
	 end if;
  end if;
end process;
-- g_pass must stay '0' until rx_clk is valid and stable
process(rx_clk,g_pass)
begin
  if g_pass = '0' then
    w_addr(2 downto 0) <= "000";
  elsif rx_clk'event and rx_clk = '1' then
	 w_addr(2 downto 0) <= w_addr(2 downto 0) + 1;
  end if;
end process;
process(gclk0)
begin
  if gclk0'event and gclk0 = '1' then
    if(g_pass = '0')then
	   r_addr(2 downto 0) <= "100";
	 else
		r_addr(2 downto 0) <= r_addr(2 downto 0) + 1;
	 end if;
    if(g_pattern = '0')then
	   pattern(28 downto 0) <= '1' & x"0000000";
	 else
		pattern(28 downto 0) <= pattern(27 downto 0) & pattern(28);
	 end if;
  end if;
end process;
w_addr(8 downto 3) <= "000000";
r_addr(8 downto 3) <= "000000";
ram_di <= "0000" & rx_data;
pattern(31 downto 29) <= "000";
i_rxd_s : RAMB16_S36_S36
    port map (
      ADDRA => w_addr,
      ADDRB => r_addr,
      DIA   => ram_di,
      DIB   => pattern,
      DIPA  => (others => '0'),
      DIPB  => (others => '0'),
      WEA   => g_pass,
      WEB   => g_pattern,
      CLKA  => rx_clk,
      CLKB  => gclk0,
      SSRA  => '0',
      SSRB  => '0',
      ENA   => g_pass,
      ENB   => '1',
      DOB   => ram_do);


end ddrtx_a;