--------------------------------------------------------
--
-- This is the dcm module which generates all clock signals used inside the DCC.
--
--
---------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity clocks is 
    port (
	   		reset			: in std_logic;
	   		mclk			: out std_logic;
	   		mclkn			: out std_logic;
	   		mclk270		: out std_logic;
	   		mclk90		: out std_logic;
				clk_in		: in std_logic 
           );

end clocks;

architecture clock_arch of clocks is 
component DCM
    port ( CLKIN   : in  std_logic ;
           CLKFB   : in  std_logic ;
           RST     : in  std_logic ;
           DSSEN   : in  std_logic ;
           PSINCDEC: in  std_logic ;
           PSEN    : in  std_logic ;
           PSCLK   : in  std_logic ;
           CLK0    : out std_logic ;
           CLK90   : out std_logic ;
           CLK180  : out std_logic ;
           CLK270  : out std_logic ;
           CLK2X   : out std_logic ;
           CLK2X180: out std_logic ;
           CLKDV   : out std_logic ;
           CLKFX   : out std_logic ;
           CLKFX180: out std_logic ;
           LOCKED  : out std_logic ;
           STATUS  : out std_logic_vector(7 downto 0);
           PSDONE  : out std_logic );
end component;
component BUFG
         port (I: in std_logic; O: out std_logic);
end component;   
signal mclk_dcm: std_logic;
signal mclkn_dcm: std_logic;
signal mclk_int : std_logic;
signal mclk270_dcm: std_logic;
signal mclk90_i: std_logic;
signal mclk90_dcm: std_logic;
attribute CLKOUT_PHASE_SHIFT : string;
attribute PHASE_SHIFT : string;
attribute CLKOUT_PHASE_SHIFT of DCMclk90 : label is "FIXED";
attribute PHASE_SHIFT of DCMclk90 : label is "80";
begin
mclk90 <= mclk90_i;
mclk <= mclk_int;
mclkbufg : BUFG port map (O=>mclk_int, I=>mclk_dcm);
mclknbufg : BUFG port map (O=>mclkn, I=>mclkn_dcm);
DCMmclk: dcm port map	
         ( CLKIN   => clk_in ,
           CLKFB   => mclk_int ,
           RST     => reset ,
           DSSEN   => '0' ,
           PSINCDEC=> '0' ,
           PSEN    => '0' ,
           PSCLK   => '0' ,
           CLK0    => mclk_dcm ,
           CLK180  => mclkn_dcm);
mclk90bufg : BUFG port map (O=>mclk90_i, I=>mclk90_dcm);
mclk270bufg : BUFG port map (O=>mclk270, I=>mclk270_dcm);
DCMclk90: dcm port map	
         ( CLKIN   => mclk_int ,
           CLKFB   => mclk90_i ,
           RST     => reset ,
           DSSEN   => '0' ,
           PSINCDEC=> '0' ,
           PSEN    => '0' ,
           PSCLK   => '0' ,
			  clk0    => mclk90_dcm,
           CLK180   => mclk270_dcm);
end clock_arch;