Programmer's manual for DCC date: 7/3/02 author: S.X.Wu firmware revision: x"14" (x"13" for XC2V1000ES) DCC is accessed via BAR0 of log3 which occupies 0x2000 bytes of memory space OFFSET NAME ACCESS offset 0x0 command and status register R/W offset 0x4 write pointer R/W offset 0x8 read pointer R/W offset 0xc configuration register R/W offset 0x10 slink word counter Read Only offset 0x14 event builer word counter Read Only offset 0x18 pci1 word counter Read Only offset 0x1c pci2 word counter Read Only offset 0x20 pci1 event counter Read Only offset 0x24 pci2 event counter Read Only offset 0x28 pci1/pci2 input counter Read Only offset 0x800-ffc data written to SLINK Read Only (after reset, data are stored starting at 0x800, after location 0xffc is written, it wraps around) offset 0x1000-1ffc SDRAM memory window R/W command and status register 0x0 read: bit 31-15 not used bit 14 pci2 enabled bit 13 pci1 enabled bit 12 pci2 has data bit 11 pci1 has data bit 10 buffer available bit 9-2 DLL status bit 1 slink full bit 0 slink down write: bit 31-2 not used bit 1 reset slink bit 0 reset all except configuration register write pointer 0x4 read: bit 31-23 always '0' bit 22-5 DDR SDRAM write address aligned on 32-byte address bit 4-0 always '0' write: bit 31-23 not used bit 22-12 DDR SDRAM write window address (4kbytes window) bit 11-0 not used read pointer 0x8 read: bit 31-23 always '0' bit 22-5 DDR SDRAM read address aligned on 32-byte address bit 4-0 always '0' write: bit 31-23 not used bit 22-12 DDR SDRAM read window address (4kbytes window) bit 11-0 not used configuration register 0xc read: bit 31-24 Xilinx firmware revision, 0x"0b" now bit 23-16 always '0' bit 15-12 number of LRB channels to be read from PCI2 bit 11-8 number of LRB channels to be read from PCI1 bit 7-6 not used bit 5 run mode bit 4 test mode bit 3-2 slink data width, default to 32 bit bit 1 slink test mode bit 0 slink enable write: bit 31-16 write '1' to bit n resets bit n-16 bit 15-0 write '1' to bit m sets bit m slink word counter 0x10 read: bit 31-0 number of words written to slink transmitter event builder word counter 0x14 read: bit 31-0 number of words output from event builder pci1 word counter 0x18 read: bit 31-0 number of words read out from pci1 output fifo pci2 word counter 0x1c read: bit 31-0 number of words read out from pci2 output fifo pci1 event counter 0x20 read: bit 31-0 number of events read out from pci1 output fifo pci2 event counter 0x24 read: bit 31-0 number of events read out from pci2 output fifo pci1/pci2 input counter 0x28 read: bit 31-16 number of 16-bit words seen on pci2 input bit 15-0 number of 16-bit words seen on pci1 input Standard initialization procedure: operation comments write 0xffff0000 to 0xc clear configuration register set up log1,log2,LRBs set up configuration register, but do not put into run mode write 0x1 to 0x0 reset all registers write 0x20 to 0xc set to run mode write 0x1 to 0x0 reset all registers When in run mode, SDRAM memory write is ignored. If slink is enabled, SDRAM memory read is also ignored in run mode. Which results in gabbage data returned. If slink is not enabled, write to read pointer 0x8 the page address enables reading out any memory location within that 4kbyte window. Do not try to advance the read pointer ahead of the write pointer, which may result in fatal errors. Bit 4 of configuration register should be reset to '0' for normal operation. if bit 5, 4 and 1 of the configuration register are all set to '1', this is a special test mode, in which the data from pci1 and pci2 ports will be ignored, and data written to 0x1000 will be send to SLINK instead. You can access all registers in any modes.