-- Jan-23-2006 firmware version B added Pt and Phi ghost track veto within a sector 
-- Jan-23-2006 firmware version B added cluster matching bit in muon data output for run2b
-- Jan-25-2006 firmware version C corrected error in muon pattern bit of version B
-- Jan-25-2006 firmware version C added isolated track bit to muon data.
-- Jan-25-2006 firmware version C added option to enable cluster matiching and isolation bit in muon data for run2a.
-- Jan-25-2006 firmware version C DSAT must be upgraded to dsat_vb to run random test.
-- Jan-30-2006 firmware version D for run2a which does not correspond to DFEAv102 because it has veto for medium and
                                  low Pt bins.
-- Jan-31-2006 firmware version E for run2a which corresonds to DFEAv102.
-- June-2-2006 firmware version F for run2a, three control bits added to bus registers 0xB9 and 0xF9 to disable tracks
-- June-2-2006 firmware version D for run2b, three control bits added to bus registers 0xB9 and 0xF9 to disable tracks
-- Oct-24-2006 new U6V11.mcs adds finite persistence register at 0x200. History bits now writable for persistence test.
-- Oct-27-2006 firmware version E for run2b. signlet counts are added to L1CTOC output.
	       if bit 12 of register 0xB9(F9) is '0', singlet counts are azimuthally divided into four quarter-sector
	       groups. these counts are put at bits23-16 of L1 words 2,3,4 and 5 with increasing PHI.
	       If bit 12 is set to '1', counts are grouped for layer pairs a&b, c&d, e&f and g&h, with layers a&b put
               in the second word of L1 record.
	       Bit 12 of register 0xB9(F9) is also put at bit 16 of the first L1 word.
	       the timing of l1muon fake event has also been fixed in this version

DFEA timing and memory map

DFEA requires that BPCLK's rising edge is aligned with
the rising edge of the signal nrzc's START bit at the source side(DFEC outputs). 

Start bit is noted as cycle 0 and a BPCLK cycle contains 7 cycles.
DFEA samples AS, ADDR, DATA and WRITE signals at the end of cycle 4. Since propagation
delay of signals from DFEC compensates to some extent, if DFEC drives backplane
signals during cycles 3 through 5, there should be enough setup/hold margin for
DFEA.
For read cycles, DFEA always asserts the DTACK at the following BPCLK cycle. DFEA
drives DTACK and DATA lines during cycles 3 through 6, and puts valid data during cycles
4 through 6. If DFEC samples the data at the rising edge of BPCLK, the hold time is
guaranteed by the two-way propagation delays, and with three master clock cycles of
time, DATA and DTACK setup time should be fine. There are a minimum of three master
clock cycles for DATA lines' turn-around.

address 0x200:  persistence in unit of seconds, default 8 seconds.
		If set to 255, persistence is infinite.

read:
   bit 7-0	persistence in seconds
   bit 15-8	always '0'

write:
   bit 7-0	persistence in seconds
   bit 15-8	not used

address 0: board CSR  

read:
   bit 0	DFEA locked to nrzc
   bit 1	DFEA detected nrzc lock loss
   bit 2	DFEA detected nrzc parity error
   bit 7-3	not used always '0'
   bit 8	top sector scl embedded signal mismatch	
   bit 9	top sector l1 embedded signal mismatch	
   bit 10	top sector sg embedded signal mismatch	
   bit 11	top sector fx embedded signal mismatch	
   bit 12	bottom sector scl embedded signal mismatch	
   bit 13	bottom sector l1 embedded signal mismatch	
   bit 14	bottom sector sg embedded signal mismatch	
   bit 15	bottom sector fx embedded signal mismatch	

write:
   bit 0	reset
   bit 1	reset history registers and board CSR register
   bit 2	generate SCL clear (for test purposes only)
   bit 7-6	write '1' to bits 2-1 to test persistence
   bit 15-8	write '1' to corresponding bits to test persistence

address 1:  control bits delay (bit 7-3 determine how many events to be delayed, and
                                bit 2-0 determine the relative position of global eof
                                        and link eof)

read:
   bit 7-0	delay value
   bit 15-8	always '0'

write:
   bit 6-0	delay value to be wriiten to both sectors
   bit 15-7	not used

address 2:	fake and capture register
   bit 15-10	not used
   bit 9	capture input and L1 out once
   bit 8	inject and capture corresponding input and L1/L2 out once
   bit 7-6	not used
   bit 5	capture corresponding input and L1/L2 out when receiving next l1
   bit 4	inject fake data when receiving next fx
   bit 3-2	not used
   bit 1	inject at every fx
   bit 0	inject as long as it is '1'

address 3:	FPGA CSR

read:
   bit 0	top front FPGA U7 done signal
   bit 1	top back FPGA U8 done signal
   bit 2	bottom front U9 FPGA done signal
   bit 3	bottom front U10 FPGA done signal
   bit 4	top front FPGA init signal when done = '0'
		top front FPGA DCM lock signal when down = '1'
   bit 5	top back FPGA init signal when done = '0'
		top back FPGA DCM lock signal when down = '1'
   bit 6	bottom front FPGA init signal when done = '0'
		bottom front FPGA DCM lock signal when down = '1'
   bit 7	bottom back FPGA init signal when done = '0'
		bottom back FPGA DCM lock signal when down = '1'
   bit 15-8	DFEA board serial number

write:
   bit 0	top front FPGA reprogram start
   bit 1	top back FPGA reprogram start
   bit 2	bottom front FPGA reprogram start
   bit 3	bottom back FPGA reprogram start
   bit 11-4	not used
   bit 12	top front FPGA DCM reset
   bit 13	top back FPGA DCM reset
   bit 14	bottom front FPGA DCM reset
   bit 15	bottom back FPGA DCM reset

address 4:	U7 top front FPGA program data register
write:
   bit 7-0	first byte of configuration data
   bit 15-8	second byte of configuration data
read:
   bit 15-0	U7 firmware revision number(0xc as of Jan 25, 2006)

address 5:	U8 top back FPGA program data register
write:
   bit 7-0	first byte of configuration data
   bit 15-8	second byte of configuration data
read:
   bit 15-0	U8 firmware revision number(0xc as of Jan 25, 2006)

address 6:	U9 bottom front FPGA program data register
write:
   bit 7-0	first byte of configuration data
   bit 15-8	second byte of configuration data
read:
   bit 15-0	U9 firmware revision number(0xc as of Jan 25, 2006)

address 7:	U10 bottom back FPGA program data register
write:
   bit 7-0	first byte of configuration data
   bit 15-8	second byte of configuration data
read:
   bit 15-0	U10 firmware revision number(0xc as of Jan 25, 2006)

address 8:	history register a
read
   bit 0	up secotr tick_turn_locked
   bit 1	up secotr valid_trk
   bit 2	up secotr sg_err
   bit 3	up secotr bad fx
   bit 4	bottom secotr tick_turn_locked
   bit 5	bottom secotr valid_trk
   bit 6	bottom secotr sg_err
   bit 7	bottom secotr bad fx
   bit 8	scl seen
   bit 9	l1 seen
   bit 10	sg seen
   bit 11	fx seen
   bit 15-12	always'0'

write
   bit 15-0	write '1' to corresponding bits to test persistence

address 9:	history register b
read
   bit 7-0	corresponding link clock frequency error
   bit 15-8	corresponding link sync error

write
   bit 15-0	write '1' to corresponding bits to test persistence

address 10:	history register c
read
   bit 7-0	corresponding link period error
   bit 15-8	corresponding link pattern error

write
   bit 15-0	write '1' to corresponding bits to test persistence

address 11:	L2 pipeline depth register. Due to code change, the new depth value should be
		three less than the original value
write 
   bit 6-0	L2 pipeline depth register (Actullay bit 6 is not used)
   bit 15-7	not used

read
   bit 6-0	upper channel L2 pipeline depth register readback
   bit 7	always '0'
   bit 14-8	lower chan9nel L2 pipeline depth register readback
   bit 15	always '0'

address 0xc U6(backplane control) firmware version(0x12 as of OCt 25, 2006)

address 0xd tick number of captured fake event

address 0xe turn number of captured fake event

address 0xf display register for access test
	bit 14-12	can be used to control page to be display by front panel LEDs
			any cahnge in these bits will set LED page to bit14-12. Otherwise
			front panel push button increments the LED page selection register.
	bit 11-8 controls signals at test point
	when "0001"
			position  1: ground
			position  2: U6 NRZC data signal
			position  3: U6 NRZC start bit
			position  4: U6 NRZC locked
 			position  5: U7 EOF at the FPGA pad input
			position  6: ground
			position  7: ground
 			position  8: 
				LVDS link1 sync monitor. It is an overlap of the link side frame bit 
				and global side clear signal delayed by two clock cycles. 
				Changing the three LSBs of nrzc delay value to make the delayed
				clear signal following the frame bit as close as possible but do not
				overlap.
 			position  9: even sector L1_embedded
			position 10: even sector L1
			position 11: even sector FX_embedded
			position 12: even sector FX
 			position 13: odd sector L1_embedded
			position 14: odd sector L1
			position 15: odd sector FX_embedded
			position 16: odd sector FX
 			position 17: U9 EOF at the FPGA pad input
			position 18: ground
			position 19: ground
			position 20: same as position 8, but for LVDS link5

	when "0010"
			position  1: ground
			position  2: ground
			position  3: ground
			position  4: ground
 			position  5: U7 EOF at the FPGA pad input
			position  6: ground
			position  7: ground
 			position  8: 
				LVDS link2 sync monitor. It is an overlap of the link side frame bit 
				and global side clear signal delayed by two clock cycles. 
				Changing the three LSBs of nrzc delay value to make the delayed
				clear signal following the frame bit as close as possible but do not
				overlap.
 			position  9: even sector SG_embedded
			position 10: even sector SG
			position 11: even sector SCL_embedded
			position 12: even sector SCL
 			position 13: odd sector SG_embedded
			position 14: odd sector SG
			position 15: odd sector SCL_embedded
			position 16: odd sector SCL
 			position 17: U9 EOF at the FPGA pad input
			position 18: ground
			position 19: ground
			position 20: same as position 8, but for LVDS link6

	when "0011"
			position  1: ground
			position  2: ground
			position  3: ground
			position  4: ground
 			position  5: U7 EOF at the FPGA pad input
			position  6: LVDS link2 bit 3 delayed by two link2_clk cycles
			position  7: LVDS link2 bit 1 delayed by two link2_clk cycles
 			position  8: 
				LVDS link3 sync monitor. It is an overlap of the link side frame bit 
				and global side clear signal delayed by two clock cycles. 
				Changing the three LSBs of nrzc delay value to make the delayed
				clear signal following the frame bit as close as possible but do not
				overlap.
 			position  9: even sector muon_pe
			position 10: even sector muon_dat(15)
			position 11: even sector L1 header with FX bit set
			position 12: even sector L2CFT header
 			position 13: odd sector muon_pe
			position 14: odd sector muon_dat(15)
			position 15: odd sector L1 header with FX bit set
			position 16: odd sector L2CFT header
			  Note: signals from position 9 thru 16 are two clock cycles later than the
			  actual signals at the FPGA pad outputs.
 			position 17: U9 EOF at the FPGA pad input
			position 18: LVDS link7 bit 3 delayed by two link7_clk cycles
			position 19: LVDS link7 bit 1 delayed by two link7_clk cycles
			position 20: same as position 8, but for LVDS link7

	when "0100"
			position  1: ground
			position  2: ground
			position  3: ground
			position  4: ground
 			position  5: U7 EOF at the FPGA pad input
			position  6: ground
			position  7: ground
 			position  8: 
				LVDS link4 sync monitor. It is an overlap of the link side frame bit 
				and global side clear signal delayed by two clock cycles. 
				Changing the three LSBs of nrzc delay value to make the delayed
				clear signal following the frame bit as close as possible but do not
				overlap.
 			position  9: U8 EOF at the FPGA pad input
			position 10: U8 DCM_LOCK
			position 11: ground
			position 12: ground
 			position 13: U10 EOF at the FPGA pad input
			position 14: U10 DCM_LOCK
			position 15: ground
			position 16: ground
 			position 17: U9 EOF at the FPGA pad input
			position 18: ground
			position 19: ground
			position 20: same as position 8, but for LVDS link8

	when "0101" :   All position should have pulsing output. This is for assembly
			integrity test only.

	when "1111" :
			position  4: U6 clock
			position  5: U7 clock
			position  9: U8 clock
			position 13: U10 clock
			position 17: U9 clock
			other positions: ground

	when others :	all test point outputs ground level

address 0x10-16 top sector muon data capture(read-only)

address 0x18-1e bottom sector muon data capture(read-only)

note: for data word longer than 16 bits, lower 16 bits always in even addresses

address 0x20-2d top sector l1 data capture(read-only)

address 0x30-3d bottom sector l1 data capture(read-only)

address 0x40-55 top sector L2CPS data capture(read-only)

address 0x60-75 bottom sector L2CPS data capture(read-only)

address 0x80-B5 top sector L2CFT data capture(read-only)

address 0xB8 top sector sector register
   bit 6-0	sector
   bit 15-7	for test only

address 0xB9 top sector bus register
   bit 0	muon_patt
   bit 1	muon_fake
   bit 2	ctoc_zero
   bit 3	ctoc_patt
   bit 5-4	ctoc_fake_sel
   bit 7-6	ctoc_L2_fake
   bit 8	set to enable muon matching and isolation bits in muon data for run2a firmware
   bit 9	if '1' disables L1muon track output
   bit 10	if '1' disables L1CTOC track output
   bit 11	if '1' disables L2 track output
   bit 12	if '1' singlet count groups are radially divided
   bit 15-13	not used

address 0xBA top sector Max Pt equation sector number

address 0xBB top sector Max Pt equation version number

address 0xBC top sector High Pt equation sector number

address 0xBD top sector High Pt equation version number

address 0xBE top sector Med Pt equation sector number

address 0xBF top sector Med Pt equation version number

address 0xC0-F5 bottom sector L2CFT data capture(read-only)

address 0xF8 bottom sector sector register
   bit 6-0	sector
   bit 15-7	for test only

address 0xF9 bottom sector bus register
   bit 0	muon_patt
   bit 1	muon_fake
   bit 2	ctoc_zero
   bit 3	ctoc_patt
   bit 5-4	ctoc_fake_sel
   bit 7-6	ctoc_L2_fake
   bit 8	set to enable muon matching and isolation bits in muon data for run2a firmware
   bit 9	if '1' disables L1muon track output
   bit 10	if '1' disables L1CTOC track output
   bit 11	if '1' disables L2 track output
   bit 12	if '1' singlet count groups are radially divided
   bit 15-13	not used

address 0xFA bottom sector Max Pt equation sector number

address 0xFB bottom sector Max Pt equation version number

address 0xFC bottom sector High Pt equation sector number

address 0xFD bottom sector High Pt equation version number

address 0xFE bottom sector Med Pt equation sector number

address 0xFF bottom sector Med Pt equation version number

address 0x100-10D link1 data capture(read-only)

address 0x110-11D link2 data capture(read-only)

address 0x120-12D link3 data capture(read-only)

address 0x130-13D link4 data capture(read-only)

address 0x140-14D link5 data capture(read-only)

address 0x150-15D link6 data capture(read-only)

address 0x160-16D link7 data capture(read-only)

address 0x170-17D link8 data capture(read-only)

address 0x180-18D link1 fake data

address 0x190-19D link2 fake data

address 0x1A0-1AD link3 fake data

address 0x1AE top veto equation version number

address 0x1B0-1BD link4 fake data

address 0x1BE top sector Low Pt equation sector number

address 0x1BF top sector Low Pt equation version number

address 0x1C0-1CD link5 fake data

address 0x1D0-1DD link6 fake data

address 0x1E0-1ED link7 fake data

address 0x1F0-1FD link8 fake data

address 0x1FE bottom sector Low Pt equation sector number

address 0x1FF bottom sector Low Pt equation version number

FPGA programming procedure:

1. write to address 0x3 to start reprogramming
2. read from address 0x3 and check and wait until init is high
3. write configuration data to FPGA program data register, two byte
   at a time, lower byte will be sent out first.
4. read from address 0x3 and check done goes high
5. write to address 0x3 to reset DCM
6. read from address 0x3 and check init is high

LED display

red LED on the left: 3.3V
red LED on the right: 1.5V
top green LED on the left: all FPGAs' DONE high
top green LED on the right: DTACK
The rest of eight green LED displays a page of one byte information:
left column has odd bits with MSB bit 7 on the top.
right column has even bit with LSB bit0 at the bottom.
Page 0(power on default): bit 7-4 displays INIT signals of U9-U6 if corresponding done is '0'
					   and DCM lock when done is '1'
			  bit 3-0 display DONE signals of U9-U6
Page 1 : link clock error for LVDS channels 8-1
Page 2 : link sync error for LVDS channels 8-1
Page 3 : link period error for LVDS channels 8-1
Page 4 : link pattern error for LVDS channels 8-1
Page 5 : bit 7	embedded mismatch in LVDS 5-8
	 bit 6	embedded mismatch in LVDS 1-4
         bit 5  fx signal received
         bit 4  sg signal received
         bit 3  l1 signal received
         bit 2  scl signal received
         bit 1  nrzc start bit locked
         bit 0  nrzc parity error
Page 6 : DFEA S/N
Page 7 : lower byte of display register

TEST points

The 40-pin front panel header provides test signals from the FPGAs
The right column pins are all grounds.
The left column are signals
The positions are counted from top through bottom as 1 thru 20.
Refer to display register 0xf for details

LVDS link inputs:
link1	red cable from sector N-1
link2	brown cable from sector N
link3	green cable from sector N
link4	purple cable from sector N
link5	red cable from sector N+1
link6	yellow cable from sector N+1
link7	blue cable from sector N+1
link8	green cable from sector N+2

JTAG chain order:
U10,U8,U6,U22,U7 and U9

For LVDS link BERT test:
./dfea_test bert
It programs FPGAs with special version U7clb.mcs, U8clb.mcs, U9clb.mcs and U10clb.mcs
writes 0x10 to CSR of DSAT SCL
writes 0x1 to DFEA 0x0 to reset all error counters and LFSRs
writes 0x3f to DFEA 0xb8 and 0xf8 to arm all receivers
writes 0xc0 to DFEA 0xb8 and 0xf8 to start transmitting LFSRs
reads 18 registers from DFEA 0x40, first six are error counts. Others are received data
reads 18 registers from DFEA 0x60, first six are error counts. Others are received data

writes