Equations

********** Mapped Logic **********
FTCPE_backup: FTCPE port map (backup,backup_T,clk,NOT porn,'0');
     backup_T <= ((ma(20) AND ma(17) AND ma(16) AND ma(18) AND ma(19) AND
      en_conf AND NOT en_dclk AND backup AND NOT powerondelay AND pci3_done AND
      NOT sp_o(1))
      OR (NOT ma(20) AND NOT ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND
      ma(12) AND ma(13) AND ma(14) AND ma(15) AND en_conf AND NOT en_dclk AND
      NOT backup AND conf_fail AND NOT powerondelay AND NOT sp_o(1))
      OR (NOT ma(20) AND NOT ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND
      ma(12) AND ma(13) AND ma(14) AND ma(15) AND en_conf AND NOT en_dclk AND
      NOT backup AND NOT powerondelay AND NOT re_conf AND pci3_done AND NOT sp_o(1)));
FTCPE_conf_fail: FTCPE port map (conf_fail,conf_fail_T,clk,NOT porn,'0');
     conf_fail_T <= ((shift_data.EXP)
      OR (ma(20) AND conf_fail AND powerondelay AND NOT pci3_done AND
      NOT sp_o(1))
      OR (ma(20) AND NOT conf_fail AND NOT powerondelay AND NOT pci3_done AND
      NOT sp_o(1))
      OR (mdq(0) AND NOT mdq(1) AND mdq(2) AND NOT mdq(3) AND NOT mdq(4) AND
      mdq(5) AND NOT mdq(6) AND NOT ma(20) AND conf_fail AND sp_o(0) AND
      flash_we_q AND sp_i(5) AND NOT sp_o(1)));
dcc_clk <= clk;
FDCPE_div80: FDCPE port map (div8(0),div8_D(0),clk,NOT porn,'0',NOT sp_o(1));
     div8_D(0) <= (en_conf AND NOT div8(0));
FDCPE_div81: FDCPE port map (div8(1),div8_D(1),clk,NOT porn,'0',NOT sp_o(1));
     div8_D(1) <= ((en_conf AND div8(0) AND NOT div8(1))
      OR (en_conf AND NOT div8(0) AND div8(1)));
FTCPE_div82: FTCPE port map (div8(2),div8_T(2),clk,NOT porn,'0',NOT sp_o(1));
     div8_T(2) <= ((NOT en_conf AND div8(2))
      OR (en_conf AND div8(0) AND div8(1)));
FDCPE_en_conf: FDCPE port map (en_conf,en_conf_D,clk,'0',NOT porn);
     en_conf_D <= ((EXP13_.EXP)
      OR (pci3_dclk_OBUF.EXP)
      OR (NOT ma(18) AND en_conf)
      OR (NOT ma(19) AND en_conf)
      OR (en_conf AND en_dclk)
      OR (mdq(0) AND NOT mdq(1) AND mdq(2) AND NOT mdq(3) AND NOT mdq(4) AND
      mdq(5) AND NOT mdq(6) AND sp_o(0) AND flash_we_q AND sp_i(5) AND
      NOT sp_o(1)));
FTCPE_en_dclk: FTCPE port map (en_dclk,en_dclk_T,clk,NOT porn,'0');
     en_dclk_T <= ((pci2_dclk_OBUF.EXP)
      OR (NOT ma(20) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND
      en_dclk AND NOT sp_o(1))
      OR (ma(17) AND ma(18) AND ma(19) AND ma(12) AND ma(13) AND
      ma(14) AND ma(15) AND en_dclk AND NOT sp_o(1))
      OR (NOT ma(12) AND NOT ma(13) AND NOT ma(14) AND NOT ma(15) AND NOT ma(10) AND
      NOT ma(11) AND NOT ma(8) AND NOT ma(9) AND NOT ma(0) AND NOT ma(1) AND NOT ma(2) AND NOT ma(3) AND
      NOT ma(4) AND NOT ma(5) AND NOT ma(6) AND NOT ma(7) AND en_conf AND en_dclk AND
      div8(0) AND div8(1) AND div8(2) AND powerondelay AND NOT sp_o(1)));
FDCPE_flash_we_q: FDCPE port map (flash_we_q,flash_we_q_D,clk,NOT porn,'0');
     flash_we_q_D <= (NOT en_conf AND NOT shift_data AND sp_i(2) AND pci3_done);
FTCPE_ma0: FTCPE port map (ma(0),ma_T(0),clk,NOT porn,'0');
     ma_T(0) <= ((ma(0) AND shift_addr AND NOT sp_i(4) AND NOT sp_o(1))
      OR (NOT ma(0) AND shift_addr AND sp_i(4) AND NOT sp_o(1))
      OR (div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND
      NOT sp_o(1)));
FTCPE_ma1: FTCPE port map (ma(1),ma_T(1),clk,NOT porn,'0');
     ma_T(1) <= ((ma(0) AND NOT ma(1) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(0) AND ma(1) AND shift_addr AND NOT sp_o(1))
      OR (ma(0) AND div8(0) AND div8(1) AND div8(2) AND
      NOT shift_addr AND NOT sp_o(1)));
FTCPE_ma2: FTCPE port map (ma(2),ma_T(2),clk,NOT porn,'0');
     ma_T(2) <= ((ma(1) AND NOT ma(2) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(1) AND ma(2) AND shift_addr AND NOT sp_o(1))
      OR (ma(0) AND ma(1) AND div8(0) AND div8(1) AND div8(2) AND
      NOT shift_addr AND NOT sp_o(1)));
FTCPE_ma3: FTCPE port map (ma(3),ma_T(3),clk,NOT porn,'0');
     ma_T(3) <= ((ma(2) AND NOT ma(3) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(2) AND ma(3) AND shift_addr AND NOT sp_o(1))
      OR (ma(0) AND ma(1) AND ma(2) AND div8(0) AND div8(1) AND
      div8(2) AND NOT shift_addr AND NOT sp_o(1)));
FTCPE_ma4: FTCPE port map (ma(4),ma_T(4),clk,NOT porn,'0');
     ma_T(4) <= ((ma(3) AND NOT ma(4) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(3) AND ma(4) AND shift_addr AND NOT sp_o(1))
      OR (ma(0) AND ma(1) AND ma(2) AND ma(3) AND div8(0) AND
      div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1)));
FTCPE_ma5: FTCPE port map (ma(5),ma_T(5),clk,NOT porn,'0');
     ma_T(5) <= ((ma(4) AND NOT ma(5) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(4) AND ma(5) AND shift_addr AND NOT sp_o(1))
      OR (ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND
      div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1)));
FTCPE_ma6: FTCPE port map (ma(6),ma_T(6),clk,NOT porn,'0');
     ma_T(6) <= ((ma(5) AND NOT ma(6) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(5) AND ma(6) AND shift_addr AND NOT sp_o(1))
      OR (ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND
      div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1)));
FTCPE_ma7: FTCPE port map (ma(7),ma_T(7),clk,NOT porn,'0');
     ma_T(7) <= ((ma(6) AND NOT ma(7) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(6) AND ma(7) AND shift_addr AND NOT sp_o(1))
      OR (ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND
      ma(6) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND
      NOT sp_o(1)));
FTCPE_ma8: FTCPE port map (ma(8),ma_T(8),clk,'0',NOT porn);
     ma_T(8) <= ((ma(8) AND NOT ma(7) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(8) AND ma(7) AND shift_addr AND NOT sp_o(1))
      OR (ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND
      ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND
      NOT shift_addr AND NOT sp_o(1)));
FTCPE_ma9: FTCPE port map (ma(9),ma_T(9),clk,NOT porn,'0');
     ma_T(9) <= ((ma(8) AND NOT ma(9) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(8) AND ma(9) AND shift_addr AND NOT sp_o(1))
      OR (ma(8) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND
      ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND
      NOT shift_addr AND NOT sp_o(1)));
FTCPE_ma10: FTCPE port map (ma(10),ma_T(10),clk,NOT porn,'0');
     ma_T(10) <= ((en_dclk.EXP)
      OR (ma(10) AND NOT ma(9) AND shift_addr AND NOT sp_o(1))
      OR (ma(8) AND ma(9) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND
      ma(4) AND ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND
      div8(2) AND NOT shift_addr AND NOT sp_o(1)));
FTCPE_ma11: FTCPE port map (ma(11),ma_T(11),clk,NOT porn,'0');
     ma_T(11) <= ((ma(10) AND NOT ma(11) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(10) AND ma(11) AND shift_addr AND NOT sp_o(1))
      OR (ma(10) AND ma(8) AND ma(9) AND ma(0) AND ma(1) AND
      ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND
      div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1)));
FTCPE_ma12: FTCPE port map (ma(12),ma_T(12),clk,'0',NOT porn);
     ma_T(12) <= ((ma(12) AND NOT ma(11) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(12) AND ma(11) AND shift_addr AND NOT sp_o(1))
      OR (ma(10) AND ma(11) AND ma(8) AND ma(9) AND ma(0) AND
      ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND
      div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1)));
FTCPE_ma13: FTCPE port map (ma(13),ma_T(13),clk,'0',NOT porn);
     ma_T(13) <= ((ma(12) AND NOT ma(13) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(12) AND ma(13) AND shift_addr AND NOT sp_o(1))
      OR (ma(12) AND ma(10) AND ma(11) AND ma(8) AND ma(9) AND
      ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND
      ma(7) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND
      NOT sp_o(1)));
FTCPE_ma14: FTCPE port map (ma(14),ma_T(14),clk,'0',NOT porn);
     ma_T(14) <= ((ma(13) AND NOT ma(14) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(13) AND ma(14) AND shift_addr AND NOT sp_o(1))
      OR (ma(12) AND ma(13) AND ma(10) AND ma(11) AND ma(8) AND
      ma(9) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND
      ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND
      NOT shift_addr AND NOT sp_o(1)));
FTCPE_ma15: FTCPE port map (ma(15),ma_T(15),clk,'0',NOT porn);
     ma_T(15) <= ((ma(14) AND NOT ma(15) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(14) AND ma(15) AND shift_addr AND NOT sp_o(1))
      OR (ma(12) AND ma(13) AND ma(14) AND ma(10) AND ma(11) AND
      ma(8) AND ma(9) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND
      ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND
      NOT shift_addr AND NOT sp_o(1)));
FTCPE_ma16: FTCPE port map (ma(16),ma_T(16),clk,NOT porn,'0');
     ma_T(16) <= ((ma(16) AND NOT ma(15) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(16) AND ma(15) AND shift_addr AND NOT sp_o(1))
      OR (ma(12) AND ma(13) AND ma(14) AND ma(15) AND ma(10) AND
      ma(11) AND ma(8) AND ma(9) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND
      ma(4) AND ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND
      div8(2) AND NOT shift_addr AND NOT sp_o(1)));
FTCPE_ma17: FTCPE port map (ma(17),ma_T(17),clk,NOT porn,'0');
     ma_T(17) <= ((ma(17) AND NOT ma(16) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(17) AND ma(16) AND shift_addr AND NOT sp_o(1))
      OR (ma(16) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND
      ma(10) AND ma(11) AND ma(8) AND ma(9) AND ma(0) AND ma(1) AND
      ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND
      div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1)));
FTCPE_ma18: FTCPE port map (ma(18),ma_T(18),clk,'0',NOT porn);
     ma_T(18) <= ((ma(17) AND NOT ma(18) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(17) AND ma(18) AND shift_addr AND NOT sp_o(1))
      OR (ma(17) AND ma(16) AND ma(12) AND ma(13) AND ma(14) AND
      ma(15) AND ma(10) AND ma(11) AND ma(8) AND ma(9) AND ma(0) AND
      ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND
      div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1)));
FTCPE_ma19: FTCPE port map (ma(19),ma_T(19),clk,'0',NOT porn);
     ma_T(19) <= ((ma(18) AND NOT ma(19) AND shift_addr AND NOT sp_o(1))
      OR (NOT ma(18) AND ma(19) AND shift_addr AND NOT sp_o(1))
      OR (ma(17) AND ma(16) AND ma(18) AND ma(12) AND ma(13) AND
      ma(14) AND ma(15) AND ma(10) AND ma(11) AND ma(8) AND ma(9) AND
      ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND
      ma(7) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND
      NOT sp_o(1)));
FTCPE_ma20: FTCPE port map (ma(20),ma_T(20),clk,NOT porn,'0');
     ma_T(20) <= ((ma(20) AND shift_addr AND NOT sp_i(6) AND NOT sp_o(1))
      OR (NOT ma(20) AND shift_addr AND sp_i(6) AND NOT sp_o(1))
      OR (ma(17) AND ma(16) AND ma(18) AND ma(19) AND ma(12) AND
      ma(13) AND ma(14) AND ma(15) AND ma(10) AND ma(11) AND ma(8) AND
      ma(9) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND
      ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND
      NOT shift_addr AND NOT sp_o(1)));
mcen <= '0';
FDCPE_mdq2data: FDCPE port map (mdq2data,mdq2data_D,clk,NOT porn,'0',NOT sp_o(1));
     mdq2data_D <= ((NOT en_conf AND NOT powerondelay AND pci3_done AND sp_i(1))
      OR (NOT div8(0) AND div8(1) AND div8(2) AND NOT powerondelay));
FDCPE_mdq0: FDCPE port map (mdq_I(0),mdq(0),clk,'0','0');
     mdq(0) <= ((moen_OBUF.EXP)
      OR (mdq(0) AND NOT porn)
      OR (mdq(0) AND sp_o(1))
      OR (porn AND mdq2data AND mdq(0).PIN AND NOT sp_o(1))
      OR (mdq(1) AND porn AND en_conf AND NOT mdq2data AND NOT sp_o(1)));
     mdq(0) <= mdq_I(0) when mdq_OE(0) = '1' else 'Z';
     mdq_OE(0) <= flash_we_q;
FDCPE_mdq1: FDCPE port map (mdq_I(1),mdq(1),clk,'0','0');
     mdq(1) <= ((_7_.EXP)
      OR (mdq(1) AND NOT porn)
      OR (mdq(1) AND sp_o(1))
      OR (porn AND mdq2data AND mdq(1).PIN AND NOT sp_o(1))
      OR (mdq(2) AND porn AND en_conf AND NOT mdq2data AND NOT sp_o(1)));
     mdq(1) <= mdq_I(1) when mdq_OE(1) = '1' else 'Z';
     mdq_OE(1) <= flash_we_q;
FDCPE_mdq2: FDCPE port map (mdq_I(2),mdq(2),clk,'0','0');
     mdq(2) <= ((_6_.EXP)
      OR (mdq(2) AND NOT porn)
      OR (mdq(2) AND sp_o(1))
      OR (porn AND mdq2data AND mdq(2).PIN AND NOT sp_o(1))
      OR (mdq(3) AND porn AND en_conf AND NOT mdq2data AND NOT sp_o(1)));
     mdq(2) <= mdq_I(2) when mdq_OE(2) = '1' else 'Z';
     mdq_OE(2) <= flash_we_q;
FDCPE_mdq3_BUFR: FDCPE port map (mdq(3)_BUFR,mdq_D(3)_BUFR,clk,'0','0');
     mdq_D(3)_BUFR <= ((mdq(4)_BUFR.EXP)
      OR (mdq(3) AND NOT porn)
      OR (mdq(3) AND sp_o(1))
      OR (porn AND mdq2data AND mdq(3).PIN AND NOT sp_o(1))
      OR (mdq(3) AND NOT en_conf AND NOT mdq2data AND NOT shift_data AND
      sp_i(2))
      OR (mdq(4) AND porn AND en_conf AND NOT mdq2data AND NOT sp_o(1)));
mdq_I(3) <= mdq(3)_BUFR;
     mdq(3) <= mdq_I(3) when mdq_OE(3) = '1' else 'Z';
     mdq_OE(3) <= flash_we_q;
mdq_I(4) <= mdq(4)_BUFR;
     mdq(4) <= mdq_I(4) when mdq_OE(4) = '1' else 'Z';
     mdq_OE(4) <= flash_we_q;
FDCPE_mdq4_BUFR: FDCPE port map (mdq(4)_BUFR,mdq_D(4)_BUFR,clk,'0','0');
     mdq_D(4)_BUFR <= ((pci1_dclk_OBUF.EXP)
      OR (mdq(4) AND NOT porn)
      OR (mdq(4) AND sp_o(1))
      OR (porn AND mdq2data AND mdq(4).PIN AND NOT sp_o(1)));
FDCPE_mdq5: FDCPE port map (mdq_I(5),mdq(5),clk,'0','0');
     mdq(5) <= ((addr(10).EXP)
      OR (addr(17).EXP)
      OR (mdq(5) AND NOT porn)
      OR (mdq(5) AND sp_o(1))
      OR (porn AND mdq2data AND mdq(5).PIN AND NOT sp_o(1))
      OR (mdq(6) AND porn AND en_conf AND NOT mdq2data AND NOT sp_o(1)));
     mdq(5) <= mdq_I(5) when mdq_OE(5) = '1' else 'Z';
     mdq_OE(5) <= flash_we_q;
FDCPE_mdq6: FDCPE port map (mdq_I(6),mdq(6),clk,'0','0');
     mdq(6) <= ((EXP12_.EXP)
      OR (mdq(6) AND NOT porn)
      OR (mdq(6) AND sp_o(1))
      OR (porn AND mdq2data AND mdq(6).PIN AND NOT sp_o(1))
      OR (porn AND en_conf AND NOT mdq2data AND sp_o(0) AND NOT sp_o(1)));
     mdq(6) <= mdq_I(6) when mdq_OE(6) = '1' else 'Z';
     mdq_OE(6) <= flash_we_q;
FDCPE_mdq7: FDCPE port map (mdq_I(7),mdq(7),clk,'0','0');
     mdq(7) <= ((powerondelay.EXP)
      OR (NOT porn AND mdq(7))
      OR (mdq(7) AND sp_o(1))
      OR (porn AND mdq2data AND mdq(7).PIN AND NOT sp_o(1))
      OR (mdq(7) AND NOT en_conf AND NOT mdq2data AND NOT shift_data AND
      sp_i(2)));
     mdq(7) <= mdq_I(7) when mdq_OE(7) = '1' else 'Z';
     mdq_OE(7) <= flash_we_q;
moen <= (NOT en_conf AND sp_i(2) AND pci3_done);
mrstn <= porn;
mwen <= NOT ((NOT en_conf AND NOT shift_data AND sp_i(2) AND pci3_done));
FDCPE_pci1_confn: FDCPE port map (pci1_confn,pci1_confn_D,clk,'0',NOT porn);
     pci1_confn_D <= (NOT ma(20) AND NOT ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND
      ma(12) AND ma(13) AND ma(14) AND ma(15) AND NOT ma(10) AND NOT ma(11) AND
      ma(8) AND NOT ma(9) AND en_conf AND NOT powerondelay);
FDCPE_pci1_data: FDCPE port map (pci1_data,pci1_data_D,clk,'0','0',porn);
     pci1_data_D <= (mdq(0) AND NOT ma(20) AND NOT ma(17) AND ma(16) AND ma(18) AND
      ma(19) AND en_dclk);
FDCPE_pci1_dclk: FDCPE port map (pci1_dclk,conf_fail.EXP,clk,NOT porn,'0');
FDCPE_pci2_confn: FDCPE port map (pci2_confn,pci2_confn_D,clk,'0',NOT porn);
     pci2_confn_D <= (NOT ma(20) AND NOT ma(17) AND ma(16) AND ma(18) AND ma(19) AND
      ma(12) AND ma(13) AND ma(14) AND ma(15) AND NOT ma(10) AND NOT ma(11) AND
      ma(8) AND NOT ma(9) AND en_conf AND NOT powerondelay);
FDCPE_pci2_data: FDCPE port map (pci2_data,pci2_data_D,clk,'0','0',porn);
     pci2_data_D <= (mdq(0) AND NOT ma(20) AND ma(17) AND NOT ma(16) AND ma(18) AND
      ma(19) AND en_dclk);
FDCPE_pci2_dclk: FDCPE port map (pci2_dclk,pci2_dclk_D,clk,NOT porn,'0');
     pci2_dclk_D <= (NOT ma(20) AND ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND
      en_dclk AND NOT sp_o(1));
FDCPE_pci3_confn: FDCPE port map (pci3_confn,pci3_confn_D,clk,'0',NOT porn);
     pci3_confn_D <= ((NOT ma(20) AND NOT ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND
      NOT ma(12) AND ma(13) AND ma(14) AND ma(15) AND ma(10) AND ma(11) AND
      NOT pci3_done)
      OR (NOT ma(20) AND ma(17) AND ma(16) AND NOT ma(18) AND ma(19) AND
      ma(12) AND ma(13) AND ma(14) AND ma(15) AND NOT ma(10) AND NOT ma(11) AND
      ma(8) AND NOT ma(9) AND en_conf AND NOT powerondelay)
      OR (NOT ma(20) AND ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND
      ma(12) AND ma(13) AND ma(14) AND ma(15) AND NOT ma(10) AND NOT ma(11) AND
      ma(8) AND NOT ma(9) AND en_conf AND NOT powerondelay));
FDCPE_pci3_data: FDCPE port map (pci3_data,ver_sr(1).EXP,clk,'0','0',porn);
FDCPE_pci3_dclk: FDCPE port map (pci3_dclk,shift_addr.EXP,clk,NOT porn,'0');
FDCPE_powerondelay: FDCPE port map (powerondelay,'0',clk,'0',NOT porn,powerondelay_CE);
     powerondelay_CE <= (NOT ma(20) AND NOT ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND
      ma(12) AND ma(13) AND ma(14) AND ma(15) AND NOT ma(10) AND NOT ma(11) AND
      NOT ma(8) AND NOT ma(9) AND NOT sp_o(1));
FTCPE_re_conf: FTCPE port map (re_conf,re_conf_T,clk,'0','0');
     re_conf_T <= ((porn AND en_dclk AND re_conf AND NOT sp_o(1))
      OR (mdq(0) AND NOT mdq(1) AND mdq(2) AND NOT mdq(3) AND NOT mdq(4) AND
      mdq(5) AND NOT mdq(6) AND porn AND sp_o(0) AND flash_we_q AND sp_i(5) AND
      NOT re_conf AND NOT sp_o(1)));
FDCPE_shift_addr: FDCPE port map (shift_addr,shift_addr_D,clk,'0','0',shift_addr_CE);
     shift_addr_D <= (NOT en_conf AND pci3_done AND sp_i(0));
     shift_addr_CE <= (porn AND NOT sp_o(1));
FDCPE_shift_data: FDCPE port map (shift_data,sp_i(3),clk,NOT porn,'0',NOT sp_o(1));
FDCPE_sp_o0: FDCPE port map (sp_o(0),sp_o_D(0),clk,'0','0');
     sp_o_D(0) <= ((NOT porn AND sp_o(0))
      OR (sp_o(0) AND sp_o(1))
      OR (porn AND mdq2data AND mdq(7).PIN AND NOT sp_o(1))
      OR (NOT en_conf AND NOT mdq2data AND NOT shift_data AND sp_i(2) AND
      sp_o(0))
      OR (mdq(6) AND porn AND NOT en_conf AND NOT mdq2data AND
      shift_data AND NOT sp_o(1)));
FTCPE_sp_o1: FTCPE port map (sp_o(1),'1',clk,'0',NOT porn);
FTCPE_sp_o2: FTCPE port map (sp_o(2),sp_o_T(2),clk,'0','0');
     sp_o_T(2) <= ((porn AND mdq2data AND sp_o(2) AND NOT sp_o(1))
      OR (porn AND shift_data AND NOT ver_sr(5) AND sp_o(2) AND
      NOT sp_o(1))
      OR (porn AND NOT mdq2data AND shift_data AND ver_sr(5) AND
      NOT sp_o(2) AND NOT sp_o(1)));
sp_o(3) <= vtx_done;
FTCPE_ver_sr1: FTCPE port map (ver_sr(1),ver_sr_T(1),clk,'0','0');
     ver_sr_T(1) <= ((porn AND mdq2data AND NOT ver_sr(1) AND NOT sp_o(1))
      OR (porn AND NOT mdq2data AND shift_data AND ver_sr(1) AND
      NOT sp_o(1)));
FTCPE_ver_sr2: FTCPE port map (ver_sr(2),ver_sr_T(2),clk,'0','0');
     ver_sr_T(2) <= ((porn AND mdq2data AND ver_sr(2) AND NOT sp_o(1))
      OR (porn AND shift_data AND NOT ver_sr(1) AND ver_sr(2) AND
      NOT sp_o(1))
      OR (porn AND NOT mdq2data AND shift_data AND ver_sr(1) AND
      NOT ver_sr(2) AND NOT sp_o(1)));
FTCPE_ver_sr3: FTCPE port map (ver_sr(3),ver_sr_T(3),clk,'0','0');
     ver_sr_T(3) <= ((porn AND mdq2data AND ver_sr(3) AND NOT sp_o(1))
      OR (porn AND shift_data AND NOT ver_sr(2) AND ver_sr(3) AND
      NOT sp_o(1))
      OR (porn AND NOT mdq2data AND shift_data AND ver_sr(2) AND
      NOT ver_sr(3) AND NOT sp_o(1)));
FTCPE_ver_sr4: FTCPE port map (ver_sr(4),ver_sr_T(4),clk,'0','0');
     ver_sr_T(4) <= ((porn AND mdq2data AND ver_sr(4) AND NOT sp_o(1))
      OR (porn AND shift_data AND NOT ver_sr(3) AND ver_sr(4) AND
      NOT sp_o(1))
      OR (porn AND NOT mdq2data AND shift_data AND ver_sr(3) AND
      NOT ver_sr(4) AND NOT sp_o(1)));
FTCPE_ver_sr5: FTCPE port map (ver_sr(5),ver_sr_T(5),clk,'0','0');
     ver_sr_T(5) <= ((porn AND mdq2data AND ver_sr(5) AND NOT sp_o(1))
      OR (porn AND shift_data AND NOT ver_sr(4) AND ver_sr(5) AND
      NOT sp_o(1))
      OR (porn AND NOT mdq2data AND shift_data AND ver_sr(4) AND
      NOT ver_sr(5) AND NOT sp_o(1)));
FDCPE_vtx_clk: FDCPE port map (vtx_clk,vtx_clk_D,clk,'0',NOT porn);
     vtx_clk_D <= (ma(20) AND en_dclk AND sp_o(1));
FDCPE_vtx_confn: FDCPE port map (vtx_confn,vtx_confn_D,clk,'0',NOT porn);
     vtx_confn_D <= ((NOT ma(20) AND NOT ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND
      NOT ma(12) AND ma(13) AND ma(14) AND ma(15) AND ma(10) AND ma(11) AND
      NOT vtx_confn AND NOT pci3_done)
      OR (NOT ma(20) AND ma(17) AND ma(16) AND NOT ma(18) AND ma(19) AND
      ma(12) AND ma(13) AND ma(14) AND ma(15) AND NOT ma(10) AND NOT ma(11) AND
      ma(8) AND NOT ma(9) AND en_conf AND NOT powerondelay)
      OR (NOT ma(20) AND ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND
      ma(12) AND ma(13) AND ma(14) AND ma(15) AND NOT ma(10) AND NOT ma(11) AND
      ma(8) AND NOT ma(9) AND en_conf AND NOT powerondelay));
FDCPE_vtx_data: FDCPE port map (vtx_data,vtx_data_D,clk,'0','0',porn);
     vtx_data_D <= (mdq(0) AND ma(20) AND en_dclk);
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);