Timing Report

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Design Name dcc_conf
Device, Speed (SpeedFile Version) XC9572XL, -10 (3.0)
Date Created Thu Aug 30 16:48:39 2007
Created By Timing Report Generator: version J.38
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Performance Summary
Min. Clock Period 29.700 ns.
Max. Clock Frequency (fSYSTEM) 33.670 MHz.
Limited by Cycle Time for clk
Clock to Setup (tCYC) 29.700 ns.
Pad to Pad Delay (tPD) 20.000 ns.
Setup to Clock at the Pad (tSU) 13.400 ns.
Clock Pad to Output Pad Delay (tCO) 23.500 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS_clk 30.0 29.7 664 0


Constraint: TS_clk

Description: PERIOD:clk:30.000nS:HIGH:15.000nS
Path Requirement (ns) Delay (ns) Slack (ns)
mdq<3>_BUFR.Q to conf_fail.D 30.000 29.700 0.300
mdq<3>_BUFR.Q to mdq<4>_BUFR.D 30.000 29.700 0.300
mdq<4>_BUFR.Q to conf_fail.D 30.000 29.700 0.300



Number of constraints not met: 0

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
clk 33.670 Limited by Cycle Time for clk

Setup/Hold Times for Clocks

Setup/Hold Times for Clock clk
Source Pad Setup to clk (edge) Hold to clk (edge)
mdq<0> 12.000 0.000
mdq<1> 12.000 0.000
mdq<2> 12.000 0.000
mdq<3> 12.000 0.000
mdq<4> 12.000 0.000
mdq<5> 12.000 0.000
mdq<6> 12.000 0.000
mdq<7> 12.000 0.000
pci1_done 13.000 0.000
pci2_done 13.000 0.000
pci3_done 13.400 0.000
porn 13.000 0.000
sp_i<0> 12.000 0.000
sp_i<1> 12.000 0.000
sp_i<2> 13.000 0.000
sp_i<3> 12.000 0.000
sp_i<4> 13.000 0.000
sp_i<5> 13.000 0.000
sp_i<6> 12.000 0.000
vtx_done 13.000 0.000


Clock to Pad Timing

Clock clk to Pad
Destination Pad Clock (edge) to Pad
mdq<3> 23.500
mdq<4> 23.500
moen 23.500
mwen 23.500
mdq<0> 14.500
mdq<1> 14.500
mdq<2> 14.500
mdq<5> 14.500
mdq<6> 14.500
mdq<7> 14.500
ma<0> 10.300
ma<10> 10.300
ma<11> 10.300
ma<12> 10.300
ma<13> 10.300
ma<14> 10.300
ma<15> 10.300
ma<16> 10.300
ma<17> 10.300
ma<18> 10.300
ma<19> 10.300
ma<1> 10.300
ma<20> 10.300
ma<2> 10.300
ma<3> 10.300
ma<4> 10.300
ma<5> 10.300
ma<6> 10.300
ma<7> 10.300
ma<8> 10.300
ma<9> 10.300
pci1_confn 10.300
pci1_data 10.300
pci1_dclk 10.300
pci2_confn 10.300
pci2_data 10.300
pci2_dclk 10.300
pci3_confn 10.300
pci3_data 10.300
pci3_dclk 10.300
sp_o<0> 10.300
sp_o<2> 10.300
vtx_clk 10.300
vtx_confn 10.300
vtx_data 10.300
sp_o<1> 5.800


Clock to Setup Times for Clocks

Clock to Setup for clock clk
Source Destination Delay
mdq<3>_BUFR.Q conf_fail.D 29.700
mdq<3>_BUFR.Q mdq<4>_BUFR.D 29.700
mdq<4>_BUFR.Q conf_fail.D 29.700
mdq<4>_BUFR.Q mdq<4>_BUFR.D 29.700
mdq<4>_BUFR.Q mdq<5>.D 29.700
mdq<3>_BUFR.Q en_conf.D 28.700
mdq<3>_BUFR.Q mdq<2>.D 28.700
mdq<3>_BUFR.Q mdq<3>_BUFR.D 28.700
mdq<3>_BUFR.Q re_conf.D 28.700
mdq<4>_BUFR.Q en_conf.D 28.700
mdq<4>_BUFR.Q mdq<3>_BUFR.D 28.700
mdq<4>_BUFR.Q re_conf.D 28.700
conf_fail.Q en_conf.D 16.900
en_conf.Q en_conf.D 16.900
ma<16>.Q en_conf.D 16.900
ma<20>.Q en_conf.D 16.900
re_conf.Q en_conf.D 16.900
backup.Q mdq<6>.D 16.500
conf_fail.Q conf_fail.D 16.500
div8<0>.Q en_dclk.D 16.500
div8<1>.Q en_dclk.D 16.500
div8<2>.Q en_dclk.D 16.500
en_conf.Q en_dclk.D 16.500
en_conf.Q mdq<0>.D 16.500
en_conf.Q mdq<1>.D 16.500
en_conf.Q mdq<2>.D 16.500
en_conf.Q mdq<3>_BUFR.D 16.500
en_conf.Q mdq<4>_BUFR.D 16.500
en_conf.Q mdq<5>.D 16.500
en_conf.Q mdq<6>.D 16.500
en_conf.Q mdq<7>.D 16.500
en_dclk.Q en_dclk.D 16.500
en_dclk.Q pci1_dclk.D 16.500
en_dclk.Q pci3_data.D 16.500
en_dclk.Q pci3_dclk.D 16.500
flash_we_q.Q conf_fail.D 16.500
ma<0>.Q en_dclk.D 16.500
ma<10>.Q en_dclk.D 16.500
ma<10>.Q ma<10>.D 16.500
ma<11>.Q en_dclk.D 16.500
ma<12>.Q en_conf.D 16.500
ma<12>.Q en_dclk.D 16.500
ma<13>.Q en_conf.D 16.500
ma<13>.Q en_dclk.D 16.500
ma<14>.Q en_conf.D 16.500
ma<14>.Q en_dclk.D 16.500
ma<15>.Q en_conf.D 16.500
ma<15>.Q en_dclk.D 16.500
ma<16>.Q pci1_dclk.D 16.500
ma<16>.Q pci3_data.D 16.500
ma<16>.Q pci3_dclk.D 16.500
ma<17>.Q en_conf.D 16.500
ma<17>.Q pci1_dclk.D 16.500
ma<17>.Q pci3_data.D 16.500
ma<17>.Q pci3_dclk.D 16.500
ma<18>.Q pci1_dclk.D 16.500
ma<18>.Q pci3_data.D 16.500
ma<18>.Q pci3_dclk.D 16.500
ma<19>.Q pci1_dclk.D 16.500
ma<19>.Q pci3_data.D 16.500
ma<19>.Q pci3_dclk.D 16.500
ma<1>.Q en_dclk.D 16.500
ma<20>.Q pci1_dclk.D 16.500
ma<20>.Q pci3_data.D 16.500
ma<20>.Q pci3_dclk.D 16.500
ma<2>.Q en_dclk.D 16.500
ma<3>.Q en_dclk.D 16.500
ma<4>.Q en_dclk.D 16.500
ma<5>.Q en_dclk.D 16.500
ma<6>.Q en_dclk.D 16.500
ma<7>.Q en_dclk.D 16.500
ma<8>.Q en_dclk.D 16.500
ma<9>.Q en_dclk.D 16.500
ma<9>.Q ma<10>.D 16.500
mdq2data.Q mdq<0>.D 16.500
mdq2data.Q mdq<1>.D 16.500
mdq2data.Q mdq<2>.D 16.500
mdq2data.Q mdq<3>_BUFR.D 16.500
mdq2data.Q mdq<4>_BUFR.D 16.500
mdq2data.Q mdq<5>.D 16.500
mdq2data.Q mdq<6>.D 16.500
mdq2data.Q mdq<7>.D 16.500
mdq<0>.Q conf_fail.D 16.500
mdq<0>.Q mdq<0>.D 16.500
mdq<0>.Q mdq<1>.D 16.500
mdq<0>.Q pci3_data.D 16.500
mdq<1>.Q conf_fail.D 16.500
mdq<1>.Q mdq<1>.D 16.500
mdq<1>.Q mdq<2>.D 16.500
mdq<2>.Q conf_fail.D 16.500
mdq<2>.Q mdq<2>.D 16.500
mdq<2>.Q mdq<3>_BUFR.D 16.500
mdq<5>.Q conf_fail.D 16.500
mdq<5>.Q mdq<4>_BUFR.D 16.500
mdq<5>.Q mdq<5>.D 16.500
mdq<5>.Q mdq<6>.D 16.500
mdq<6>.Q conf_fail.D 16.500
mdq<6>.Q mdq<6>.D 16.500
mdq<6>.Q mdq<7>.D 16.500
powerondelay.Q en_conf.D 16.500
powerondelay.Q en_dclk.D 16.500
shift_addr.Q ma<10>.D 16.500
shift_data.Q mdq<0>.D 16.500
shift_data.Q mdq<1>.D 16.500
shift_data.Q mdq<2>.D 16.500
shift_data.Q mdq<3>_BUFR.D 16.500
shift_data.Q mdq<4>_BUFR.D 16.500
shift_data.Q mdq<5>.D 16.500
shift_data.Q mdq<6>.D 16.500
shift_data.Q mdq<7>.D 16.500
sp_o<0>.Q conf_fail.D 16.500
sp_o<1>.Q conf_fail.D 16.500
sp_o<1>.Q en_conf.D 16.500
sp_o<1>.Q en_dclk.D 16.500
sp_o<1>.Q ma<10>.D 16.500
sp_o<1>.Q mdq<0>.D 16.500
sp_o<1>.Q mdq<1>.D 16.500
sp_o<1>.Q mdq<2>.D 16.500
sp_o<1>.Q mdq<3>_BUFR.D 16.500
sp_o<1>.Q mdq<4>_BUFR.D 16.500
sp_o<1>.Q mdq<5>.D 16.500
sp_o<1>.Q mdq<6>.D 16.500
sp_o<1>.Q mdq<7>.D 16.500
sp_o<1>.Q pci1_dclk.D 16.500
sp_o<1>.Q pci3_dclk.D 16.500
backup.Q backup.D 15.500
conf_fail.Q backup.D 15.500
div8<0>.Q div8<0>.D 15.500
div8<0>.Q div8<1>.D 15.500
div8<0>.Q div8<2>.D 15.500
div8<0>.Q ma<0>.D 15.500
div8<0>.Q ma<10>.D 15.500
div8<0>.Q ma<11>.D 15.500
div8<0>.Q ma<12>.D 15.500
div8<0>.Q ma<13>.D 15.500
div8<0>.Q ma<14>.D 15.500
div8<0>.Q ma<15>.D 15.500
div8<0>.Q ma<16>.D 15.500
div8<0>.Q ma<17>.D 15.500
div8<0>.Q ma<18>.D 15.500
div8<0>.Q ma<19>.D 15.500
div8<0>.Q ma<1>.D 15.500
div8<0>.Q ma<20>.D 15.500
div8<0>.Q ma<2>.D 15.500
div8<0>.Q ma<3>.D 15.500
div8<0>.Q ma<4>.D 15.500
div8<0>.Q ma<5>.D 15.500
div8<0>.Q ma<6>.D 15.500
div8<0>.Q ma<7>.D 15.500
div8<0>.Q ma<8>.D 15.500
div8<0>.Q ma<9>.D 15.500
div8<0>.Q mdq2data.D 15.500
div8<1>.Q div8<1>.D 15.500
div8<1>.Q div8<2>.D 15.500
div8<1>.Q ma<0>.D 15.500
div8<1>.Q ma<10>.D 15.500
div8<1>.Q ma<11>.D 15.500
div8<1>.Q ma<12>.D 15.500
div8<1>.Q ma<13>.D 15.500
div8<1>.Q ma<14>.D 15.500
div8<1>.Q ma<15>.D 15.500
div8<1>.Q ma<16>.D 15.500
div8<1>.Q ma<17>.D 15.500
div8<1>.Q ma<18>.D 15.500
div8<1>.Q ma<19>.D 15.500
div8<1>.Q ma<1>.D 15.500
div8<1>.Q ma<20>.D 15.500
div8<1>.Q ma<2>.D 15.500
div8<1>.Q ma<3>.D 15.500
div8<1>.Q ma<4>.D 15.500
div8<1>.Q ma<5>.D 15.500
div8<1>.Q ma<6>.D 15.500
div8<1>.Q ma<7>.D 15.500
div8<1>.Q ma<8>.D 15.500
div8<1>.Q ma<9>.D 15.500
div8<1>.Q mdq2data.D 15.500
div8<2>.Q div8<2>.D 15.500
div8<2>.Q ma<0>.D 15.500
div8<2>.Q ma<10>.D 15.500
div8<2>.Q ma<11>.D 15.500
div8<2>.Q ma<12>.D 15.500
div8<2>.Q ma<13>.D 15.500
div8<2>.Q ma<14>.D 15.500
div8<2>.Q ma<15>.D 15.500
div8<2>.Q ma<16>.D 15.500
div8<2>.Q ma<17>.D 15.500
div8<2>.Q ma<18>.D 15.500
div8<2>.Q ma<19>.D 15.500
div8<2>.Q ma<1>.D 15.500
div8<2>.Q ma<20>.D 15.500
div8<2>.Q ma<2>.D 15.500
div8<2>.Q ma<3>.D 15.500
div8<2>.Q ma<4>.D 15.500
div8<2>.Q ma<5>.D 15.500
div8<2>.Q ma<6>.D 15.500
div8<2>.Q ma<7>.D 15.500
div8<2>.Q ma<8>.D 15.500
div8<2>.Q ma<9>.D 15.500
div8<2>.Q mdq2data.D 15.500
en_conf.Q backup.D 15.500
en_conf.Q div8<0>.D 15.500
en_conf.Q div8<1>.D 15.500
en_conf.Q div8<2>.D 15.500
en_conf.Q flash_we_q.D 15.500
en_conf.Q mdq2data.D 15.500
en_conf.Q pci1_confn.D 15.500
en_conf.Q pci2_confn.D 15.500
en_conf.Q pci3_confn.D 15.500
en_conf.Q shift_addr.D 15.500
en_conf.Q sp_o<0>.D 15.500
en_conf.Q vtx_confn.D 15.500
en_dclk.Q backup.D 15.500
en_dclk.Q en_conf.D 15.500
en_dclk.Q pci1_data.D 15.500
en_dclk.Q pci2_data.D 15.500
en_dclk.Q pci2_dclk.D 15.500
en_dclk.Q re_conf.D 15.500
en_dclk.Q vtx_clk.D 15.500
en_dclk.Q vtx_data.D 15.500
flash_we_q.Q en_conf.D 15.500
flash_we_q.Q re_conf.D 15.500
ma<0>.Q ma<0>.D 15.500
ma<0>.Q ma<10>.D 15.500
ma<0>.Q ma<11>.D 15.500
ma<0>.Q ma<12>.D 15.500
ma<0>.Q ma<13>.D 15.500
ma<0>.Q ma<14>.D 15.500
ma<0>.Q ma<15>.D 15.500
ma<0>.Q ma<16>.D 15.500
ma<0>.Q ma<17>.D 15.500
ma<0>.Q ma<18>.D 15.500
ma<0>.Q ma<19>.D 15.500
ma<0>.Q ma<1>.D 15.500
ma<0>.Q ma<20>.D 15.500
ma<0>.Q ma<2>.D 15.500
ma<0>.Q ma<3>.D 15.500
ma<0>.Q ma<4>.D 15.500
ma<0>.Q ma<5>.D 15.500
ma<0>.Q ma<6>.D 15.500
ma<0>.Q ma<7>.D 15.500
ma<0>.Q ma<8>.D 15.500
ma<0>.Q ma<9>.D 15.500
ma<10>.Q ma<11>.D 15.500
ma<10>.Q ma<12>.D 15.500
ma<10>.Q ma<13>.D 15.500
ma<10>.Q ma<14>.D 15.500
ma<10>.Q ma<15>.D 15.500
ma<10>.Q ma<16>.D 15.500
ma<10>.Q ma<17>.D 15.500
ma<10>.Q ma<18>.D 15.500
ma<10>.Q ma<19>.D 15.500
ma<10>.Q ma<20>.D 15.500
ma<10>.Q pci1_confn.D 15.500
ma<10>.Q pci2_confn.D 15.500
ma<10>.Q pci3_confn.D 15.500
ma<10>.Q vtx_confn.D 15.500
ma<11>.Q ma<11>.D 15.500
ma<11>.Q ma<12>.D 15.500
ma<11>.Q ma<13>.D 15.500
ma<11>.Q ma<14>.D 15.500
ma<11>.Q ma<15>.D 15.500
ma<11>.Q ma<16>.D 15.500
ma<11>.Q ma<17>.D 15.500
ma<11>.Q ma<18>.D 15.500
ma<11>.Q ma<19>.D 15.500
ma<11>.Q ma<20>.D 15.500
ma<11>.Q pci1_confn.D 15.500
ma<11>.Q pci2_confn.D 15.500
ma<11>.Q pci3_confn.D 15.500
ma<11>.Q vtx_confn.D 15.500
ma<12>.Q backup.D 15.500
ma<12>.Q ma<12>.D 15.500
ma<12>.Q ma<13>.D 15.500
ma<12>.Q ma<14>.D 15.500
ma<12>.Q ma<15>.D 15.500
ma<12>.Q ma<16>.D 15.500
ma<12>.Q ma<17>.D 15.500
ma<12>.Q ma<18>.D 15.500
ma<12>.Q ma<19>.D 15.500
ma<12>.Q ma<20>.D 15.500
ma<12>.Q pci1_confn.D 15.500
ma<12>.Q pci2_confn.D 15.500
ma<12>.Q pci3_confn.D 15.500
ma<12>.Q vtx_confn.D 15.500
ma<13>.Q backup.D 15.500
ma<13>.Q ma<13>.D 15.500
ma<13>.Q ma<14>.D 15.500
ma<13>.Q ma<15>.D 15.500
ma<13>.Q ma<16>.D 15.500
ma<13>.Q ma<17>.D 15.500
ma<13>.Q ma<18>.D 15.500
ma<13>.Q ma<19>.D 15.500
ma<13>.Q ma<20>.D 15.500
ma<13>.Q pci1_confn.D 15.500
ma<13>.Q pci2_confn.D 15.500
ma<13>.Q pci3_confn.D 15.500
ma<13>.Q vtx_confn.D 15.500
ma<14>.Q backup.D 15.500
ma<14>.Q ma<14>.D 15.500
ma<14>.Q ma<15>.D 15.500
ma<14>.Q ma<16>.D 15.500
ma<14>.Q ma<17>.D 15.500
ma<14>.Q ma<18>.D 15.500
ma<14>.Q ma<19>.D 15.500
ma<14>.Q ma<20>.D 15.500
ma<14>.Q pci1_confn.D 15.500
ma<14>.Q pci2_confn.D 15.500
ma<14>.Q pci3_confn.D 15.500
ma<14>.Q vtx_confn.D 15.500
ma<15>.Q backup.D 15.500
ma<15>.Q ma<15>.D 15.500
ma<15>.Q ma<16>.D 15.500
ma<15>.Q ma<17>.D 15.500
ma<15>.Q ma<18>.D 15.500
ma<15>.Q ma<19>.D 15.500
ma<15>.Q ma<20>.D 15.500
ma<15>.Q pci1_confn.D 15.500
ma<15>.Q pci2_confn.D 15.500
ma<15>.Q pci3_confn.D 15.500
ma<15>.Q vtx_confn.D 15.500
ma<16>.Q backup.D 15.500
ma<16>.Q ma<16>.D 15.500
ma<16>.Q ma<17>.D 15.500
ma<16>.Q ma<18>.D 15.500
ma<16>.Q ma<19>.D 15.500
ma<16>.Q ma<20>.D 15.500
ma<16>.Q pci1_confn.D 15.500
ma<16>.Q pci1_data.D 15.500
ma<16>.Q pci2_confn.D 15.500
ma<16>.Q pci2_data.D 15.500
ma<16>.Q pci2_dclk.D 15.500
ma<16>.Q pci3_confn.D 15.500
ma<16>.Q vtx_confn.D 15.500
ma<17>.Q backup.D 15.500
ma<17>.Q en_dclk.D 15.500
ma<17>.Q ma<17>.D 15.500
ma<17>.Q ma<18>.D 15.500
ma<17>.Q ma<19>.D 15.500
ma<17>.Q ma<20>.D 15.500
ma<17>.Q pci1_confn.D 15.500
ma<17>.Q pci1_data.D 15.500
ma<17>.Q pci2_confn.D 15.500
ma<17>.Q pci2_data.D 15.500
ma<17>.Q pci2_dclk.D 15.500
ma<17>.Q pci3_confn.D 15.500
ma<17>.Q vtx_confn.D 15.500
ma<18>.Q backup.D 15.500
ma<18>.Q en_conf.D 15.500
ma<18>.Q en_dclk.D 15.500
ma<18>.Q ma<18>.D 15.500
ma<18>.Q ma<19>.D 15.500
ma<18>.Q ma<20>.D 15.500
ma<18>.Q pci1_confn.D 15.500
ma<18>.Q pci1_data.D 15.500
ma<18>.Q pci2_confn.D 15.500
ma<18>.Q pci2_data.D 15.500
ma<18>.Q pci2_dclk.D 15.500
ma<18>.Q pci3_confn.D 15.500
ma<18>.Q vtx_confn.D 15.500
ma<19>.Q backup.D 15.500
ma<19>.Q en_conf.D 15.500
ma<19>.Q en_dclk.D 15.500
ma<19>.Q ma<19>.D 15.500
ma<19>.Q ma<20>.D 15.500
ma<19>.Q pci1_confn.D 15.500
ma<19>.Q pci1_data.D 15.500
ma<19>.Q pci2_confn.D 15.500
ma<19>.Q pci2_data.D 15.500
ma<19>.Q pci2_dclk.D 15.500
ma<19>.Q pci3_confn.D 15.500
ma<19>.Q vtx_confn.D 15.500
ma<1>.Q ma<10>.D 15.500
ma<1>.Q ma<11>.D 15.500
ma<1>.Q ma<12>.D 15.500
ma<1>.Q ma<13>.D 15.500
ma<1>.Q ma<14>.D 15.500
ma<1>.Q ma<15>.D 15.500
ma<1>.Q ma<16>.D 15.500
ma<1>.Q ma<17>.D 15.500
ma<1>.Q ma<18>.D 15.500
ma<1>.Q ma<19>.D 15.500
ma<1>.Q ma<1>.D 15.500
ma<1>.Q ma<20>.D 15.500
ma<1>.Q ma<2>.D 15.500
ma<1>.Q ma<3>.D 15.500
ma<1>.Q ma<4>.D 15.500
ma<1>.Q ma<5>.D 15.500
ma<1>.Q ma<6>.D 15.500
ma<1>.Q ma<7>.D 15.500
ma<1>.Q ma<8>.D 15.500
ma<1>.Q ma<9>.D 15.500
ma<20>.Q backup.D 15.500
ma<20>.Q conf_fail.D 15.500
ma<20>.Q en_dclk.D 15.500
ma<20>.Q ma<20>.D 15.500
ma<20>.Q pci1_confn.D 15.500
ma<20>.Q pci1_data.D 15.500
ma<20>.Q pci2_confn.D 15.500
ma<20>.Q pci2_data.D 15.500
ma<20>.Q pci2_dclk.D 15.500
ma<20>.Q pci3_confn.D 15.500
ma<20>.Q vtx_clk.D 15.500
ma<20>.Q vtx_confn.D 15.500
ma<20>.Q vtx_data.D 15.500
ma<2>.Q ma<10>.D 15.500
ma<2>.Q ma<11>.D 15.500
ma<2>.Q ma<12>.D 15.500
ma<2>.Q ma<13>.D 15.500
ma<2>.Q ma<14>.D 15.500
ma<2>.Q ma<15>.D 15.500
ma<2>.Q ma<16>.D 15.500
ma<2>.Q ma<17>.D 15.500
ma<2>.Q ma<18>.D 15.500
ma<2>.Q ma<19>.D 15.500
ma<2>.Q ma<20>.D 15.500
ma<2>.Q ma<2>.D 15.500
ma<2>.Q ma<3>.D 15.500
ma<2>.Q ma<4>.D 15.500
ma<2>.Q ma<5>.D 15.500
ma<2>.Q ma<6>.D 15.500
ma<2>.Q ma<7>.D 15.500
ma<2>.Q ma<8>.D 15.500
ma<2>.Q ma<9>.D 15.500
ma<3>.Q ma<10>.D 15.500
ma<3>.Q ma<11>.D 15.500
ma<3>.Q ma<12>.D 15.500
ma<3>.Q ma<13>.D 15.500
ma<3>.Q ma<14>.D 15.500
ma<3>.Q ma<15>.D 15.500
ma<3>.Q ma<16>.D 15.500
ma<3>.Q ma<17>.D 15.500
ma<3>.Q ma<18>.D 15.500
ma<3>.Q ma<19>.D 15.500
ma<3>.Q ma<20>.D 15.500
ma<3>.Q ma<3>.D 15.500
ma<3>.Q ma<4>.D 15.500
ma<3>.Q ma<5>.D 15.500
ma<3>.Q ma<6>.D 15.500
ma<3>.Q ma<7>.D 15.500
ma<3>.Q ma<8>.D 15.500
ma<3>.Q ma<9>.D 15.500
ma<4>.Q ma<10>.D 15.500
ma<4>.Q ma<11>.D 15.500
ma<4>.Q ma<12>.D 15.500
ma<4>.Q ma<13>.D 15.500
ma<4>.Q ma<14>.D 15.500
ma<4>.Q ma<15>.D 15.500
ma<4>.Q ma<16>.D 15.500
ma<4>.Q ma<17>.D 15.500
ma<4>.Q ma<18>.D 15.500
ma<4>.Q ma<19>.D 15.500
ma<4>.Q ma<20>.D 15.500
ma<4>.Q ma<4>.D 15.500
ma<4>.Q ma<5>.D 15.500
ma<4>.Q ma<6>.D 15.500
ma<4>.Q ma<7>.D 15.500
ma<4>.Q ma<8>.D 15.500
ma<4>.Q ma<9>.D 15.500
ma<5>.Q ma<10>.D 15.500
ma<5>.Q ma<11>.D 15.500
ma<5>.Q ma<12>.D 15.500
ma<5>.Q ma<13>.D 15.500
ma<5>.Q ma<14>.D 15.500
ma<5>.Q ma<15>.D 15.500
ma<5>.Q ma<16>.D 15.500
ma<5>.Q ma<17>.D 15.500
ma<5>.Q ma<18>.D 15.500
ma<5>.Q ma<19>.D 15.500
ma<5>.Q ma<20>.D 15.500
ma<5>.Q ma<5>.D 15.500
ma<5>.Q ma<6>.D 15.500
ma<5>.Q ma<7>.D 15.500
ma<5>.Q ma<8>.D 15.500
ma<5>.Q ma<9>.D 15.500
ma<6>.Q ma<10>.D 15.500
ma<6>.Q ma<11>.D 15.500
ma<6>.Q ma<12>.D 15.500
ma<6>.Q ma<13>.D 15.500
ma<6>.Q ma<14>.D 15.500
ma<6>.Q ma<15>.D 15.500
ma<6>.Q ma<16>.D 15.500
ma<6>.Q ma<17>.D 15.500
ma<6>.Q ma<18>.D 15.500
ma<6>.Q ma<19>.D 15.500
ma<6>.Q ma<20>.D 15.500
ma<6>.Q ma<6>.D 15.500
ma<6>.Q ma<7>.D 15.500
ma<6>.Q ma<8>.D 15.500
ma<6>.Q ma<9>.D 15.500
ma<7>.Q ma<10>.D 15.500
ma<7>.Q ma<11>.D 15.500
ma<7>.Q ma<12>.D 15.500
ma<7>.Q ma<13>.D 15.500
ma<7>.Q ma<14>.D 15.500
ma<7>.Q ma<15>.D 15.500
ma<7>.Q ma<16>.D 15.500
ma<7>.Q ma<17>.D 15.500
ma<7>.Q ma<18>.D 15.500
ma<7>.Q ma<19>.D 15.500
ma<7>.Q ma<20>.D 15.500
ma<7>.Q ma<7>.D 15.500
ma<7>.Q ma<8>.D 15.500
ma<7>.Q ma<9>.D 15.500
ma<8>.Q ma<10>.D 15.500
ma<8>.Q ma<11>.D 15.500
ma<8>.Q ma<12>.D 15.500
ma<8>.Q ma<13>.D 15.500
ma<8>.Q ma<14>.D 15.500
ma<8>.Q ma<15>.D 15.500
ma<8>.Q ma<16>.D 15.500
ma<8>.Q ma<17>.D 15.500
ma<8>.Q ma<18>.D 15.500
ma<8>.Q ma<19>.D 15.500
ma<8>.Q ma<20>.D 15.500
ma<8>.Q ma<8>.D 15.500
ma<8>.Q ma<9>.D 15.500
ma<8>.Q pci1_confn.D 15.500
ma<8>.Q pci2_confn.D 15.500
ma<8>.Q pci3_confn.D 15.500
ma<8>.Q vtx_confn.D 15.500
ma<9>.Q ma<11>.D 15.500
ma<9>.Q ma<12>.D 15.500
ma<9>.Q ma<13>.D 15.500
ma<9>.Q ma<14>.D 15.500
ma<9>.Q ma<15>.D 15.500
ma<9>.Q ma<16>.D 15.500
ma<9>.Q ma<17>.D 15.500
ma<9>.Q ma<18>.D 15.500
ma<9>.Q ma<19>.D 15.500
ma<9>.Q ma<20>.D 15.500
ma<9>.Q ma<9>.D 15.500
ma<9>.Q pci1_confn.D 15.500
ma<9>.Q pci2_confn.D 15.500
ma<9>.Q pci3_confn.D 15.500
ma<9>.Q vtx_confn.D 15.500
mdq2data.Q sp_o<0>.D 15.500
mdq2data.Q sp_o<2>.D 15.500
mdq2data.Q ver_sr<1>.D 15.500
mdq2data.Q ver_sr<2>.D 15.500
mdq2data.Q ver_sr<3>.D 15.500
mdq2data.Q ver_sr<4>.D 15.500
mdq2data.Q ver_sr<5>.D 15.500
mdq<0>.Q en_conf.D 15.500
mdq<0>.Q pci1_data.D 15.500
mdq<0>.Q pci2_data.D 15.500
mdq<0>.Q re_conf.D 15.500
mdq<0>.Q vtx_data.D 15.500
mdq<1>.Q en_conf.D 15.500
mdq<1>.Q mdq<0>.D 15.500
mdq<1>.Q re_conf.D 15.500
mdq<2>.Q en_conf.D 15.500
mdq<2>.Q mdq<1>.D 15.500
mdq<2>.Q re_conf.D 15.500
mdq<5>.Q en_conf.D 15.500
mdq<5>.Q re_conf.D 15.500
mdq<6>.Q en_conf.D 15.500
mdq<6>.Q mdq<5>.D 15.500
mdq<6>.Q re_conf.D 15.500
mdq<6>.Q sp_o<0>.D 15.500
mdq<7>.Q mdq<7>.D 15.500
powerondelay.Q backup.D 15.500
powerondelay.Q conf_fail.D 15.500
powerondelay.Q mdq2data.D 15.500
powerondelay.Q pci1_confn.D 15.500
powerondelay.Q pci2_confn.D 15.500
powerondelay.Q pci3_confn.D 15.500
powerondelay.Q vtx_confn.D 15.500
re_conf.Q backup.D 15.500
re_conf.Q re_conf.D 15.500
shift_addr.Q ma<0>.D 15.500
shift_addr.Q ma<11>.D 15.500
shift_addr.Q ma<12>.D 15.500
shift_addr.Q ma<13>.D 15.500
shift_addr.Q ma<14>.D 15.500
shift_addr.Q ma<15>.D 15.500
shift_addr.Q ma<16>.D 15.500
shift_addr.Q ma<17>.D 15.500
shift_addr.Q ma<18>.D 15.500
shift_addr.Q ma<19>.D 15.500
shift_addr.Q ma<1>.D 15.500
shift_addr.Q ma<20>.D 15.500
shift_addr.Q ma<2>.D 15.500
shift_addr.Q ma<3>.D 15.500
shift_addr.Q ma<4>.D 15.500
shift_addr.Q ma<5>.D 15.500
shift_addr.Q ma<6>.D 15.500
shift_addr.Q ma<7>.D 15.500
shift_addr.Q ma<8>.D 15.500
shift_addr.Q ma<9>.D 15.500
shift_data.Q flash_we_q.D 15.500
shift_data.Q sp_o<0>.D 15.500
shift_data.Q sp_o<2>.D 15.500
shift_data.Q ver_sr<1>.D 15.500
shift_data.Q ver_sr<2>.D 15.500
shift_data.Q ver_sr<3>.D 15.500
shift_data.Q ver_sr<4>.D 15.500
shift_data.Q ver_sr<5>.D 15.500
sp_o<0>.Q en_conf.D 15.500
sp_o<0>.Q mdq<6>.D 15.500
sp_o<0>.Q re_conf.D 15.500
sp_o<0>.Q sp_o<0>.D 15.500
sp_o<1>.Q backup.D 15.500
sp_o<1>.Q ma<0>.D 15.500
sp_o<1>.Q ma<11>.D 15.500
sp_o<1>.Q ma<12>.D 15.500
sp_o<1>.Q ma<13>.D 15.500
sp_o<1>.Q ma<14>.D 15.500
sp_o<1>.Q ma<15>.D 15.500
sp_o<1>.Q ma<16>.D 15.500
sp_o<1>.Q ma<17>.D 15.500
sp_o<1>.Q ma<18>.D 15.500
sp_o<1>.Q ma<19>.D 15.500
sp_o<1>.Q ma<1>.D 15.500
sp_o<1>.Q ma<20>.D 15.500
sp_o<1>.Q ma<2>.D 15.500
sp_o<1>.Q ma<3>.D 15.500
sp_o<1>.Q ma<4>.D 15.500
sp_o<1>.Q ma<5>.D 15.500
sp_o<1>.Q ma<6>.D 15.500
sp_o<1>.Q ma<7>.D 15.500
sp_o<1>.Q ma<8>.D 15.500
sp_o<1>.Q ma<9>.D 15.500
sp_o<1>.Q pci2_dclk.D 15.500
sp_o<1>.Q re_conf.D 15.500
sp_o<1>.Q sp_o<0>.D 15.500
sp_o<1>.Q sp_o<2>.D 15.500
sp_o<1>.Q ver_sr<1>.D 15.500
sp_o<1>.Q ver_sr<2>.D 15.500
sp_o<1>.Q ver_sr<3>.D 15.500
sp_o<1>.Q ver_sr<4>.D 15.500
sp_o<1>.Q ver_sr<5>.D 15.500
sp_o<1>.Q vtx_clk.D 15.500
sp_o<2>.Q sp_o<2>.D 15.500
ver_sr<1>.Q ver_sr<1>.D 15.500
ver_sr<1>.Q ver_sr<2>.D 15.500
ver_sr<2>.Q ver_sr<2>.D 15.500
ver_sr<2>.Q ver_sr<3>.D 15.500
ver_sr<3>.Q ver_sr<3>.D 15.500
ver_sr<3>.Q ver_sr<4>.D 15.500
ver_sr<4>.Q ver_sr<4>.D 15.500
ver_sr<4>.Q ver_sr<5>.D 15.500
ver_sr<5>.Q sp_o<2>.D 15.500
ver_sr<5>.Q ver_sr<5>.D 15.500
vtx_confn.Q vtx_confn.D 15.500
ma<10>.Q powerondelay.CE 10.000
ma<11>.Q powerondelay.CE 10.000
ma<12>.Q powerondelay.CE 10.000
ma<13>.Q powerondelay.CE 10.000
ma<14>.Q powerondelay.CE 10.000
ma<15>.Q powerondelay.CE 10.000
ma<16>.Q powerondelay.CE 10.000
ma<17>.Q powerondelay.CE 10.000
ma<18>.Q powerondelay.CE 10.000
ma<19>.Q powerondelay.CE 10.000
ma<20>.Q powerondelay.CE 10.000
ma<8>.Q powerondelay.CE 10.000
ma<9>.Q powerondelay.CE 10.000
sp_o<1>.Q div8<0>.CE 10.000
sp_o<1>.Q div8<1>.CE 10.000
sp_o<1>.Q div8<2>.CE 10.000
sp_o<1>.Q mdq2data.CE 10.000
sp_o<1>.Q powerondelay.CE 10.000
sp_o<1>.Q shift_addr.CE 10.000
sp_o<1>.Q shift_data.CE 10.000


Pad to Pad List

Source Pad Destination Pad Delay
pci3_done moen 20.000
pci3_done mwen 20.000
porn mrstn 20.000
sp_i<2> moen 20.000
sp_i<2> mwen 20.000
vtx_done sp_o<3> 20.000
clk dcc_clk 15.500



Number of paths analyzed: 664
Number of Timing errors: 0
Analysis Completed: Thu Aug 30 16:48:39 2007