cpldfit: version J.38 Xilinx Inc. Fitter Report Design Name: dcc_conf Date: 8-30-2007, 4:48PM Device Used: XC9572XL-10-TQ100 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 70 /72 ( 97%) 262 /360 ( 73%) 179/216 ( 83%) 62 /72 ( 86%) 63 /72 ( 87%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 17/18 47/54 68/90 10/18 FB2 18/18* 42/54 68/90 18/18* FB3 17/18 43/54 67/90 9/18 FB4 18/18* 47/54 59/90 13/18 ----- ----- ----- ----- 70/72 179/216 262/360 50/72 * - Resource is exhausted ** Global Control Resources ** Signal 'clk' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 12 12 | I/O : 57 66 Output : 42 42 | GCK/IO : 3 3 Bidirectional : 8 8 | GTS/IO : 2 2 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 63 63 ** Power Data ** There are 0 macrocells in high performance mode (MCHP). There are 70 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld:1007 - Removing unused input(s) 'sp_i<7>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:896 - Unable to map all desired signals into function block, FB2, because too many function block product terms are required. Buffering output signal mdq<4> to allow all signals assigned to this function block to be placed. WARNING:Cpld:896 - Unable to map all desired signals into function block, FB2, because too many function block product terms are required. Buffering output signal mdq<3> to allow all signals assigned to this function block to be placed. ************************* Summary of Mapped Logic ************************ ** 50 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State ma<10> 4 17 FB1_1 16 I/O O LOW SLOW RESET mdq<5> 8 12 FB1_2 13 I/O I/O LOW SLOW RESET ma<17> 4 24 FB1_3 18 I/O O LOW SLOW RESET mdq<6> 8 12 FB1_5 14 I/O I/O LOW SLOW RESET mdq<7> 6 10 FB1_6 15 I/O I/O LOW SLOW RESET ma<20> 4 28 FB1_8 17 I/O O LOW SLOW RESET pci2_confn 2 16 FB1_10 28 I/O O LOW SLOW SET ma<19> 4 26 FB1_11 23 GCK/I/O O LOW SLOW SET pci2_data 2 8 FB1_15 29 I/O O LOW SLOW RESET pci2_dclk 2 8 FB1_17 30 I/O O LOW SLOW RESET ma<9> 4 16 FB2_1 87 I/O O LOW SLOW RESET ma<6> 4 13 FB2_2 94 I/O O LOW SLOW RESET mrstn 1 1 FB2_3 91 I/O O LOW SLOW ma<7> 4 14 FB2_4 93 I/O O LOW SLOW RESET ma<5> 4 12 FB2_5 95 I/O O LOW SLOW RESET ma<4> 4 11 FB2_6 96 I/O O LOW SLOW RESET ma<1> 4 8 FB2_7 3 GTS/I/O O LOW SLOW RESET ma<3> 4 10 FB2_8 97 I/O O LOW SLOW RESET ma<2> 4 9 FB2_9 99 GSR/I/O O LOW SLOW RESET ma<0> 4 8 FB2_10 1 I/O O LOW SLOW RESET mcen 0 0 FB2_11 4 GTS/I/O O LOW SLOW moen 1 3 FB2_12 6 I/O O LOW SLOW mdq<0> 7 11 FB2_13 8 I/O I/O LOW SLOW RESET mdq<1> 7 11 FB2_14 9 I/O I/O LOW SLOW RESET mdq<3> 2 2 FB2_15 11 I/O I/O LOW SLOW mdq<2> 8 12 FB2_16 10 I/O I/O LOW SLOW RESET mdq<4> 2 2 FB2_17 12 I/O I/O LOW SLOW ma<18> 4 25 FB2_18 92 I/O O LOW SLOW SET vtx_confn 4 18 FB3_2 32 I/O O LOW SLOW SET dcc_clk 1 1 FB3_4 50 I/O O LOW FAST vtx_clk 2 4 FB3_5 35 I/O O LOW SLOW SET pci1_confn 2 16 FB3_6 53 I/O O LOW SLOW SET pci1_data 2 8 FB3_7 54 I/O O LOW SLOW RESET vtx_data 2 4 FB3_8 37 I/O O LOW SLOW RESET pci1_dclk 2 8 FB3_11 52 I/O O LOW SLOW RESET pci3_data 3 8 FB3_15 56 I/O O LOW SLOW RESET pci3_dclk 3 8 FB3_18 59 I/O O LOW SLOW RESET sp_o<0> 5 9 FB4_3 71 I/O O LOW SLOW RESET pci3_confn 4 17 FB4_4 72 I/O O LOW SLOW SET sp_o<2> 3 6 FB4_6 76 I/O O LOW SLOW RESET Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State sp_o<3> 1 1 FB4_7 77 I/O O LOW SLOW ma<14> 4 21 FB4_10 81 I/O O LOW SLOW SET sp_o<1> 1 1 FB4_11 74 I/O O LOW FAST SET ma<13> 4 20 FB4_12 82 I/O O LOW SLOW SET ma<12> 4 19 FB4_13 85 I/O O LOW SLOW SET ma<15> 4 22 FB4_14 78 I/O O LOW SLOW SET ma<8> 4 15 FB4_15 89 I/O O LOW SLOW SET ma<11> 4 18 FB4_16 86 I/O O LOW SLOW RESET mwen 1 4 FB4_17 90 I/O O LOW SLOW ma<16> 4 23 FB4_18 79 I/O O LOW SLOW RESET ** 20 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State powerondelay 2 15 FB1_7 LOW SET flash_we_q 2 5 FB1_9 LOW RESET div8<0> 3 4 FB1_12 LOW RESET mdq2data 4 9 FB1_13 LOW RESET div8<2> 4 6 FB1_14 LOW RESET div8<1> 4 5 FB1_16 LOW RESET en_dclk 5 28 FB1_18 LOW RESET shift_addr 2 5 FB3_1 LOW RESET re_conf 2 14 FB3_3 LOW RESET shift_data 3 3 FB3_9 LOW RESET conf_fail 5 16 FB3_10 LOW RESET mdq<4>_BUFR 7 11 FB3_12 LOW RESET mdq<3>_BUFR 7 11 FB3_13 LOW RESET ver_sr<1> 2 5 FB3_14 LOW RESET en_conf 18 27 FB3_17 LOW SET ver_sr<5> 3 6 FB4_1 LOW RESET ver_sr<4> 3 6 FB4_2 LOW RESET ver_sr<3> 3 6 FB4_5 LOW RESET ver_sr<2> 3 6 FB4_8 LOW RESET backup 4 18 FB4_9 LOW RESET ** 13 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use porn FB1_4 20 I/O I clk FB1_9 22 GCK/I/O GCK/I vtx_done FB1_12 33 I/O I pci2_done FB1_14 27 GCK/I/O I sp_i<0> FB3_10 60 I/O I sp_i<1> FB3_12 61 I/O I sp_i<2> FB3_13 63 I/O I pci1_done FB3_14 55 I/O I sp_i<3> FB3_16 64 I/O I pci3_done FB3_17 58 I/O I sp_i<4> FB4_1 65 I/O I sp_i<6> FB4_2 67 I/O I sp_i<5> FB4_9 66 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 47/7 Number of signals used by logic mapping into function block: 47 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use ma<10> 4 1<- \/2 0 FB1_1 16 I/O O mdq<5> 8 3<- 0 0 FB1_2 13 I/O I/O ma<17> 4 0 /\1 0 FB1_3 18 I/O O (unused) 0 0 \/3 2 FB1_4 20 I/O I mdq<6> 8 3<- 0 0 FB1_5 14 I/O I/O mdq<7> 6 1<- 0 0 FB1_6 15 I/O I/O powerondelay 2 0 /\1 2 FB1_7 25 I/O (b) ma<20> 4 0 0 1 FB1_8 17 I/O O flash_we_q 2 0 0 3 FB1_9 22 GCK/I/O GCK/I pci2_confn 2 0 0 3 FB1_10 28 I/O O ma<19> 4 0 0 1 FB1_11 23 GCK/I/O O div8<0> 3 0 0 2 FB1_12 33 I/O I mdq2data 4 0 0 1 FB1_13 36 I/O (b) div8<2> 4 0 0 1 FB1_14 27 GCK/I/O I pci2_data 2 0 0 3 FB1_15 29 I/O O div8<1> 4 0 0 1 FB1_16 39 I/O (b) pci2_dclk 2 0 \/1 2 FB1_17 30 I/O O en_dclk 5 1<- \/1 0 FB1_18 40 I/O (b) Signals Used by Logic in Function Block 1: mdq<7>.PIN 17: ma<15> 33: mdq<0> 2: mdq<6>.PIN 18: ma<16> 34: mdq<4> 3: mdq<5>.PIN 19: ma<17> 35: mdq<5> 4: backup 20: ma<18> 36: mdq<6> 5: div8<0> 21: ma<19> 37: mdq<7> 6: div8<1> 22: ma<1> 38: porn 7: div8<2> 23: ma<20> 39: pci3_done 8: en_conf 24: ma<2> 40: powerondelay 9: en_dclk 25: ma<3> 41: shift_addr 10: flash_we_q 26: ma<4> 42: shift_data 11: ma<0> 27: ma<5> 43: sp_i<1> 12: ma<10> 28: ma<6> 44: sp_i<2> 13: ma<11> 29: ma<7> 45: sp_i<6> 14: ma<12> 30: ma<8> 46: sp_o<0> 15: ma<13> 31: ma<9> 47: sp_o<1> 16: ma<14> 32: mdq2data Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs ma<10> ....XXX...XX.........X.XXXXXXXX......X..X.....X... 17 mdq<5> ..X....X.X.....................X.XXX.XX..X.X..X... 12 ma<17> ....XXX...XXXXXXXXX..X.XXXXXXXX......X..X.....X... 24 mdq<6> .X.X...X.X.....................X..XX.X...X.X.XX... 12 mdq<7> X......X.X.....................X...XXX...X.X..X... 10 powerondelay ...........XXXXXXXXXX.X......XX......X........X... 15 ma<20> ....XXX...XXXXXXXXXXXXXXXXXXXXX......X..X...X.X... 28 flash_we_q .......X.............................XX..X.X...... 5 pci2_confn .......X...XXXXXXXXXX.X......XX......X.X.......... 16 ma<19> ....XXX...XXXXXXXXXXXX.XXXXXXXX......X..X.....X... 26 div8<0> ....X..X.............................X........X... 4 mdq2data ....XXXX.............................XXX..X...X... 9 div8<2> ....XXXX.............................X........X... 6 pci2_data ........X........XXXX.X.........X....X............ 8 div8<1> ....XX.X.............................X........X... 5 pci2_dclk ........X........XXXX.X..............X........X... 8 en_dclk ....XXXXX.XXXXXXX.XXXXXXXXXXXXX......X.X......X... 28 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 42/12 Number of signals used by logic mapping into function block: 42 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use ma<9> 4 0 0 1 FB2_1 87 I/O O ma<6> 4 0 0 1 FB2_2 94 I/O O mrstn 1 0 0 4 FB2_3 91 I/O O ma<7> 4 0 0 1 FB2_4 93 I/O O ma<5> 4 0 0 1 FB2_5 95 I/O O ma<4> 4 0 0 1 FB2_6 96 I/O O ma<1> 4 0 0 1 FB2_7 3 GTS/I/O O ma<3> 4 0 0 1 FB2_8 97 I/O O ma<2> 4 0 0 1 FB2_9 99 GSR/I/O O ma<0> 4 0 0 1 FB2_10 1 I/O O mcen 0 0 0 5 FB2_11 4 GTS/I/O O moen 1 0 \/2 2 FB2_12 6 I/O O mdq<0> 7 2<- 0 0 FB2_13 8 I/O I/O mdq<1> 7 2<- 0 0 FB2_14 9 I/O I/O mdq<3> 2 0 /\2 1 FB2_15 11 I/O I/O mdq<2> 8 3<- 0 0 FB2_16 10 I/O I/O mdq<4> 2 0 /\3 0 FB2_17 12 I/O I/O ma<18> 4 0 0 1 FB2_18 92 I/O O Signals Used by Logic in Function Block 1: mdq<2>.PIN 15: ma<15> 29: mdq<0> 2: mdq<1>.PIN 16: ma<16> 30: mdq<1> 3: mdq<0>.PIN 17: ma<17> 31: mdq<2> 4: div8<0> 18: ma<18> 32: mdq<3> 5: div8<1> 19: ma<1> 33: mdq<3>_BUFR 6: div8<2> 20: ma<2> 34: mdq<4>_BUFR 7: en_conf 21: ma<3> 35: porn 8: flash_we_q 22: ma<4> 36: pci3_done 9: ma<0> 23: ma<5> 37: shift_addr 10: ma<10> 24: ma<6> 38: shift_data 11: ma<11> 25: ma<7> 39: sp_i<2> 12: ma<12> 26: ma<8> 40: sp_i<4> 13: ma<13> 27: ma<9> 41: sp_o<1> 14: ma<14> 28: mdq2data 42: vtx_done Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs ma<9> ...XXX..X.........XXXXXXXXX.......X.X...X......... 16 ma<6> ...XXX..X.........XXXXXX..........X.X...X......... 13 mrstn ..................................X............... 1 ma<7> ...XXX..X.........XXXXXXX.........X.X...X......... 14 ma<5> ...XXX..X.........XXXXX...........X.X...X......... 12 ma<4> ...XXX..X.........XXXX............X.X...X......... 11 ma<1> ...XXX..X.........X...............X.X...X......... 8 ma<3> ...XXX..X.........XXX.............X.X...X......... 10 ma<2> ...XXX..X.........XX..............X.X...X......... 9 ma<0> ...XXX..X.........................X.X..XX......... 8 mcen .................................................. 0 moen ......X............................X..X........... 3 mdq<0> ..X...XX...................XXX....X..XXXX......... 11 mdq<1> .X....XX...................XXXX...X..XX.X......... 11 mdq<3> .......X........................X................. 2 mdq<2> X.....XX...................X.XXX..X..XX.XX........ 12 mdq<4> .......X.........................X................ 2 ma<18> ...XXX..XXXXXXXXXXXXXXXXXXX.......X.X...X......... 25 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 43/11 Number of signals used by logic mapping into function block: 43 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use shift_addr 2 0 /\2 1 FB3_1 41 I/O (b) vtx_confn 4 0 0 1 FB3_2 32 I/O O re_conf 2 0 0 3 FB3_3 49 I/O (b) dcc_clk 1 0 0 4 FB3_4 50 I/O O vtx_clk 2 0 0 3 FB3_5 35 I/O O pci1_confn 2 0 0 3 FB3_6 53 I/O O pci1_data 2 0 0 3 FB3_7 54 I/O O vtx_data 2 0 0 3 FB3_8 37 I/O O shift_data 3 0 \/1 1 FB3_9 42 I/O (b) conf_fail 5 1<- \/1 0 FB3_10 60 I/O I pci1_dclk 2 1<- \/4 0 FB3_11 52 I/O O mdq<4>_BUFR 7 4<- \/2 0 FB3_12 61 I/O I mdq<3>_BUFR 7 2<- 0 0 FB3_13 63 I/O I ver_sr<1> 2 0 \/2 1 FB3_14 55 I/O I pci3_data 3 2<- \/4 0 FB3_15 56 I/O O (unused) 0 0 \/5 0 FB3_16 64 I/O I en_conf 18 13<- 0 0 FB3_17 58 I/O I pci3_dclk 3 2<- /\4 0 FB3_18 59 I/O O Signals Used by Logic in Function Block 1: mdq<4>.PIN 16: ma<18> 30: pci1_done 2: mdq<3>.PIN 17: ma<19> 31: pci2_done 3: conf_fail 18: ma<20> 32: pci3_done 4: clk 19: ma<8> 33: powerondelay 5: en_conf 20: ma<9> 34: re_conf 6: en_dclk 21: mdq2data 35: shift_data 7: flash_we_q 22: mdq<0> 36: sp_i<0> 8: ma<10> 23: mdq<1> 37: sp_i<2> 9: ma<11> 24: mdq<2> 38: sp_i<3> 10: ma<12> 25: mdq<3> 39: sp_i<5> 11: ma<13> 26: mdq<4> 40: sp_o<0> 12: ma<14> 27: mdq<5> 41: sp_o<1> 13: ma<15> 28: mdq<6> 42: ver_sr<1> 14: ma<16> 29: porn 43: vtx_confn 15: ma<17> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs shift_addr ....X.......................X..X...X....X......... 5 vtx_confn ....X..XXXXXXXXXXXXX........X..XX.........X....... 18 re_conf .....XX..............XXXXXXXX....X....XXX......... 14 dcc_clk ...X.............................................. 1 vtx_clk .....X...........X..........X...........X......... 4 pci1_confn ....X..XXXXXXXXXXXXX........X...X................. 16 pci1_data .....X.......XXXXX...X......X..................... 8 vtx_data .....X...........X...X......X..................... 4 shift_data ............................X........X..X......... 3 conf_fail ..X...X..........X...XXXXXXXX..XX.....XXX......... 16 pci1_dclk .....X.......XXXXX..........X...........X......... 8 mdq<4>_BUFR X...X...............X...XXX.X.X...X.X...X......... 11 mdq<3>_BUFR .X..X...............X..XXX..XX....X.X...X......... 11 ver_sr<1> ....................X.......X.....X.....XX........ 5 pci3_data .....X.......XXXXX...X......X..................... 8 en_conf ..X.XXX..XXXXXXXXX...XXXXXXXX..XXX....XXX......... 27 pci3_dclk .....X.......XXXXX..........X...........X......... 8 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 47/7 Number of signals used by logic mapping into function block: 47 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use ver_sr<5> 3 0 0 2 FB4_1 65 I/O I ver_sr<4> 3 0 0 2 FB4_2 67 I/O I sp_o<0> 5 0 0 0 FB4_3 71 I/O O pci3_confn 4 0 0 1 FB4_4 72 I/O O ver_sr<3> 3 0 0 2 FB4_5 68 I/O (b) sp_o<2> 3 0 0 2 FB4_6 76 I/O O sp_o<3> 1 0 0 4 FB4_7 77 I/O O ver_sr<2> 3 0 0 2 FB4_8 70 I/O (b) backup 4 0 0 1 FB4_9 66 I/O I ma<14> 4 0 0 1 FB4_10 81 I/O O sp_o<1> 1 0 0 4 FB4_11 74 I/O O ma<13> 4 0 0 1 FB4_12 82 I/O O ma<12> 4 0 0 1 FB4_13 85 I/O O ma<15> 4 0 0 1 FB4_14 78 I/O O ma<8> 4 0 0 1 FB4_15 89 I/O O ma<11> 4 0 0 1 FB4_16 86 I/O O mwen 1 0 0 4 FB4_17 90 I/O O ma<16> 4 0 0 1 FB4_18 79 I/O O Signals Used by Logic in Function Block 1: mdq<7>.PIN 17: ma<17> 33: pci3_done 2: backup 18: ma<18> 34: powerondelay 3: conf_fail 19: ma<19> 35: re_conf 4: div8<0> 20: ma<1> 36: shift_addr 5: div8<1> 21: ma<20> 37: shift_data 6: div8<2> 22: ma<2> 38: sp_i<2> 7: en_conf 23: ma<3> 39: sp_o<0> 8: en_dclk 24: ma<4> 40: sp_o<1> 9: ma<0> 25: ma<5> 41: sp_o<2> 10: ma<10> 26: ma<6> 42: ver_sr<1> 11: ma<11> 27: ma<7> 43: ver_sr<2> 12: ma<12> 28: ma<8> 44: ver_sr<3> 13: ma<13> 29: ma<9> 45: ver_sr<4> 14: ma<14> 30: mdq2data 46: ver_sr<5> 15: ma<15> 31: mdq<6> 47: vtx_done 16: ma<16> 32: porn Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs ver_sr<5> .............................X.X....X..X....XX.... 6 ver_sr<4> .............................X.X....X..X...XX..... 6 sp_o<0> X.....X......................XXX....XXXX.......... 9 pci3_confn ......X..XXXXXXXXXX.X......XX..XXX................ 17 ver_sr<3> .............................X.X....X..X..XX...... 6 sp_o<2> .............................X.X....X..XX....X.... 6 sp_o<3> ..............................................X... 1 ver_sr<2> .............................X.X....X..X.XX....... 6 backup .XX...XX...XXXXXXXX.X..........XXXX....X.......... 18 ma<14> ...XXX..XXXXXX.....X.XXXXXXXX..X...X...X.......... 21 sp_o<1> ...............................X.................. 1 ma<13> ...XXX..XXXXX......X.XXXXXXXX..X...X...X.......... 20 ma<12> ...XXX..XXXX.......X.XXXXXXXX..X...X...X.......... 19 ma<15> ...XXX..XXXXXXX....X.XXXXXXXX..X...X...X.......... 22 ma<8> ...XXX..X..........X.XXXXXXX...X...X...X.......... 15 ma<11> ...XXX..XXX........X.XXXXXXXX..X...X...X.......... 18 mwen ......X.........................X...XX............ 4 ma<16> ...XXX..XXXXXXXX...X.XXXXXXXX..X...X...X.......... 23 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FTCPE_backup: FTCPE port map (backup,backup_T,clk,NOT porn,'0'); backup_T <= ((ma(20) AND ma(17) AND ma(16) AND ma(18) AND ma(19) AND en_conf AND NOT en_dclk AND backup AND NOT powerondelay AND pci3_done AND NOT sp_o(1)) OR (NOT ma(20) AND NOT ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND en_conf AND NOT en_dclk AND NOT backup AND conf_fail AND NOT powerondelay AND NOT sp_o(1)) OR (NOT ma(20) AND NOT ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND en_conf AND NOT en_dclk AND NOT backup AND NOT powerondelay AND NOT re_conf AND pci3_done AND NOT sp_o(1))); FTCPE_conf_fail: FTCPE port map (conf_fail,conf_fail_T,clk,NOT porn,'0'); conf_fail_T <= ((shift_data.EXP) OR (ma(20) AND conf_fail AND powerondelay AND NOT pci3_done AND NOT sp_o(1)) OR (ma(20) AND NOT conf_fail AND NOT powerondelay AND NOT pci3_done AND NOT sp_o(1)) OR (mdq(0) AND NOT mdq(1) AND mdq(2) AND NOT mdq(3) AND NOT mdq(4) AND mdq(5) AND NOT mdq(6) AND NOT ma(20) AND conf_fail AND sp_o(0) AND flash_we_q AND sp_i(5) AND NOT sp_o(1))); dcc_clk <= clk; FDCPE_div80: FDCPE port map (div8(0),div8_D(0),clk,NOT porn,'0',NOT sp_o(1)); div8_D(0) <= (en_conf AND NOT div8(0)); FDCPE_div81: FDCPE port map (div8(1),div8_D(1),clk,NOT porn,'0',NOT sp_o(1)); div8_D(1) <= ((en_conf AND div8(0) AND NOT div8(1)) OR (en_conf AND NOT div8(0) AND div8(1))); FTCPE_div82: FTCPE port map (div8(2),div8_T(2),clk,NOT porn,'0',NOT sp_o(1)); div8_T(2) <= ((NOT en_conf AND div8(2)) OR (en_conf AND div8(0) AND div8(1))); FDCPE_en_conf: FDCPE port map (en_conf,en_conf_D,clk,'0',NOT porn); en_conf_D <= ((EXP13_.EXP) OR (pci3_dclk_OBUF.EXP) OR (NOT ma(18) AND en_conf) OR (NOT ma(19) AND en_conf) OR (en_conf AND en_dclk) OR (mdq(0) AND NOT mdq(1) AND mdq(2) AND NOT mdq(3) AND NOT mdq(4) AND mdq(5) AND NOT mdq(6) AND sp_o(0) AND flash_we_q AND sp_i(5) AND NOT sp_o(1))); FTCPE_en_dclk: FTCPE port map (en_dclk,en_dclk_T,clk,NOT porn,'0'); en_dclk_T <= ((pci2_dclk_OBUF.EXP) OR (NOT ma(20) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND en_dclk AND NOT sp_o(1)) OR (ma(17) AND ma(18) AND ma(19) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND en_dclk AND NOT sp_o(1)) OR (NOT ma(12) AND NOT ma(13) AND NOT ma(14) AND NOT ma(15) AND NOT ma(10) AND NOT ma(11) AND NOT ma(8) AND NOT ma(9) AND NOT ma(0) AND NOT ma(1) AND NOT ma(2) AND NOT ma(3) AND NOT ma(4) AND NOT ma(5) AND NOT ma(6) AND NOT ma(7) AND en_conf AND en_dclk AND div8(0) AND div8(1) AND div8(2) AND powerondelay AND NOT sp_o(1))); FDCPE_flash_we_q: FDCPE port map (flash_we_q,flash_we_q_D,clk,NOT porn,'0'); flash_we_q_D <= (NOT en_conf AND NOT shift_data AND sp_i(2) AND pci3_done); FTCPE_ma0: FTCPE port map (ma(0),ma_T(0),clk,NOT porn,'0'); ma_T(0) <= ((ma(0) AND shift_addr AND NOT sp_i(4) AND NOT sp_o(1)) OR (NOT ma(0) AND shift_addr AND sp_i(4) AND NOT sp_o(1)) OR (div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma1: FTCPE port map (ma(1),ma_T(1),clk,NOT porn,'0'); ma_T(1) <= ((ma(0) AND NOT ma(1) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(0) AND ma(1) AND shift_addr AND NOT sp_o(1)) OR (ma(0) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma2: FTCPE port map (ma(2),ma_T(2),clk,NOT porn,'0'); ma_T(2) <= ((ma(1) AND NOT ma(2) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(1) AND ma(2) AND shift_addr AND NOT sp_o(1)) OR (ma(0) AND ma(1) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma3: FTCPE port map (ma(3),ma_T(3),clk,NOT porn,'0'); ma_T(3) <= ((ma(2) AND NOT ma(3) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(2) AND ma(3) AND shift_addr AND NOT sp_o(1)) OR (ma(0) AND ma(1) AND ma(2) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma4: FTCPE port map (ma(4),ma_T(4),clk,NOT porn,'0'); ma_T(4) <= ((ma(3) AND NOT ma(4) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(3) AND ma(4) AND shift_addr AND NOT sp_o(1)) OR (ma(0) AND ma(1) AND ma(2) AND ma(3) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma5: FTCPE port map (ma(5),ma_T(5),clk,NOT porn,'0'); ma_T(5) <= ((ma(4) AND NOT ma(5) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(4) AND ma(5) AND shift_addr AND NOT sp_o(1)) OR (ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma6: FTCPE port map (ma(6),ma_T(6),clk,NOT porn,'0'); ma_T(6) <= ((ma(5) AND NOT ma(6) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(5) AND ma(6) AND shift_addr AND NOT sp_o(1)) OR (ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma7: FTCPE port map (ma(7),ma_T(7),clk,NOT porn,'0'); ma_T(7) <= ((ma(6) AND NOT ma(7) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(6) AND ma(7) AND shift_addr AND NOT sp_o(1)) OR (ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma8: FTCPE port map (ma(8),ma_T(8),clk,'0',NOT porn); ma_T(8) <= ((ma(8) AND NOT ma(7) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(8) AND ma(7) AND shift_addr AND NOT sp_o(1)) OR (ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma9: FTCPE port map (ma(9),ma_T(9),clk,NOT porn,'0'); ma_T(9) <= ((ma(8) AND NOT ma(9) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(8) AND ma(9) AND shift_addr AND NOT sp_o(1)) OR (ma(8) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma10: FTCPE port map (ma(10),ma_T(10),clk,NOT porn,'0'); ma_T(10) <= ((en_dclk.EXP) OR (ma(10) AND NOT ma(9) AND shift_addr AND NOT sp_o(1)) OR (ma(8) AND ma(9) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma11: FTCPE port map (ma(11),ma_T(11),clk,NOT porn,'0'); ma_T(11) <= ((ma(10) AND NOT ma(11) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(10) AND ma(11) AND shift_addr AND NOT sp_o(1)) OR (ma(10) AND ma(8) AND ma(9) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma12: FTCPE port map (ma(12),ma_T(12),clk,'0',NOT porn); ma_T(12) <= ((ma(12) AND NOT ma(11) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(12) AND ma(11) AND shift_addr AND NOT sp_o(1)) OR (ma(10) AND ma(11) AND ma(8) AND ma(9) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma13: FTCPE port map (ma(13),ma_T(13),clk,'0',NOT porn); ma_T(13) <= ((ma(12) AND NOT ma(13) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(12) AND ma(13) AND shift_addr AND NOT sp_o(1)) OR (ma(12) AND ma(10) AND ma(11) AND ma(8) AND ma(9) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma14: FTCPE port map (ma(14),ma_T(14),clk,'0',NOT porn); ma_T(14) <= ((ma(13) AND NOT ma(14) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(13) AND ma(14) AND shift_addr AND NOT sp_o(1)) OR (ma(12) AND ma(13) AND ma(10) AND ma(11) AND ma(8) AND ma(9) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma15: FTCPE port map (ma(15),ma_T(15),clk,'0',NOT porn); ma_T(15) <= ((ma(14) AND NOT ma(15) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(14) AND ma(15) AND shift_addr AND NOT sp_o(1)) OR (ma(12) AND ma(13) AND ma(14) AND ma(10) AND ma(11) AND ma(8) AND ma(9) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma16: FTCPE port map (ma(16),ma_T(16),clk,NOT porn,'0'); ma_T(16) <= ((ma(16) AND NOT ma(15) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(16) AND ma(15) AND shift_addr AND NOT sp_o(1)) OR (ma(12) AND ma(13) AND ma(14) AND ma(15) AND ma(10) AND ma(11) AND ma(8) AND ma(9) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma17: FTCPE port map (ma(17),ma_T(17),clk,NOT porn,'0'); ma_T(17) <= ((ma(17) AND NOT ma(16) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(17) AND ma(16) AND shift_addr AND NOT sp_o(1)) OR (ma(16) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND ma(10) AND ma(11) AND ma(8) AND ma(9) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma18: FTCPE port map (ma(18),ma_T(18),clk,'0',NOT porn); ma_T(18) <= ((ma(17) AND NOT ma(18) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(17) AND ma(18) AND shift_addr AND NOT sp_o(1)) OR (ma(17) AND ma(16) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND ma(10) AND ma(11) AND ma(8) AND ma(9) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma19: FTCPE port map (ma(19),ma_T(19),clk,'0',NOT porn); ma_T(19) <= ((ma(18) AND NOT ma(19) AND shift_addr AND NOT sp_o(1)) OR (NOT ma(18) AND ma(19) AND shift_addr AND NOT sp_o(1)) OR (ma(17) AND ma(16) AND ma(18) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND ma(10) AND ma(11) AND ma(8) AND ma(9) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); FTCPE_ma20: FTCPE port map (ma(20),ma_T(20),clk,NOT porn,'0'); ma_T(20) <= ((ma(20) AND shift_addr AND NOT sp_i(6) AND NOT sp_o(1)) OR (NOT ma(20) AND shift_addr AND sp_i(6) AND NOT sp_o(1)) OR (ma(17) AND ma(16) AND ma(18) AND ma(19) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND ma(10) AND ma(11) AND ma(8) AND ma(9) AND ma(0) AND ma(1) AND ma(2) AND ma(3) AND ma(4) AND ma(5) AND ma(6) AND ma(7) AND div8(0) AND div8(1) AND div8(2) AND NOT shift_addr AND NOT sp_o(1))); mcen <= '0'; FDCPE_mdq2data: FDCPE port map (mdq2data,mdq2data_D,clk,NOT porn,'0',NOT sp_o(1)); mdq2data_D <= ((NOT en_conf AND NOT powerondelay AND pci3_done AND sp_i(1)) OR (NOT div8(0) AND div8(1) AND div8(2) AND NOT powerondelay)); FDCPE_mdq0: FDCPE port map (mdq_I(0),mdq(0),clk,'0','0'); mdq(0) <= ((moen_OBUF.EXP) OR (mdq(0) AND NOT porn) OR (mdq(0) AND sp_o(1)) OR (porn AND mdq2data AND mdq(0).PIN AND NOT sp_o(1)) OR (mdq(1) AND porn AND en_conf AND NOT mdq2data AND NOT sp_o(1))); mdq(0) <= mdq_I(0) when mdq_OE(0) = '1' else 'Z'; mdq_OE(0) <= flash_we_q; FDCPE_mdq1: FDCPE port map (mdq_I(1),mdq(1),clk,'0','0'); mdq(1) <= ((_7_.EXP) OR (mdq(1) AND NOT porn) OR (mdq(1) AND sp_o(1)) OR (porn AND mdq2data AND mdq(1).PIN AND NOT sp_o(1)) OR (mdq(2) AND porn AND en_conf AND NOT mdq2data AND NOT sp_o(1))); mdq(1) <= mdq_I(1) when mdq_OE(1) = '1' else 'Z'; mdq_OE(1) <= flash_we_q; FDCPE_mdq2: FDCPE port map (mdq_I(2),mdq(2),clk,'0','0'); mdq(2) <= ((_6_.EXP) OR (mdq(2) AND NOT porn) OR (mdq(2) AND sp_o(1)) OR (porn AND mdq2data AND mdq(2).PIN AND NOT sp_o(1)) OR (mdq(3) AND porn AND en_conf AND NOT mdq2data AND NOT sp_o(1))); mdq(2) <= mdq_I(2) when mdq_OE(2) = '1' else 'Z'; mdq_OE(2) <= flash_we_q; FDCPE_mdq3_BUFR: FDCPE port map (mdq(3)_BUFR,mdq_D(3)_BUFR,clk,'0','0'); mdq_D(3)_BUFR <= ((mdq(4)_BUFR.EXP) OR (mdq(3) AND NOT porn) OR (mdq(3) AND sp_o(1)) OR (porn AND mdq2data AND mdq(3).PIN AND NOT sp_o(1)) OR (mdq(3) AND NOT en_conf AND NOT mdq2data AND NOT shift_data AND sp_i(2)) OR (mdq(4) AND porn AND en_conf AND NOT mdq2data AND NOT sp_o(1))); mdq_I(3) <= mdq(3)_BUFR; mdq(3) <= mdq_I(3) when mdq_OE(3) = '1' else 'Z'; mdq_OE(3) <= flash_we_q; mdq_I(4) <= mdq(4)_BUFR; mdq(4) <= mdq_I(4) when mdq_OE(4) = '1' else 'Z'; mdq_OE(4) <= flash_we_q; FDCPE_mdq4_BUFR: FDCPE port map (mdq(4)_BUFR,mdq_D(4)_BUFR,clk,'0','0'); mdq_D(4)_BUFR <= ((pci1_dclk_OBUF.EXP) OR (mdq(4) AND NOT porn) OR (mdq(4) AND sp_o(1)) OR (porn AND mdq2data AND mdq(4).PIN AND NOT sp_o(1))); FDCPE_mdq5: FDCPE port map (mdq_I(5),mdq(5),clk,'0','0'); mdq(5) <= ((addr(10).EXP) OR (addr(17).EXP) OR (mdq(5) AND NOT porn) OR (mdq(5) AND sp_o(1)) OR (porn AND mdq2data AND mdq(5).PIN AND NOT sp_o(1)) OR (mdq(6) AND porn AND en_conf AND NOT mdq2data AND NOT sp_o(1))); mdq(5) <= mdq_I(5) when mdq_OE(5) = '1' else 'Z'; mdq_OE(5) <= flash_we_q; FDCPE_mdq6: FDCPE port map (mdq_I(6),mdq(6),clk,'0','0'); mdq(6) <= ((EXP12_.EXP) OR (mdq(6) AND NOT porn) OR (mdq(6) AND sp_o(1)) OR (porn AND mdq2data AND mdq(6).PIN AND NOT sp_o(1)) OR (porn AND en_conf AND NOT mdq2data AND sp_o(0) AND NOT sp_o(1))); mdq(6) <= mdq_I(6) when mdq_OE(6) = '1' else 'Z'; mdq_OE(6) <= flash_we_q; FDCPE_mdq7: FDCPE port map (mdq_I(7),mdq(7),clk,'0','0'); mdq(7) <= ((powerondelay.EXP) OR (NOT porn AND mdq(7)) OR (mdq(7) AND sp_o(1)) OR (porn AND mdq2data AND mdq(7).PIN AND NOT sp_o(1)) OR (mdq(7) AND NOT en_conf AND NOT mdq2data AND NOT shift_data AND sp_i(2))); mdq(7) <= mdq_I(7) when mdq_OE(7) = '1' else 'Z'; mdq_OE(7) <= flash_we_q; moen <= (NOT en_conf AND sp_i(2) AND pci3_done); mrstn <= porn; mwen <= NOT ((NOT en_conf AND NOT shift_data AND sp_i(2) AND pci3_done)); FDCPE_pci1_confn: FDCPE port map (pci1_confn,pci1_confn_D,clk,'0',NOT porn); pci1_confn_D <= (NOT ma(20) AND NOT ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND NOT ma(10) AND NOT ma(11) AND ma(8) AND NOT ma(9) AND en_conf AND NOT powerondelay); FDCPE_pci1_data: FDCPE port map (pci1_data,pci1_data_D,clk,'0','0',porn); pci1_data_D <= (mdq(0) AND NOT ma(20) AND NOT ma(17) AND ma(16) AND ma(18) AND ma(19) AND en_dclk); FDCPE_pci1_dclk: FDCPE port map (pci1_dclk,conf_fail.EXP,clk,NOT porn,'0'); FDCPE_pci2_confn: FDCPE port map (pci2_confn,pci2_confn_D,clk,'0',NOT porn); pci2_confn_D <= (NOT ma(20) AND NOT ma(17) AND ma(16) AND ma(18) AND ma(19) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND NOT ma(10) AND NOT ma(11) AND ma(8) AND NOT ma(9) AND en_conf AND NOT powerondelay); FDCPE_pci2_data: FDCPE port map (pci2_data,pci2_data_D,clk,'0','0',porn); pci2_data_D <= (mdq(0) AND NOT ma(20) AND ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND en_dclk); FDCPE_pci2_dclk: FDCPE port map (pci2_dclk,pci2_dclk_D,clk,NOT porn,'0'); pci2_dclk_D <= (NOT ma(20) AND ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND en_dclk AND NOT sp_o(1)); FDCPE_pci3_confn: FDCPE port map (pci3_confn,pci3_confn_D,clk,'0',NOT porn); pci3_confn_D <= ((NOT ma(20) AND NOT ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND NOT ma(12) AND ma(13) AND ma(14) AND ma(15) AND ma(10) AND ma(11) AND NOT pci3_done) OR (NOT ma(20) AND ma(17) AND ma(16) AND NOT ma(18) AND ma(19) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND NOT ma(10) AND NOT ma(11) AND ma(8) AND NOT ma(9) AND en_conf AND NOT powerondelay) OR (NOT ma(20) AND ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND NOT ma(10) AND NOT ma(11) AND ma(8) AND NOT ma(9) AND en_conf AND NOT powerondelay)); FDCPE_pci3_data: FDCPE port map (pci3_data,ver_sr(1).EXP,clk,'0','0',porn); FDCPE_pci3_dclk: FDCPE port map (pci3_dclk,shift_addr.EXP,clk,NOT porn,'0'); FDCPE_powerondelay: FDCPE port map (powerondelay,'0',clk,'0',NOT porn,powerondelay_CE); powerondelay_CE <= (NOT ma(20) AND NOT ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND NOT ma(10) AND NOT ma(11) AND NOT ma(8) AND NOT ma(9) AND NOT sp_o(1)); FTCPE_re_conf: FTCPE port map (re_conf,re_conf_T,clk,'0','0'); re_conf_T <= ((porn AND en_dclk AND re_conf AND NOT sp_o(1)) OR (mdq(0) AND NOT mdq(1) AND mdq(2) AND NOT mdq(3) AND NOT mdq(4) AND mdq(5) AND NOT mdq(6) AND porn AND sp_o(0) AND flash_we_q AND sp_i(5) AND NOT re_conf AND NOT sp_o(1))); FDCPE_shift_addr: FDCPE port map (shift_addr,shift_addr_D,clk,'0','0',shift_addr_CE); shift_addr_D <= (NOT en_conf AND pci3_done AND sp_i(0)); shift_addr_CE <= (porn AND NOT sp_o(1)); FDCPE_shift_data: FDCPE port map (shift_data,sp_i(3),clk,NOT porn,'0',NOT sp_o(1)); FDCPE_sp_o0: FDCPE port map (sp_o(0),sp_o_D(0),clk,'0','0'); sp_o_D(0) <= ((NOT porn AND sp_o(0)) OR (sp_o(0) AND sp_o(1)) OR (porn AND mdq2data AND mdq(7).PIN AND NOT sp_o(1)) OR (NOT en_conf AND NOT mdq2data AND NOT shift_data AND sp_i(2) AND sp_o(0)) OR (mdq(6) AND porn AND NOT en_conf AND NOT mdq2data AND shift_data AND NOT sp_o(1))); FTCPE_sp_o1: FTCPE port map (sp_o(1),'1',clk,'0',NOT porn); FTCPE_sp_o2: FTCPE port map (sp_o(2),sp_o_T(2),clk,'0','0'); sp_o_T(2) <= ((porn AND mdq2data AND sp_o(2) AND NOT sp_o(1)) OR (porn AND shift_data AND NOT ver_sr(5) AND sp_o(2) AND NOT sp_o(1)) OR (porn AND NOT mdq2data AND shift_data AND ver_sr(5) AND NOT sp_o(2) AND NOT sp_o(1))); sp_o(3) <= vtx_done; FTCPE_ver_sr1: FTCPE port map (ver_sr(1),ver_sr_T(1),clk,'0','0'); ver_sr_T(1) <= ((porn AND mdq2data AND NOT ver_sr(1) AND NOT sp_o(1)) OR (porn AND NOT mdq2data AND shift_data AND ver_sr(1) AND NOT sp_o(1))); FTCPE_ver_sr2: FTCPE port map (ver_sr(2),ver_sr_T(2),clk,'0','0'); ver_sr_T(2) <= ((porn AND mdq2data AND ver_sr(2) AND NOT sp_o(1)) OR (porn AND shift_data AND NOT ver_sr(1) AND ver_sr(2) AND NOT sp_o(1)) OR (porn AND NOT mdq2data AND shift_data AND ver_sr(1) AND NOT ver_sr(2) AND NOT sp_o(1))); FTCPE_ver_sr3: FTCPE port map (ver_sr(3),ver_sr_T(3),clk,'0','0'); ver_sr_T(3) <= ((porn AND mdq2data AND ver_sr(3) AND NOT sp_o(1)) OR (porn AND shift_data AND NOT ver_sr(2) AND ver_sr(3) AND NOT sp_o(1)) OR (porn AND NOT mdq2data AND shift_data AND ver_sr(2) AND NOT ver_sr(3) AND NOT sp_o(1))); FTCPE_ver_sr4: FTCPE port map (ver_sr(4),ver_sr_T(4),clk,'0','0'); ver_sr_T(4) <= ((porn AND mdq2data AND ver_sr(4) AND NOT sp_o(1)) OR (porn AND shift_data AND NOT ver_sr(3) AND ver_sr(4) AND NOT sp_o(1)) OR (porn AND NOT mdq2data AND shift_data AND ver_sr(3) AND NOT ver_sr(4) AND NOT sp_o(1))); FTCPE_ver_sr5: FTCPE port map (ver_sr(5),ver_sr_T(5),clk,'0','0'); ver_sr_T(5) <= ((porn AND mdq2data AND ver_sr(5) AND NOT sp_o(1)) OR (porn AND shift_data AND NOT ver_sr(4) AND ver_sr(5) AND NOT sp_o(1)) OR (porn AND NOT mdq2data AND shift_data AND ver_sr(4) AND NOT ver_sr(5) AND NOT sp_o(1))); FDCPE_vtx_clk: FDCPE port map (vtx_clk,vtx_clk_D,clk,'0',NOT porn); vtx_clk_D <= (ma(20) AND en_dclk AND sp_o(1)); FDCPE_vtx_confn: FDCPE port map (vtx_confn,vtx_confn_D,clk,'0',NOT porn); vtx_confn_D <= ((NOT ma(20) AND NOT ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND NOT ma(12) AND ma(13) AND ma(14) AND ma(15) AND ma(10) AND ma(11) AND NOT vtx_confn AND NOT pci3_done) OR (NOT ma(20) AND ma(17) AND ma(16) AND NOT ma(18) AND ma(19) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND NOT ma(10) AND NOT ma(11) AND ma(8) AND NOT ma(9) AND en_conf AND NOT powerondelay) OR (NOT ma(20) AND ma(17) AND NOT ma(16) AND ma(18) AND ma(19) AND ma(12) AND ma(13) AND ma(14) AND ma(15) AND NOT ma(10) AND NOT ma(11) AND ma(8) AND NOT ma(9) AND en_conf AND NOT powerondelay)); FDCPE_vtx_data: FDCPE port map (vtx_data,vtx_data_D,clk,'0','0',porn); vtx_data_D <= (mdq(0) AND ma(20) AND en_dclk); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9572XL-10-TQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC9572XL-10-TQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 ma<0> 51 VCC 2 NC 52 pci1_dclk 3 ma<1> 53 pci1_confn 4 mcen 54 pci1_data 5 VCC 55 pci1_done 6 moen 56 pci3_data 7 NC 57 VCC 8 mdq<0> 58 pci3_done 9 mdq<1> 59 pci3_dclk 10 mdq<2> 60 sp_i<0> 11 mdq<3> 61 sp_i<1> 12 mdq<4> 62 GND 13 mdq<5> 63 sp_i<2> 14 mdq<6> 64 sp_i<3> 15 mdq<7> 65 sp_i<4> 16 ma<10> 66 sp_i<5> 17 ma<20> 67 sp_i<6> 18 ma<17> 68 KPR 19 NC 69 GND 20 porn 70 KPR 21 GND 71 sp_o<0> 22 clk 72 pci3_confn 23 ma<19> 73 NC 24 NC 74 sp_o<1> 25 KPR 75 GND 26 VCC 76 sp_o<2> 27 pci2_done 77 sp_o<3> 28 pci2_confn 78 ma<15> 29 pci2_data 79 ma<16> 30 pci2_dclk 80 NC 31 GND 81 ma<14> 32 vtx_confn 82 ma<13> 33 vtx_done 83 TDO 34 NC 84 GND 35 vtx_clk 85 ma<12> 36 KPR 86 ma<11> 37 vtx_data 87 ma<9> 38 VCC 88 VCC 39 KPR 89 ma<8> 40 KPR 90 mwen 41 KPR 91 mrstn 42 KPR 92 ma<18> 43 NC 93 ma<7> 44 GND 94 ma<6> 45 TDI 95 ma<5> 46 NC 96 ma<4> 47 TMS 97 ma<3> 48 TCK 98 VCC 49 KPR 99 ma<2> 50 dcc_clk 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572xl-10-TQ100 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : LOW Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 32