Xilinx Design Summary

dccv2c29 Project Status (08/13/2008 - 12:05:52)
Project File:	dccv2c29.ise	Current State:	Programming File Generated
Module Name:	dcc	Errors:	No Errors
Target Device:	xc2v2000-4bg575	Warnings:	509 Warnings
Product Version:	ISE 10.1.02 - Foundation Simulator	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	All Constraints Met
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Timing Report)

dccv2c29 Partition Summary				[-]
No partition information was found.

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Total Number Slice Registers	4,224	21,504	19%
Number used as Flip Flops	4,223
Number used as Latches	1
Number of 4 input LUTs	4,230	21,504	19%
Logic Distribution
Number of occupied Slices	3,853	10,752	35%
Number of Slices containing only related logic	3,853	3,853	100%
Number of Slices containing unrelated logic	0	3,853	0%
Total Number of 4 input LUTs	4,674	21,504	21%
Number used as logic	3,700
Number used as a route-thru	444
Number used for Dual Port RAMs	300
Number used as 16x1 RAMs	32
Number used as 16x1 ROMs	4
Number used as Shift registers	194
Number of bonded IOBs
Number of bonded	245	408	60%
IOB Flip Flops	375
Number of TBUFs	1,120	5,376	20%
Number of RAMB16s	51	56	91%
Number of BUFGMUXs	9	16	56%
Number of DCMs	3	8	37%

Performance Summary				[-]
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

Date Generated: 08/13/2008 - 12:05:52