Programmer's manual for DCC author: S.X.Wu firmware revision: x"2c30" -- release notes 8/11/2008 Another try to fix BCN mismatch counter errors. firmware revision: x"2c2f" -- release notes 8/6/2008 Trying to fix problems with counters in the range of 0x600-0x7ff firmware revision: x"2c2e" -- release notes 7/22/2008 bit 3 of register 0x4 redefined: It was used for slink64/32 selection. Since nobody is using slink32 anymore, it is used to control HTR CRC word overwrite. Default is no overwrite, if set to '1', overwrite is enabled. firmware revision: x"2c2d" -- release notes 6/11/2008 The bug was not fixed by v2c2c. This bug was introduced in version 2c29 by a typo in VHDL module monitor.vhd The bug caused LRB event data being overwritten by the last word of DCC event data when register 0x8 is not in error capturing mode (i.e. bits 23-16 are all zero) firmware revision: x"2c2c" -- release notes 6/10/2008 A bug in the logic which overwrites HTR generate CRC word was fixed. The bug caused data words occationally being over written. firmware revision: x"2c2b" -- release notes 5/30/2008 counters for LRB single/multiple bit errors added in 0x540-0x5b8 firmware revision: x"2c2a" -- release notes 5/27/2008 a bug introduced in v2c29 is fixed. The bug caused register read out errors. firmware revision: x"2c29" -- release notes 5/27/2008 monitor prescale control register 0x8 extended to 32-bits to capture events with errors. If bits23-16 are all zero, it works as before. If any of these bits is set, the 128 monitor event buffer behaves like a ring buffer, it overwrites the old events when buffer is full. If any event error matches any bits set in bits23-16 of register 0x8, monitor will catch the next 64 events and then stop and set the monitor buffer full flag. Readout of the monitored events remains unchanged. You can readout them while the run is still going. After finishing the readout, you can re-enabling the capture function by writing to register 0x8 again. Beaware that do not reset the run bit before reading out the events, otherwise the event order will not be all that straight forward. firmware revision: x"2c28" -- release notes 5/19/2008 Just to make CERN's 2c27 obsolete firmware revision: x"2c27" -- release notes 5/18/2008 LRB data CRC check added. CRC error will set bit 10 of HTR status header in DCC output data. Individual 32bit counters have been added to count CRC errors. LRB CRC uses the same polynomial as DCC CRC data, namely x^16 + x^15 + x^2 + 1 firmware revision: x"2c26" -- release notes 5/15/2008 counters 0x600-0x7FC added For any particular HTR channel in any particular event, counters for different type of errors are mutually exclusive, i.e. , no more than one counter can count. resync function now takes account of Calibration trigger cases. Calibration flag now from the correct HTR status bit 14(was bit 12) firmware revision: x"2c25" -- release notes 5/10/2008 control bits 24-20 of register 0x1c restored. This should make the firmware compatible with the old software. firmware revision: x"2c24" -- release notes 5/7/2008 register 0x20 has been added to save bcnt offset values old BCNT offset control bits 24-20 of register 0x1C removed event builder resync function algorithm modified. Simulation shows its ability of resync if register 0x18 is written with all zero. firmware revision: x"2c23" -- release notes 4/2/2008 Fixed a DCC's HTR data buffer overrun problem. firmware revision: x"2c22" -- release notes 3/24/2008 bit 15 of register x8 is used to enable TTS BUSY being generated when trigger rule is violated. register 0xbe8(32 bits) counts number of time rules are violated. firmware revision: x"2c21" -- release notes 3/20/2008 This revision should fix a bug in event number mismatch checking firmware revision: x"2c20" -- release notes 3/20/2008 L1 rate limit added: if more than 30 L1 within 12000 Bx, BUSY will be sent to TTS system firmware revision: x"2c1f" -- release notes 3/18/2008 the lower byte of the firmware version is noe in bits 23-16 of the second DCC header word. firmware revision: x"2c1e" -- release notes 3/15/2008 A bug in the HTR status handling is fixed. This bug could prevent HTR OFW/BZ warning does not stay. firmware revision: x"2c1d" -- release notes 3/14/2008 a bug in 2c1c is fixed. This version also only requires one HTR event to return HTR status to normal. This should help to solve the busy deadlock problem. firmware revision: x"2c1c" -- release notes 3/13/2008 HTR status will not be used for STT if LRB errors are detected for that event. firmware revision: x"2c1b" -- release notes 3/13/2008 no changes other than the version number firmware revision: x"2c1a" -- release notes 3/12/2008 added TTS state at level 1 time to bit 11-8 of the first DCC header word. firmware revision: x"2c18" -- release notes 12/11/2007 a bug in ttc broadcast strobe pin assignment fixed. TTC broadcast commands do not work in all earlier versions. a bug in HTR mismatching counters has been fixed too. The orbit count of HTR used in matching is reduced to five LSBs. firmware revision: x"2c17" -- release notes 12/5/2007 calibration trigger now reset with bit 0 of register 0x0, was bit 2 of register 0x0 firmware revision: x"2c16" -- release notes 12/5/2007 test version, same code as 2c15. Using ISE9.1 instead of ISE9.2 firmware revision: x"2c15" -- release notes 10/17/2007 A bug introduced in version 2c11 is fixed. No revisions between 2c11 and 2c14 should be used firmware revision: x"2c14" -- release notes 9/28/2007 bug fixed for SST signals firmware revision: x"2c13" -- release notes 9/27/2007 protection added against monitored event count from wrapping around when it is zero firmware revision: x"2c12" -- release notes 9/18/2007 added bit 14 in register 0x4. If set to '1', monitor buffer full will pause the event builder. firmware revision: x"2c11" -- release notes 6/13/2007 SDRAM precharge changed to for all banks. firmware revision: x"2c10" -- release notes 2/21/2007 Orbit number in second DAQ header now occupies bits 35-4 instead of 31-0. firmware revision: x"2c0f" -- release notes 2/19/2007 A bug in the event number fifo is fixed. firmware revision: x"2c0e" -- release notes 2/16/2007 A bug in the TTCrx interface is fixed. The old firmware would have problem when 1. receiving L1 while not in run mode. 2. Broadcast calibration trigger is received. firmware revision: x"2c0d" -- release notes 2/13/2007 A bug in the HTR data buffer which caused high-low swapping in 64-bit word is fixed. firmware revision: x"2c0c" -- release notes 1/22/2007 A bug is fixed in the VME write to SDRAM. A problem in VME write to LOG3 fmem space is also found related to the UniverseII VSI setting. It does not work correctly when posted write is enabled. So the PWEN bit of the VSI2_CTL register(0xf28) must not be set. At the same time, log3 firmware must be upgraded to pci3v12.hex firmware revision: x"2c0b" -- release notes 1/10/2007 changes from last revision slink fifo access address moved from 0x5000-57fc to 0x3000-0x37fc register 0x88 definition has been modified to simplify read out TTCrx event number fifo expanded and moved from 0x6000-6ffc to 0x4000-0x7ffc orbit number is now also available for readout. The third 32-bit word in DAQ header is the orbit count DDR SDRAM controller has been improved, it has now automatic readout timing compensation. firmware revision: x"2c05" -- release notes 5/12/2006 Chnages from version x"2b04": VME block transfer errors fixed counters in address range 0x3a0 thru 0x3e4 have been reallocated new counters counting HTR status bits added in address range 0x800 thru 0xbb8 new monitoring counters added in address range 0xbc0 thru 0xbe4 new control registers for error handling added in address range 0xc00 thru 0xe10 new DCC spec defined in Eric's June 1 2005 has been fully implemented with minor modification The control register of error handling consists of eight bits. With the bits 7-4 as state changing threshold. bits 3-0 are the new state. Up-down counters are used to monitor these error bits. They counted up when the corresponding bit in the status word is set and counted down when the bit is reset. If the up-down counter is bigger than the threshold, the new state will be set. Up-down counters are used to avoid unneccesary state changes. To disable the state change for a certain bit, its threshold in the control register should be set to "1111". If several state change requests occur at the same time, the precedance is discoonect, error, out of sync and the others. Once enters disconnect, error or out of sync states, only a reset or resync command could change the state. Between ready and busy, full warning is a must pass state as specified in the state diagram. Disconnect state is represented now by "1111" instead of "0000" orbit counter is put in bits 31-0 of the second DAQ header word. BCN matching now also includes the six LSBs of the orbit counter. In order to empty LRBs quickly in case of a resync command, LRBs must be updated to LRBV27 -- DCC is accessed via BAR0 of log3 which occupies 0x20000 bytes of memory space They all support burst read/write access OFFSET NAME ACCESS offset 0x0 command and status register R/W offset 0x4 configuration register R/W offset 0x8 monitoring event control R/W offset 0xc HTR channel enable register Read Only offset 0x10 TTCrx ID register R/W offset 0x14 TTCrx I2C access register R/W offset 0x18 synchronization control register R/W offset 0x1C source ID register R/W offset 0x20 BCNT offset register R/W offset 0x80 SDRAM page register R/W offset 0x84 monitoring event word count Read only offset 0x88 event number fifo pointers Read Only offset 0x8c Slink fifo pointers Read Only offset 0xa0 evt_bldr debugging signals Read Only offset 0xa4 evt_bldr debugging signals Read Only offset 0xa8 all zeros Read Only offset 0xac ddr_w_queue debugging signals Read Only offset 0xb0 last ddrram data word during random memory test(should be zero) Read Only offset 0xb4 last LFSR word during random memory test(should be zero) Read Only offset 0xb8 last ddrram address random memory test(should be 0x7f0000) Read Only bit 13-0 cache_eof bit 14 memory test done bit 15 memory test failed bit 23-16 SDRAM page register bit 31-24 tst_addr offset 0xbc next to last ddrram data word during random memory test(should be 0x80000000)Read Only offset 0x200 HTR0 mismatch counter low Read Only offset 0x204 HTR0 mismatch counter high Read Only offset 0x208 HTR1 mismatch counter low Read Only offset 0x20c HTR1 mismatch counter high Read Only offset 0x210 HTR2 mismatch counter low Read Only offset 0x214 HTR2 mismatch counter high Read Only offset 0x218 HTR3 mismatch counter low Read Only offset 0x20c HTR3 mismatch counter high Read Only offset 0x220 HTR4 mismatch counter low Read Only offset 0x224 HTR4 mismatch counter high Read Only offset 0x228 HTR5 mismatch counter low Read Only offset 0x22c HTR5 mismatch counter high Read Only offset 0x230 HTR6 mismatch counter low Read Only offset 0x234 HTR6 mismatch counter high Read Only offset 0x238 HTR7 mismatch counter low Read Only offset 0x23c HTR7 mismatch counter high Read Only offset 0x240 HTR8 mismatch counter low Read Only offset 0x244 HTR8 mismatch counter high Read Only offset 0x248 HTR9 mismatch counter low Read Only offset 0x24c HTR9 mismatch counter high Read Only offset 0x250 HTR10 mismatch counter low Read Only offset 0x254 HTR10 mismatch counter high Read Only offset 0x258 HTR11 mismatch counter low Read Only offset 0x25c HTR11 mismatch counter high Read Only offset 0x260 HTR12 mismatch counter low Read Only offset 0x264 HTR12 mismatch counter high Read Only offset 0x268 HTR13 mismatch counter low Read Only offset 0x26c HTR13 mismatch counter high Read Only offset 0x270 HTR14 mismatch counter low Read Only offset 0x274 HTR14 mismatch counter high Read Only offset 0x290 HTR0 block counter low Read Only offset 0x294 HTR0 block counter high Read Only offset 0x298 HTR1 block counter low Read Only offset 0x29c HTR1 block counter high Read Only offset 0x2a0 HTR2 block counter low Read Only offset 0x2a4 HTR2 block counter high Read Only offset 0x2a8 HTR3 block counter low Read Only offset 0x2ac HTR3 block counter high Read Only offset 0x2b0 HTR4 block counter low Read Only offset 0x2b4 HTR4 block counter high Read Only offset 0x2b8 HTR5 block counter low Read Only offset 0x2bc HTR5 block counter high Read Only offset 0x2c0 HTR6 block counter low Read Only offset 0x2c4 HTR6 block counter high Read Only offset 0x2c8 HTR7 block counter low Read Only offset 0x2cc HTR7 block counter high Read Only offset 0x2d0 HTR8 block counter low Read Only offset 0x2d4 HTR8 block counter high Read Only offset 0x2d8 HTR9 block counter low Read Only offset 0x2dc HTR9 block counter high Read Only offset 0x2e0 HTR10 block counter low Read Only offset 0x2e4 HTR10 block counter high Read Only offset 0x2e8 HTR11 block counter low Read Only offset 0x2ec HTR11 block counter high Read Only offset 0x2f0 HTR12 block counter low Read Only offset 0x2f4 HTR12 block counter high Read Only offset 0x2f8 HTR13 block counter low Read Only offset 0x2fc HTR13 block counter high Read Only offset 0x300 HTR14 block counter low Read Only offset 0x304 HTR14 block counter high Read Only offset 0x320 HTR0 word counter low Read Only offset 0x324 HTR0 word counter high Read Only offset 0x328 HTR1 word counter low Read Only offset 0x32c HTR1 word counter high Read Only offset 0x330 HTR2 word counter low Read Only offset 0x334 HTR2 word counter high Read Only offset 0x338 HTR3 word counter low Read Only offset 0x33c HTR3 word counter high Read Only offset 0x340 HTR4 word counter low Read Only offset 0x344 HTR4 word counter high Read Only offset 0x348 HTR5 word counter low Read Only offset 0x34c HTR5 word counter high Read Only offset 0x350 HTR6 word counter low Read Only offset 0x354 HTR6 word counter high Read Only offset 0x358 HTR7 word counter low Read Only offset 0x35c HTR7 word counter high Read Only offset 0x360 HTR8 word counter low Read Only offset 0x364 HTR8 word counter high Read Only offset 0x368 HTR9 word counter low Read Only offset 0x36c HTR9 word counter high Read Only offset 0x370 HTR10 word counter low Read Only offset 0x374 HTR10 word counter high Read Only offset 0x378 HTR11 word counter low Read Only offset 0x37c HTR11 word counter high Read Only offset 0x380 HTR12 word counter low Read Only offset 0x384 HTR12 word counter high Read Only offset 0x388 HTR13 word counter low Read Only offset 0x38c HTR13 word counter high Read Only offset 0x390 HTR14 word counter low Read Only offset 0x394 HTR14 word counter high Read Only offset 0x3a0 event builder word counter low Read Only offset 0x3a4 event builder word counter high Read Only offset 0x3a8 slink word counter low Read Only offset 0x3ac slink word counter high Read Only offset 0x3b0 TTCrx Single err counter low Read Only offset 0x3b4 TTCrx Single err counter high Read Only offset 0x3b8 TTCrx double err counter low Read Only offset 0x3bc TTCrx double err counter high Read Only offset 0x3c0 READY on time counter low Read Only offset 0x3c4 READY on time counter high Read Only offset 0x3c8 BUSY on time counter low Read Only offset 0x3cc BUSY on time counter high Read Only offset 0x3d0 OVFL on time counter low Read Only offset 0x3d4 OVFL on time counter high Read Only offset 0x3d8 SYNC lost on time counter low Read Only offset 0x3dc SYNC lost on time counter high Read Only offset 0x3e0 RUN on time counter low Read Only offset 0x3e4 RUN on time counter high Read Only offset 0x400 MIP1 0x48 data Read Only offset 0x404 MIP1 0x4c data Read Only offset 0x408 MIP1 0x50 data Read Only offset 0x40c MIP1 0x54 data Read Only offset 0x410 MIP1 0x58 data Read Only offset 0x414 MIP1 0x5c data Read Only offset 0x418 MIP1 0x60 data Read Only offset 0x41c MIP1 0x64 data Read Only offset 0x420 MIP1 0x68 data Read Only offset 0x424 MIP1 0x6c data Read Only offset 0x428 MIP2 0x48 data Read Only offset 0x42c MIP2 0x4c data Read Only offset 0x430 MIP2 0x50 data Read Only offset 0x434 MIP2 0x54 data Read Only offset 0x438 MIP2 0x58 data Read Only offset 0x43c MIP2 0x5c data Read Only offset 0x440 MIP2 0x60 data Read Only offset 0x444 MIP2 0x64 data Read Only offset 0x448 MIP2 0x68 data Read Only offset 0x44c MIP2 0x6c data Read Only offset 0x450 MIP3 0x48 data Read Only offset 0x454 MIP3 0x4c data Read Only offset 0x458 MIP3 0x50 data Read Only offset 0x45c MIP3 0x54 data Read Only offset 0x460 MIP3 0x58 data Read Only offset 0x464 MIP3 0x5c data Read Only offset 0x468 MIP3 0x60 data Read Only offset 0x46c MIP3 0x64 data Read Only offset 0x470 MIP3 0x68 data Read Only offset 0x474 MIP3 0x6c data Read Only offset 0x480 MIP4 0x48 data Read Only offset 0x484 MIP4 0x4c data Read Only offset 0x488 MIP4 0x50 data Read Only offset 0x48c MIP4 0x54 data Read Only offset 0x490 MIP4 0x58 data Read Only offset 0x494 MIP4 0x5c data Read Only offset 0x498 MIP4 0x60 data Read Only offset 0x49c MIP4 0x64 data Read Only offset 0x4a0 MIP4 0x68 data Read Only offset 0x4a4 MIP4 0x6c data Read Only offset 0x4a8 MIP5 0x48 data Read Only offset 0x4ac MIP5 0x4c data Read Only offset 0x4b0 MIP5 0x50 data Read Only offset 0x4b4 MIP5 0x54 data Read Only offset 0x4b8 MIP5 0x58 data Read Only offset 0x4bc MIP5 0x5c data Read Only offset 0x4c0 MIP5 0x60 data Read Only offset 0x4c4 MIP5 0x64 data Read Only offset 0x4c8 MIP5 0x68 data Read Only offset 0x4cc MIP5 0x6c data Read Only offset 0x4d0 MIP6 0x48 data Read Only offset 0x4d4 MIP6 0x4c data Read Only offset 0x4d8 MIP6 0x50 data Read Only offset 0x4dc MIP6 0x54 data Read Only offset 0x4e0 MIP6 0x58 data Read Only offset 0x4e4 MIP6 0x5c data Read Only offset 0x4e8 MIP6 0x60 data Read Only offset 0x4ec MIP6 0x64 data Read Only offset 0x4f0 MIP6 0x68 data Read Only offset 0x4f4 MIP6 0x6c data Read Only offset 0x500 HTR0 CRC error counter Read Only offset 0x504 HTR1 CRC error counter Read Only offset 0x508 HTR2 CRC error counter Read Only offset 0x50C HTR3 CRC error counter Read Only offset 0x510 HTR4 CRC error counter Read Only offset 0x514 HTR5 CRC error counter Read Only offset 0x518 HTR6 CRC error counter Read Only offset 0x51C HTR7 CRC error counter Read Only offset 0x520 HTR8 CRC error counter Read Only offset 0x524 HTR9 CRC error counter Read Only offset 0x528 HTR10 CRC error counter Read Only offset 0x52C HTR11 CRC error counter Read Only offset 0x530 HTR12 CRC error counter Read Only offset 0x534 HTR13 CRC error counter Read Only offset 0x538 HTR14 CRC error counter Read Only offset 0x540 HTR0 LRB Cerr counter Read Only offset 0x544 HTR1 LRB Cerr counter Read Only offset 0x548 HTR2 LRB Cerr counter Read Only offset 0x54C HTR3 LRB Cerr counter Read Only offset 0x550 HTR4 LRB Cerr counter Read Only offset 0x554 HTR5 LRB Cerr counter Read Only offset 0x558 HTR6 LRB Cerr counter Read Only offset 0x55C HTR7 LRB Cerr counter Read Only offset 0x560 HTR8 LRB Cerr counter Read Only offset 0x564 HTR9 LRB Cerr counter Read Only offset 0x568 HTR10 LRB Cerr counter Read Only offset 0x56C HTR11 LRB Cerr counter Read Only offset 0x570 HTR12 LRB Cerr counter Read Only offset 0x574 HTR13 LRB Cerr counter Read Only offset 0x578 HTR14 LRB Cerr counter Read Only offset 0x580 HTR0 LRB Uerr counter Read Only offset 0x584 HTR1 LRB Uerr counter Read Only offset 0x588 HTR2 LRB Uerr counter Read Only offset 0x58C HTR3 LRB Uerr counter Read Only offset 0x590 HTR4 LRB Uerr counter Read Only offset 0x594 HTR5 LRB Uerr counter Read Only offset 0x598 HTR6 LRB Uerr counter Read Only offset 0x59C HTR7 LRB Uerr counter Read Only offset 0x5a0 HTR8 LRB Uerr counter Read Only offset 0x5a4 HTR9 LRB Uerr counter Read Only offset 0x5a8 HTR10 LRB Uerr counter Read Only offset 0x5aC HTR11 LRB Uerr counter Read Only offset 0x5b0 HTR12 LRB Uerr counter Read Only offset 0x5b4 HTR13 LRB Uerr counter Read Only offset 0x5b8 HTR14 LRB Uerr counter Read Only offset 0x600 HTR0 evn mismatch counter Read Only offset 0x604 HTR1 evn mismatch counter Read Only offset 0x608 HTR2 evn mismatch counter Read Only offset 0x60C HTR3 evn mismatch counter Read Only offset 0x610 HTR4 evn mismatch counter Read Only offset 0x614 HTR5 evn mismatch counter Read Only offset 0x618 HTR6 evn mismatch counter Read Only offset 0x61C HTR7 evn mismatch counter Read Only offset 0x620 HTR8 evn mismatch counter Read Only offset 0x624 HTR9 evn mismatch counter Read Only offset 0x628 HTR10 evn mismatch counter Read Only offset 0x62C HTR11 evn mismatch counter Read Only offset 0x630 HTR12 evn mismatch counter Read Only offset 0x634 HTR13 evn mismatch counter Read Only offset 0x638 HTR14 evn mismatch counter Read Only offset 0x640 HTR0 bcn mismatch counter Read Only offset 0x644 HTR1 bcn mismatch counter Read Only offset 0x648 HTR2 bcn mismatch counter Read Only offset 0x64C HTR3 bcn mismatch counter Read Only offset 0x650 HTR4 bcn mismatch counter Read Only offset 0x654 HTR5 bcn mismatch counter Read Only offset 0x658 HTR6 bcn mismatch counter Read Only offset 0x65C HTR7 bcn mismatch counter Read Only offset 0x660 HTR8 bcn mismatch counter Read Only offset 0x664 HTR9 bcn mismatch counter Read Only offset 0x668 HTR10 bcn mismatch counter Read Only offset 0x66C HTR11 bcn mismatch counter Read Only offset 0x670 HTR12 bcn mismatch counter Read Only offset 0x674 HTR13 bcn mismatch counter Read Only offset 0x678 HTR14 bcn mismatch counter Read Only offset 0x680 HTR0 orn mismatch counter Read Only offset 0x684 HTR1 orn mismatch counter Read Only offset 0x688 HTR2 orn mismatch counter Read Only offset 0x68C HTR3 orn mismatch counter Read Only offset 0x690 HTR4 orn mismatch counter Read Only offset 0x694 HTR5 orn mismatch counter Read Only offset 0x698 HTR6 orn mismatch counter Read Only offset 0x69C HTR7 orn mismatch counter Read Only offset 0x6A0 HTR8 orn mismatch counter Read Only offset 0x6A4 HTR9 orn mismatch counter Read Only offset 0x6A8 HTR10 orn mismatch counter Read Only offset 0x6AC HTR11 orn mismatch counter Read Only offset 0x6B0 HTR12 orn mismatch counter Read Only offset 0x6B4 HTR13 orn mismatch counter Read Only offset 0x6B8 HTR14 orn mismatch counter Read Only offset 0x6C0 HTR0 skipped event counter Read Only offset 0x6C4 HTR1 skipped event counter Read Only offset 0x6C8 HTR2 skipped event counter Read Only offset 0x6CC HTR3 skipped event counter Read Only offset 0x6D0 HTR4 skipped event counter Read Only offset 0x6D4 HTR5 skipped event counter Read Only offset 0x6D8 HTR6 skipped event counter Read Only offset 0x6DC HTR7 skipped event counter Read Only offset 0x6E0 HTR8 skipped event counter Read Only offset 0x6E4 HTR9 skipped event counter Read Only offset 0x6E8 HTR10 skipped event counter Read Only offset 0x6EC HTR11 skipped event counter Read Only offset 0x6F0 HTR12 skipped event counter Read Only offset 0x6F4 HTR13 skipped event counter Read Only offset 0x6F8 HTR14 skipped event counter Read Only offset 0x700 HTR0 CT evn mismatch counter Read Only offset 0x704 HTR1 CT evn mismatch counter Read Only offset 0x708 HTR2 CT evn mismatch counter Read Only offset 0x70C HTR3 CT evn mismatch counter Read Only offset 0x710 HTR4 CT evn mismatch counter Read Only offset 0x714 HTR5 CT evn mismatch counter Read Only offset 0x718 HTR6 CT evn mismatch counter Read Only offset 0x71C HTR7 CT evn mismatch counter Read Only offset 0x720 HTR8 CT evn mismatch counter Read Only offset 0x724 HTR9 CT evn mismatch counter Read Only offset 0x728 HTR10 CT evn mismatch counter Read Only offset 0x72C HTR11 CT evn mismatch counter Read Only offset 0x730 HTR12 CT evn mismatch counter Read Only offset 0x734 HTR13 CT evn mismatch counter Read Only offset 0x738 HTR14 CT evn mismatch counter Read Only offset 0x740 HTR0 CT bcn mismatch counter Read Only offset 0x744 HTR1 CT bcn mismatch counter Read Only offset 0x748 HTR2 CT bcn mismatch counter Read Only offset 0x74C HTR3 CT bcn mismatch counter Read Only offset 0x750 HTR4 CT bcn mismatch counter Read Only offset 0x754 HTR5 CT bcn mismatch counter Read Only offset 0x758 HTR6 CT bcn mismatch counter Read Only offset 0x75C HTR7 CT bcn mismatch counter Read Only offset 0x760 HTR8 CT bcn mismatch counter Read Only offset 0x764 HTR9 CT bcn mismatch counter Read Only offset 0x768 HTR10 CT bcn mismatch counter Read Only offset 0x76C HTR11 CT bcn mismatch counter Read Only offset 0x770 HTR12 CT bcn mismatch counter Read Only offset 0x774 HTR13 CT bcn mismatch counter Read Only offset 0x778 HTR14 CT bcn mismatch counter Read Only offset 0x780 HTR0 CT orn mismatch counter Read Only offset 0x784 HTR1 CT orn mismatch counter Read Only offset 0x788 HTR2 CT orn mismatch counter Read Only offset 0x78C HTR3 CT orn mismatch counter Read Only offset 0x790 HTR4 CT orn mismatch counter Read Only offset 0x794 HTR5 CT orn mismatch counter Read Only offset 0x798 HTR6 CT orn mismatch counter Read Only offset 0x79C HTR7 CT orn mismatch counter Read Only offset 0x7A0 HTR8 CT orn mismatch counter Read Only offset 0x7A4 HTR9 CT orn mismatch counter Read Only offset 0x7A8 HTR10 CT orn mismatch counter Read Only offset 0x7AC HTR11 CT orn mismatch counter Read Only offset 0x7B0 HTR12 CT orn mismatch counter Read Only offset 0x7B4 HTR13 CT orn mismatch counter Read Only offset 0x7B8 HTR14 CT orn mismatch counter Read Only offset 0x7C0 HTR0 padded event counter Read Only offset 0x7C4 HTR1 padded event counter Read Only offset 0x7C8 HTR2 padded event counter Read Only offset 0x7CC HTR3 padded event counter Read Only offset 0x7D0 HTR4 padded event counter Read Only offset 0x7D4 HTR5 padded event counter Read Only offset 0x7D8 HTR6 padded event counter Read Only offset 0x7DC HTR7 padded event counter Read Only offset 0x7E0 HTR8 padded event counter Read Only offset 0x7E4 HTR9 padded event counter Read Only offset 0x7E8 HTR10 padded event counter Read Only offset 0x7EC HTR11 padded event counter Read Only offset 0x7F0 HTR12 padded event counter Read Only offset 0x7F4 HTR13 padded event counter Read Only offset 0x7F8 HTR14 padded event counter Read Only offset 0x800-838 HTR0 error counters Read Only 255 max. offset 0x840-878 HTR1 error counters Read Only 255 max. offset 0x880-8b8 HTR2 error counters Read Only 255 max. offset 0x8c0-8f8 HTR3 error counters Read Only 255 max. offset 0x900-938 HTR4 error counters Read Only 255 max. offset 0x940-978 HTR5 error counters Read Only 255 max. offset 0x980-9b8 HTR6 error counters Read Only 255 max. offset 0x9c0-9f8 HTR7 error counters Read Only 255 max. offset 0xa00-a38 HTR8 error counters Read Only 255 max. offset 0xa40-a78 HTR9 error counters Read Only 255 max. offset 0xa80-ab8 HTR10 error counters Read Only 255 max. offset 0xac0-af8 HTR11 error counters Read Only 255 max. offset 0xb00-b38 HTR12 error counters Read Only 255 max. offset 0xb40-b78 HTR13 error counters Read Only 255 max. offset 0xb80-bb8 HTR14 error counters Read Only 255 max. offset 0xbc0 event builder block counter Read Only offset 0xbc4 slink block counter Read Only offset 0xbc8 monitored event counter Read Only offset 0xbcc L1accept counter Read Only offset 0xbd0 Calib Trigger counter Read Only offset 0xbd4 CT EvN mismatch counter Read Only offset 0xbd8 CT BcN mismatch counter Read Only offset 0xbdc L1 EvN mismatch counter Read Only offset 0xbe0 L1 BcN mismatch counter Read Only offset 0xbe4 bcnt error counter Read Only offset 0xbe8 trigger rule violation counter Read Only offset 0xc00 control reg for HTR staus bit0 R/W bit 3-0 state to go bit 7-4 state transition threshold set this nibble to 0xf effectively disables it. offset 0xc04 control reg for HTR staus bit1 R/W offset 0xc08 control reg for HTR staus bit2 R/W offset 0xc0c control reg for HTR staus bit3 R/W offset 0xc10 control reg for HTR staus bit4 R/W offset 0xc14 control reg for HTR staus bit5 R/W offset 0xc18 control reg for HTR staus bit6 R/W offset 0xc1c control reg for HTR staus bit7 R/W offset 0xc20 control reg for HTR staus bit8 R/W offset 0xc24 control reg for HTR staus bit9 R/W offset 0xc28 control reg for HTR staus bit10 R/W offset 0xc2c control reg for HTR staus bit11 R/W offset 0xc30 control reg for HTR staus bit12 R/W offset 0xc34 control reg for HTR staus bit13 R/W offset 0xc38 controll reg for HTR staus bit14 R/W offset 0xe00 control reg for CT EvN mismatch R/W bit 3-0 state to go bit 7-4 state transition threshold offset 0xe04 control reg for CT BCN mismatch R/W offset 0xe08 control reg for L1 EvN mismatch R/W offset 0xe0c control reg for L1 BCN mismatch R/W offset 0xe10 control reg for bcnt error R/W offset 0x3000-37fc Slink fifo R/W (During write, LSB address bits are ignored) To read, slink must be disabled offset 0x4000-7ffc TCCrx event number fifo Read Only Each event occupies a set of four consecutive 32-bit words when address bit 3-0 = 0: bit 25 faked event number, bit 24 calibration trigger bit 23-0 event number, when address bit 3-0 = 4: bit 11-0 bx number, when address bit 3-0 = 8: bit 31-0 orbit number, when address bit 3-0 = c: not used all zero To get to these data, first read register 0x88. 0x4010 + bit 13-0 of register 0x88 is the starting address of the last set of event number data processed by DCC. increment the address by 0x10 goes one event further backward. When the address reaches 0x8000, wrap it back to 0x4000 Since FIFO contents never get cleared, do not read more events than the sum of counters 0xbcc and 0xbd0 0x4010 + bit 13-0 of register 0x88 is the starting address of the last set of event number data accepted by DCC. increment the address by 0x10 goes one event further backward. When the address reaches 0x8000, wrap it back to 0x4000 Since FIFO contents never get cleared, do not read more events than counter 0xbc0 indicates offset 0x8000-effc monitoring event window Read Only offset 0x10000-1fffc SDRAM memory window R/W offset 0x28000-2effc monitoring event window Read Only(bytes swapped to be big-Endian compliant) command and status register 0x0 read: bit 31 HTR does not stop after tcc reset bit 30-16 if '1', corresponding buffer for HTR channel 14 thru 0 is full bit 15 DCC not ready bit 14 DCC BUSY bit 13 TTCrx OVERFLOW bit 12 LED display error bit 11 PCI2 LRB monitor busy bit 10 PCI1 LRB monitor busy bit 9 TTCrx sync lost bit 8 TTCrx had double error bit 7 TTCrx had single error bit 6 TTCrx bcnt error bit 5 TTCrx not ready bit 4 single word HTR event seen bit 3 monitor buffer empty bit 2 monitor buffer full bit 1 slink full bit 0 slink down write: bit 31-5 not used bit 4 read LRB monitoring data bit 3 reset errors bit 2 reset TTCrx only bit 1 reset slink only bit 0 reset all registers with offset from 0x80 up. configuration register 0x4 read: bit 31-16 Xilinx firmware revision, 0x"2c22" now bit 15 if '1', trigger rule violation outputs TTS BUSY bit 14 if '1', monitor buffer full will stop event builder bit 13 if '1', send all data to downstream when ttc reset is received. if '0', flush all data when ttc reset is received. bit 12 if '1', TTS outputs correspond to bits 11-8 instead of TTS state when run bit(bit 0) is '1', this bit will be forced to '0' bit 11-8 used for TTS driver test bit 7 when run mode bit is '0', this bit is SLINK control/data bit. For SLINK test purpose bit 6 '1' when DDR memory random test going (only when run mode bit is '0') bit 5 '1' enables TTCrx broadcast commands bit 4 '1' enables automatic LRB monitor data readout -- bit 3 slink width '0' = 64(default), '1' = 32 -- before version 0x2c2e bit 3 if set to '1', overwrite HTR CRC. Default is no overwrite bit 2 slink test mode bit 1 slink enable bit 0 run mode write: bit 31-16 write '1' to bit n resets bit n-16 bit 15-0 write '1' to bit m sets bit m monitor buffer control register 0x8 read: bit 31-24 read only. records the occurence of enabled error conditions happened to recorded events bit 23-16 read back what was written to. bit 15-0 scale factor, when bits 23-16 are not all zero, these bits are bit 15 set to '1' when when at least 128 events are in the buffer bit 14-8 monitor buffer write pointer bit 7-0 number of events captured after trigger event. Normally it should be 0x40, but could be less if event building stops due to other problems. write: if bits 23-16 are not all zeros, the monitor buffer keeps overwriting old events after 128 events are filled until the enabled error consition happens and it records 64 more events and stops. To re-enabling it, this register must be written again. If bits 23-16 are all zeros, buffering stops after becoming full. bit 23 If set to '1', catches events when LRB event length greater than 512 and truncated bit 22 If set to '1', catches events when CRC error happened bit 21 If set to '1', catches events when oc/bcn mismatch happened bit 20 If set to '1', catches events when evn mismatch happened bit 19 If set to '1', catches events when HTR_CK set bit 18 If set to '1', catches events when HTR_EE set bit 17 If set to '1', catches events when HTR_BZ set bit 16 If set to '1', catches events when HTR_OW set bit 15-0 scale factor( = contents + 1) HTR enable register 0xc read: bit 31-18 always '0' bit 17-0 a '1' enables the corresponding HTR channel TTCrx TTCrx ID register 0x10 read: bit 31-20 always '0' bit 19-16 Orbit number initial value at broadcast OCreset command bit 15-14 always '0' bit 13-0 TTCrx ID write: write access is allowed only when run mode bit(bit 0 of register 0x4) is '0' bit 31-20 not used bit 19-16 Orbit number initial value at broadcast OCreset command bit 15-14 always '0' bit 13-0 TTCrx ID TTCrx I2C access register 0x14 read: bit 31-16 always '0' bit 15 I2C busy bit 14 I2C access failed bit 13 last I2C access was a write operation bit 7-0 read data from last I2C read access if bit 15-13 = "000" write: bit 31-16 not used bit 15 '0' => write to I2C register file, '1' => read from I2C register file bit 14-13 not used bit 12-8 register address bit 7-0 write data, ignored if bit 15 = '1'(read access) Please note that the I2C access is extremely slow. Before writing to this register, first make sure that I2C is not busy synchronization control register 0x18 read: bit 31-22 always '0' bit 21-0 as written write: write access is allowed only when run mode bit(bit 0 of register 0x4) is '0' bit 31-22 not used bit 21 If '1', disables level1 accept input. For debugging only bit 20 if '1', does not wait for next HTR data bit 19 if '1', does not skip HTR data bit 18 if '1', does not insert HTR data unless timeout occurs. bit 17 timeout enable. if '0', event build waits for level1 accept for ever. bit 16 timeout enable. if '0', event build waits for HTR data for ever. bit 15-8 timeout value in unit of 1/16 of microseconds. This is used for event number timeout bit 7-0 timeout value in unit of microseconds. This value should be greater than 128 for normal operation. This is for HTR data timeout Source ID register 0x1c read: bit 31-24 always '0' bit 23-0 source ID write: write access is allowed only when run mode bit(bit 0 of register 0x4) is '0' bit 31-24 not used bit 23-20 evt_ty bit 19-12 evt_stat bit 11-0 source ID BCNT offset register 0x20 read: bit 31-13 always '0' bit 12 if '1', ttc_bcntres only works once after system reset bit 11-0 BCNT offset write: write access is allowed only when run mode bit(bit 0 of register 0x4) is '0' bit 31-20 not used bit 12 ttc_bcntres control bit bit 11-0 BCNT offset SDRAM memory page register 0x80 read: bit 31-7 always '0' bit 6-0 SDRAM page number write: write access is allowed only when run mode bit(bit 0 of register 0x4) is '0' If run bit is '1', write to 0x80 increments page number by one. bit 31-7 not used bit 6-0 SDRAM page number, each page is 64kbytes size monitor event word count 0x84 read: bit 31-13 always '0' bit 12-0 monitored event size in 32-bit word. In run mode, it returns '0' if there is no data avaiable TTCrx fifo pointers 0x88 read: bit 31-30 always '0' bit 29-16 TTCrx fifo write pointer bit 15-14 always '0' bit 13-0 TTCrx fifo read pointer Slink fifo pointers 0x8c read: bit 31-25 always '0' bit 24-16 Slink fifo write pointer bit 15-9 always '0' bit 8-0 Slink fifo read pointer front panel LED display Blinking at 1Hz means error detected. If error does not persist, blinking lasts 5 to 10 seconds. Standard initialization procedure: operation comments write 0xffff0000 to 0x4 clear configuration register write n to 0x8 set up monitoring event scale factor to n+1 write 0x????? to 0xc set up HTR enable register write I2C_ID to 0x10 set up I2C ID register write 0x4 to 0x0 reset TTCrx set up log1,log2,LRBs set up configuration register, but do not put into run mode write 0x3 to 0x0 reset all registers and slink write 0x3 to 0x4 set to run mode and enable slink write 0x3 to 0x0 reset all registers and slink after run started When in run mode, SDRAM memory write is ignored and read returns garbbage data. When not in run mode, write to SDRAM page register 0x80 enables access to any memory location within that 64kbyte window. When not in run mode, data written to the Slink fifo range will be output to Slink if the latter is enabled. In run mode, writes to Slink fifo are ignored. Readout from Slink fifo does not change the status of the fifo. It always contains the last 512 32-bit words sent to Slink. You can access all registers in any modes. To read the monitored event, first read 0x84. In run mode(bit 0 of 0x4 set), this register gives the word count of the event pointed by the page register, it returns 0 when no event is available. Writing anything to 0x80 moves to next buffer when 0x84 is non zero. If 0x84 is zreo, the write to 0x84 is ignored. pci interface bar0 offset 0x0 lrb1 base address register bar0 offset 0x4 lrb2 base address register bar0 offset 0x8 lrb3 base address register bar0 offset 0xc HTR enable register x"00000" & "000" & lrb3 & lrb2 & lrb1; *************************************************************************** resync algorithm *************************************************************************** if register 0x18 is set to all zero, DCC can resync HTR event data based on event numbers as described below: If DCC event number and HTR event number a. match or b. their four LSBs are the same and the four LSBs of HTR event number are consecutive, event is accepted. Otherwise, DCC event number is compared with that of the next HTR event, if next event and the DCC event is of different type(one is calibration and the other is normal data), current event will be accepted without further check. If the next HTR event number is a. equal or b. smaller and the the difference is less than 16 and the four LSBs of HTR event number are consecutive, DCC will skip the current HTR event. If the next HTR event number is bigger and the the difference is less than 16 and the four LSBs of HTR event number are consecutive, DCC will pad in an empty event. Otherwise, DCC will read the current HTR event. In whichever case, as long as the errors do not persist, DCC will eventually resync the HTR data. *************************************************************************** configuration FLASH programming *************************************************************************** to access configuration control chip, use BAR1 (LOG3_mem) BAR1 occupies 16 bytes space : 0x0 write FLASH address 0x4 write/read FLASH data 0x8 write resets virtex2 chip 0xC write 0xa5 to this address starts reconfiguration All accesses have to be 32-bit word. Byte enable signals are assumed to be all active. flash memory address register has address 0x0 and is write-only. Only data bits 20-0 are used flash mmeory data register has address 0x4. write access uses bits 7-0 for flash data. read access returns bits 31-24 all '0' bits 23-16 DCC's cpld firmware version bits 15-14 always '0' bit 13 is '1' indicates that configuration started from 0xc0000 (configured with backup sector) bit 12 pci3 done signal inverted bit 11 pci2 done signal inverted bit 10 pci1 done signal inverted bit 9 virtex done signal inverted bit 8 always '0' bit 7-0 are flash data address register does not auto-increment write to data register automatically starts the execution of the command for flash memory operation, please refer to AM29F080B data sheet Following any wirte/read operation, flash controller automatically reads the flash for later access !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! It is important to notice that any read access always gets the data resulted from the last read/write access. !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! Any access takes 2+ microsecond to finish. Any new access before the FLASH is ready again will result in a retry. to start a reconfiguration, first write the starting address to flash memory address register for normal configuration, set address to 0xCF100, it reconfigures all FPGAs for pci3 interface backup configuration, set address to 0xBF100, it only reconfigures pci3 interface then write 0xa5 to address 0xC, this starts the reconfiguration pci3 interface has two sets of configuration data in the flash memory, one starts at 0xc0000, and the other starts at 0xf0000. Never update two sets at the same time. Always reconfigure after updating one set. Only if it works correctly, then start updating the other. flash memory contents 0xc0000 - pci3 backup 0xd0000 - pci1 0xe0000 - pci2 0xf0000 - pci3 normal 0x100000 - virtex2