Device Utilization Summary | [-] |
Slice Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Registers |
5,475 |
54,576 |
10% |
|
Number used as Flip Flops |
5,471 |
|
|
|
Number used as Latches |
4 |
|
|
|
Number used as Latch-thrus |
0 |
|
|
|
Number used as AND/OR logics |
0 |
|
|
|
Number of Slice LUTs |
4,582 |
27,288 |
16% |
|
Number used as logic |
4,147 |
27,288 |
15% |
|
Number using O6 output only |
2,748 |
|
|
|
Number using O5 output only |
161 |
|
|
|
Number using O5 and O6 |
1,238 |
|
|
|
Number used as ROM |
0 |
|
|
|
Number used as Memory |
114 |
6,408 |
1% |
|
Number used as Dual Port RAM |
0 |
|
|
|
Number used as Single Port RAM |
0 |
|
|
|
Number used as Shift Register |
114 |
|
|
|
Number using O6 output only |
76 |
|
|
|
Number using O5 output only |
1 |
|
|
|
Number using O5 and O6 |
37 |
|
|
|
Number used exclusively as route-thrus |
321 |
|
|
|
Number with same-slice register load |
251 |
|
|
|
Number with same-slice carry load |
70 |
|
|
|
Number with other load |
0 |
|
|
|
Number of occupied Slices |
1,840 |
6,822 |
26% |
|
Number of MUXCYs used |
676 |
13,644 |
4% |
|
Number of LUT Flip Flop pairs used |
5,746 |
|
|
|
Number with an unused Flip Flop |
1,312 |
5,746 |
22% |
|
Number with an unused LUT |
1,164 |
5,746 |
20% |
|
Number of fully used LUT-FF pairs |
3,270 |
5,746 |
56% |
|
Number of unique control sets |
214 |
|
|
|
Number of slice register sites lost to control set restrictions |
742 |
54,576 |
1% |
|
Number of bonded IOBs |
115 |
296 |
38% |
|
Number of LOCed IOBs |
86 |
115 |
74% |
|
IOB Flip Flops |
20 |
|
|
|
IOB Master Pads |
25 |
|
|
|
IOB Slave Pads |
25 |
|
|
|
Number of bonded IPADs |
6 |
16 |
37% |
|
Number of LOCed IPADs |
6 |
6 |
100% |
|
Number of bonded OPADs |
4 |
8 |
50% |
|
Number of LOCed OPADs |
4 |
4 |
100% |
|
Number of RAMB16BWERs |
40 |
116 |
34% |
|
Number of RAMB8BWERs |
1 |
232 |
1% |
|
Number of BUFIO2/BUFIO2_2CLKs |
6 |
32 |
18% |
|
Number used as BUFIO2s |
6 |
|
|
|
Number used as BUFIO2_2CLKs |
0 |
|
|
|
Number of BUFIO2FB/BUFIO2FB_2CLKs |
5 |
32 |
15% |
|
Number used as BUFIO2FBs |
5 |
|
|
|
Number used as BUFIO2FB_2CLKs |
0 |
|
|
|
Number of BUFG/BUFGMUXs |
15 |
16 |
93% |
|
Number used as BUFGs |
15 |
|
|
|
Number used as BUFGMUX |
0 |
|
|
|
Number of DCM/DCM_CLKGENs |
6 |
8 |
75% |
|
Number used as DCMs |
6 |
|
|
|
Number used as DCM_CLKGENs |
0 |
|
|
|
Number of ILOGIC2/ISERDES2s |
3 |
376 |
1% |
|
Number used as ILOGIC2s |
3 |
|
|
|
Number used as ISERDES2s |
0 |
|
|
|
Number of IODELAY2/IODRP2/IODRP2_MCBs |
0 |
376 |
0% |
|
Number of OLOGIC2/OSERDES2s |
17 |
376 |
4% |
|
Number used as OLOGIC2s |
17 |
|
|
|
Number used as OSERDES2s |
0 |
|
|
|
Number of BSCANs |
1 |
4 |
25% |
|
Number of BUFHs |
0 |
256 |
0% |
|
Number of BUFPLLs |
0 |
8 |
0% |
|
Number of BUFPLL_MCBs |
0 |
4 |
0% |
|
Number of DSP48A1s |
0 |
58 |
0% |
|
Number of GTPA1_DUALs |
1 |
2 |
50% |
|
Number of ICAPs |
1 |
1 |
100% |
|
Number of MCBs |
0 |
2 |
0% |
|
Number of PCIE_A1s |
0 |
1 |
0% |
|
Number of PCILOGICSEs |
0 |
2 |
0% |
|
Number of PLL_ADVs |
0 |
4 |
0% |
|
Number of PMVs |
0 |
1 |
0% |
|
Number of STARTUPs |
0 |
1 |
0% |
|
Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
Number of RPM macros |
10 |
|
|
|
Average Fanout of Non-Clock Nets |
3.06 |
|
|
|