ATM daughterboard tester v3 spec F and SA response tester does not respond to f = x"3", x"7" and x"9" when f = x"0", timing conforms to SDS timing (YSSIR* low for one clock cycle) for other f, YSSIR* low lasts for three cycles. for f = x"8", data are written to a fifo which is 1023 deep for f = x"0", data are read from the fifo for f = x"1" sa = 0, bit 15-8 fifo write address bit 7-0 bit 7-0 fifo read address bit 7-0 for f = x"1" sa = 1, bit 15-12 last tKO operation f bit 11 not used bit 10-0 last TKO operation sa For f = x"a", x"b", x"c" and x"d", each has a register for each sa. These registers can be read out by f = x"2', x"3", x"4" and x"5" respectively. For f = x"e" and x"6", four registers are implemented: address 0xe000 r/w CSR register bit 15-8 tester firmware version (0x03 the latest) This portion is read only bit 7 unused bit 6 when '0', force SDS read length to be multiples of 3 (rounded up) bit 5 When '0', SDSREQ interval controlled by register 0xe006. When '1', random interval. bit 4 when '0', G_trig interval controlled by register 0xe004. When '1', random interval. bit 3 when '0', SDS read length controlled by register 0xe002. When '1', random length. bit 2 when '1', SDS always gets Q response, i.e. SDS never ends by Q. bit 1-0 when "01", sequential data when "10", pseudo-random data when others, data written to 0x8000 address 0xe002 r/w SDS length register ( minimum 2. If less than 2, still reads 2) address 0xe004 r/w g_trig interval register, unit is 150ns address 0xe006 r/w SDSREQ interval register, unit is 150ns address 0xe008 r/w random burst length mask register, set bits 15 through N to '1' will limit the burst length to N-bit long. address 0xe00a r/w random G_trig interval mask register, set bits 15 through N to '1' will limit the burst length to N-bit long. address 0xe00c r/w random SDSREQ interval mask register, set bits 15 through N to '1' will limit the burst length to N-bit long. test header signals: pin 1 SPI_SCK pin 2 SPI_CSn pin 3 SPI_SO pin 4 SPI_SI pin 14 SDSREQ pin 15 G_TRIG pin 16 TKOCLK/2 pin 17 DOIT* SPI interface responds only to a RDID instruction (0xF9) of M25P32 FLASH memory and returns 3 bytes of ID as 0x202016 This version is designed for new ATM daughter board, it does not work for old daughter board JTAG downloading.