1/11/07	some bugs were found and the new version is 0x12

ATM_db UDP port mem

commands 0x0-0x5

0x0-0x1		w		if bit 0 is 1, resets UDP timeout, TKO interface, SDRAM FIFO, error status bits and counters in range 0x200-0x27f
				if bit 1 is 1, resets TKO interface including error bits and counter 0x240-0x247, SDRAM FIFO 
				if bit 2 is 1, resets error status bits
				if bit 3 is 1, resets counters in range 0x200-0x27f except 0x240-0x247 which is reset by reset TKO interface command
				bits 4-6 not used
				if bit 7 is 1, resets ATM board
				if bit 8 is 1, puts daughter mode in memory test mode (see register 0x10b bit 1)
				if bit 9 is 1, puts daughter board in SDS debug mode (see register 0x10b bit 2)
				if bit 10is 1, enables to access SPI interface of ATM board (v2 daughter board only) 
				bits 11-15 not used

0x2-0x3		w		starts FLASH operation

0x4-0x5		w		FPGA reprogram command. wirte 0xa5 to configure with default data, or write 0x1a5 to configure with backup data. 


registers 0x100-0x11f

0x100-0x101	r/w	SDS start timer period in unit of 100us, counter stays cleared during the whole SDS burst
0x102-0x103	r/w	SDS starts after N+1 G-trig, counter stays cleared during the whole SDS burst
0x104-0x105	r/w	TKO status for read, start/stop SDS for write
		read:
			bit 0	SDS stopped by Q
			bit 1	SDS stopped by UDP command
			bit 2	SDS started by UDP command
			bit 3	SDS started by G_trig
			bit 4	SDS started by timer
			bit 5	SDS started by SDSREQ
			bit 7-6 not used
			bit 8	last TKO operation got Q response
			bit 9	last TKO operation got YSSIR response
			bit 10	SDRAM FIFO almost full
			bit 11	SDS is going
			bit 12	SDS burst length counter has overflowed
			bit 13	Q* = 1 happened not at cell boundary
			bit 14	UDP read/write ATM FIFO attempted while SDS enabled
			bit 15	not used, reads as 0

		write:	bit 0	not used
			bit 1	stop SDS
			bit 2	start SDS
			bit 3-15not used

0x106-0x107	r/w	SDS control register
			bit 0-3	not used
			bit 4	enable G_trig to start SDS when set to 1
			bit 5	enable timer to start SDS when set to 1
			bit 6	enable UDP command to start SDS when set to 1
			bit 7	enable SDSREQ to start SDS when set to 1
			bit 8-15not used

0x108-0x109	r/w	test register for exercising UDP read/write

0x10a-0x10b	r	daughter board status register
			bit 0	if 1, daughter board is configured from backup configuration data 
			bit 1	if 1, daughter board in SDS debug mode. In this mode, no flag cells
				are inserted. Also SDS halts when SDRAM FIFO is full.
			bit 2	if 1, daughter board in memory test mode. In this mode, pseudo-random
				sequential data is written to SDRAM memory instead of SDS data.
				This data is generated by a 16-bit LFSR with bit0 input as an
				XNOR of bit 15,14,12 and 3 as input of bit 0
			bit 3	if 1, sccess PCI port instead of the on-board FLASH (version 2 daughterboard only)
			bit 4	SDRAM FIFO almost full
			bit 5	UDP acknowledge timeout occured
			bit 6-7	not used, reads as 0
			bit 8-10inverted lock signal of three DCM used. Should always be 0
			bit 9-13not used, reads as 0
			bit 14	TX_FIFO_AFULL signal
			bit 15	TCP_ESTABLISH signal

0x10c-0x10d	r	SDRAM FIFO status (for test purposes only)
			bit 0-7	SDRAM DCM phase shift
			bit 8-11not used, reads as 0
			bit 12	SDRAM FIFO output empty
			bit 13	SDRAM DCM phase control ready
			bit 14	SDRAM initialization done
			bit 15	SDRAM FIFO ready

0x10e-0x10f	r	daughter board firmware version, 0x0011 as of 01/10/2007

0x110-0x113	r	SiTCP firmware version

0x114-0x115		not used, reads as 0

0x116-0x117	r	SSN device status (used to define MAC address)
			bit 0	if 1, SSN readout done
			bit 1	if 1, SSN readout CRC correct
			bit 2-7	not used, reads as 0
			bit 8-15calculated SSN CRC 

0x118-0x11f	r	SSN readout data. MAC address x"005051" & SSN(29 downto 8) & "00"

0x120-0x121	r	bit 15-4	all zero
		r	bit 3-0		SDS sequential number bits 35-32
0x122-0x123	r	SDS sequential number bits 31-16
0x124-0x125	r	SDS sequential number bits 15-0 

counters 0x200-0x27f

0x200-0x207	r	number of words written to SDRAM FIFO
0x208-0x20f	r	total number of words SDS read from ATM
0x210-0x217	r	total number of SDS bursts
0x218-0x21f	r	total number of words lost due to SDRAM FIFO almost full, it is always multiple of three as long as
			SDS readout number of words from ATM is multiple of three  
0x220-0x227	r	number of SDS bursts totally lost due to SDRAM FIFO almost full
0x228-0x22f	r	number of SDS bursts partially lost due to SDRAM FIFO almost full
0x230-0x23f	r	not used, read as all zero
0x240-0x247	r	number of words in the SDRAM FIFO
0x248-0x24f	r	time SDRAM is empty from first write to SiTCP to last write in units of 40ns
0x250-0x257	r	time TX_FIFO_AFULL is high from first write to SiTCP to last write in units of 40ns
0x258-0x25f	r	total time elapsed from first write to SiTCP to last write in units of 40ns
0x260-0x267	r	total TCP connection on time in units of 40ns
0x268-0x26f	r	total time with TCP_ESTABLISH high and TX_FIFO_AFULL low
0x270-0x277	r	total number of bytes written to SiTCP
0x278-0x27f	r	number of errors detected on pseudo-random data written to SiTCP

FLASH access space

0x400-0x7ff		FLASH command and data buffer

TKO access is mapped to address space 0x8000-0xffff
address bit 15 is always '1' and address bit 0 is always '0'
data length must always equals 2.
address bits 14-12 mapped to FN 2-0
address bits 11-1 mapped to SA 10-0
write operation will force FN bit 3 to '1'
read operation will force FN bit 3 to '0'