ATM_db UDP port memory map

0x0		w		if bit 0 is '1', resets timeout bit
				if bit 1 is '1', resets TKO interface, SDRAM FIFO 
				if bit 2 is '1' and bit 6 of 0x506 is '1', starts SDS once
				if bit 3 is '1' sends 16-bit pseudo-random sequencial data to SiTCP

0x2		w		starts FLASH operation

0x4		w		FPGA reprogram command lower byte, data must be oxa5
0x5		w		FPGA reprogram command upper byte.
					data = 0 to reconfigure with default file
					data = 1 to reconfigure with backup file

FLASH access space

0x400-403		FLASH command buffer
0x600-0x7ff		FLASH data buffer

common registers space

0x500		r		Last TKO read data bit 7-0
0x501		r		Last TKO read data bit 15-8
0x502		r		Last TKO write data bit 7-0
0x503		r		Last TKO write data bit 15-8
0x504		r		bit 7-4 Last TKO FN
					bit 3 always '0'
					bit 2-0 Last TKO SA bit 10-8
0x505		r		Last TKO SA bit 7-0
0x506		r/w	bit 7-4
					bit 7 unused
					bit 6 when '1' enables start DSD by sending UDP command
					bit 5 when '1' enables start DSD by timer(at 17 us break)
					bit 4 when '1' enables start DSD by counting G_trig
					bit 3 always '0'
			ro		bit 2 '1' if last TKO failed due to collision with FIFO read
			ro		bit 1 '1' if last TKO got YSSIR response
			ro		bit 0 '1' if last TKO got Q response
0x507		r/w	G_TRIG count threshold, default to 0xff
0x508		r/w	test register
0x509		r/w	test register
0x50a		r		my_MSS bit 7-0
0x50b		r		bit 7-4 always '0'
					bit 3-0 my_MSS bit 11-8
0x50c		r		my_TCP_PORT bit 7-0
0x50d		r		my_TCP_PORT bit 15-8
0x50e		r		my_UDP_PORT bit 7-0
0x50f		r		my_UDP_PORT bit 15-8
0x510		r		TCP_version bit 7-0
0x511		r		TCP_version bit 15-8
0x512		r		TCP_version bit 23-16
0x513		r		TCP_version bit 31-24
0x514		r		calculated CRC of SSN(serial number)
0x515		r		always '0'
0x516		r		bit 7	if '1', FPGA configured with backup configuration data
					bit 6-3 always '0'
					bit 2 '1' if local acknowledge timeout has happened
					bit 1 '1' if SSN CRC check succeded
					bit 0 '1' if SSN read out done
0x517		r		ATM_DB firmware version
0x518		r		SSN bit 7-0 should always be 0x1
0x519		r		SSN bit 15-8 (used as MAC bit 11-4, MAC bit 3-0 are all '0')
0x51a		r		SSN bit 23-16 (used as MAC bit 19-12)
0x51b		r		SSN bit 31-24 (used as MAC bit 27-20)
0x51c		r		SSN bit 39-32 (used as MAC bit 35-28)
0x51d		r		SSN bit 47-40 (used as MAC bit 43-39)
0x51e		r		SSN bit 55-48 (bit 3-0 used as MAC bit 47-44)
0x51f		r		SSN bit 63-56

TKO access is mapped to address space 0x8000-0xffff
address bit 15 is always '1' and address bit 0 is always '0'
data length must always equals 2.
address bits 14-12 mapped to FN 2-0
address bits 11-1 mapped to SA 10-0
write operation will force FN bit 3 to '1'
read operation will force FN bit 3 to '0'

ATM tester firmware spec

Any TKO function except F(3), F(7) and F(9) will be accepted and
return with YSSIR and Q responses.
F(8) is FIFO write and F(0) is FIFO read. SA is ignored for F(8) and F(0).
The FIFO can hold a maximum of 1023 words. There is no overwrite protection.
When FIFO is empty, Q responses will be suppressed for further FIFO read and
FIFO remains empty.
F(1) reads FIFO's write and read pointers, though only the lower 8 bits
of each are available. Write pointer occupies the high byte and read pointer
the lower byte.
For other legal write and read operations, F bits 2-0 are ignored.
That is, data access will be to/from the same location as specified by SA.
So there are in total 2048 registers for non FIFO TKO accesses.