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# Generated by PlanAhead 14.4.1 built on 'Tue Dec 18 05:21:09 MST 2012' by 'xbuild'
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# Constraints from file : 'AMC13_T1.ucf'
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create_clock -period 4.288 -name sys_clk [get_ports sys_clk_p]
set_propagated_clock [get_ports sys_clk_p]
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sys_clk]
create_clock -period 250.000 -name SPI_SCK [get_ports SPI_SCK]
#set_clock_groups 
create_clock -period 5.000 -name TTS_clk [get_pins i_ttc_if/i_TTS_clk_buf/O]
# A PERIOD placed on an internal net will result in a clock defined with an internal source. Any upstream source clock latency will not be analyzed
#create_clock -period 6.000 -name CDRclk [get_pins i_ttc_if/i_CDRclk_buf/O]
create_clock -period 6.237 -name CDRclk_p [get_ports CDRclk_p]
#set_input_delay -clock CDRclk_p -max 3.500 [get_ports CDRdata_p]
#set_input_delay -clock CDRclk_p -min 2.500 [get_ports CDRdata_p]
# D:/iseproj/AMC1310G/AMC13_T1.ucf:43
create_clock -period 24.000 -name TTCclk_p [get_ports TTCclk_p]
create_clock -period 4.000 -name AMC_REFCLK_P [get_ports AMC_REFCLK_P]
create_clock -period 4.000 -name AMC_UsrClk [get_pins i_AMC_if/i_UsrClk_buf/O]
create_clock -period 8.000 -name clk125 [get_pins i_clk125_buf/O]
create_clock -period 32.000 -name ipb_clk [get_pins i_ipb_clk_buf/O]
create_clock -period 5.000 -name sysclk [get_pins i_sysclk_buf/O]
create_clock -period 20.000 -name DRPclk [get_pins i_DRPclk_buf/O]
create_clock -period 3.200 -name ClientClk2x [get_pins g_TCPIP_if.i_TCPIP_if/i_ClientClk2X/O]
#create_clock -period 3.200 -name ClientClk2x0 [get_pins i_TCPIP_if/i_ClientClk2X0/O]
#create_clock -period 3.200 -name ClientClk2x1 [get_pins i_TCPIP_if/i_ClientClk2X1/O]
#create_clock -period 3.200 -name ClientClk2x2 [get_pins i_TCPIP_if/i_ClientClk2X2/O]
create_clock -period 6.400 -name ClientClk [get_pins g_TCPIP_if.i_TCPIP_if/i_ClientClk/O]
create_clock -period 3.103 -name SFP_txusrclk [get_pins g_TCPIP_if.i_TCPIP_if/i_txusrclk/O]
create_clock -period 3.103 -name SFP0_rxusrclk [get_pins g_TCPIP_if.i_TCPIP_if/g_SFP_rxusrclk[0].i_SFP_rxusrclk/O]
create_clock -period 3.103 -name SFP1_rxusrclk [get_pins g_TCPIP_if.i_TCPIP_if/g_SFP_rxusrclk[1].i_SFP_rxusrclk/O]
create_clock -period 3.103 -name SFP2_rxusrclk [get_pins g_TCPIP_if.i_TCPIP_if/g_SFP_rxusrclk[2].i_SFP_rxusrclk/O]
set_clock_groups -asynchronous -group [list sysclk DRPclk] -group [list ClientClk2x ClientClk] -group [list ipb_clk clk125] -group [get_clocks -include_generated_clocks sys_clk] -group SPI_SCK -group TTS_clk -group TTCclk_p -group AMC_UsrClk -group [get_clocks -include_generated_clocks SFP_txusrclk] -group SFP0_rxusrclk -group SFP1_rxusrclk -group SFP2_rxusrclk -group [get_clocks -include_generated_clocks CDRclk_p] -group AMC_REFCLK_P
#set_clock_groups -asynchronous -group [list sysclk DRPclk] -group [list ClientClk2x0 ClientClk2x1 ClientClk2x2 ClientClk] -group [list ipb_clk clk125] -group [get_clocks -include_generated_clocks sys_clk] -group SPI_SCK -group TTS_clk -group TTCclk_p -group AMC_UsrClk -group [get_clocks -include_generated_clocks SFP_txusrclk] -group SFP0_rxusrclk -group SFP1_rxusrclk -group SFP2_rxusrclk -group [get_clocks -include_generated_clocks CDRclk_p] -group AMC_REFCLK_P
set_false_path -from [get_pins {conf_reg[8]/C}]
set_false_path -from [get_pins {g_TCPIP_if.i_TCPIP_if/IPADDR_reg[?][*]/C}]
#set_false_path -to [get_pins i_TCPIP_if/i_TCPIP?/i_dataFIFO/i_FIFO_*/bl.fifo_36_inst_bl.fifo_36_bl/RST]
#set_false_path -to [get_pins {i_TCPIP_if/g_evt_FIFO[?].i_evt_FIFO/g_FIFO[?].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl/RST}]
set_false_path -from [get_pins g_TCPIP_if.i_TCPIP_if/*i_TCPIP/SEG_ACK_reg[*]/C]
set_false_path -to [get_pins g_TCPIP_if.i_TCPIP_if/*i_TCPIP/i_headerFIFO/bl.fifo*/RST]
set_false_path -to [get_pins {g_TCPIP_if.i_TCPIP_if/*i_TCPIP/i_ReTx_FIFO/*/bl.fifo*/RST}]
#set_false_path -to [get_pins g_TCPIP_if.i_TCPIP_if/*i_TCPIP/i_ReTx_FIFO/FIFO6463/bl.fifo*/RST]
set_false_path -to [get_pins {g_TCPIP_if.i_TCPIP_if/*i_TCPIP/i_dataFIFO/*/bl.fifo*/RST}]
#set_false_path -to [get_pins {g_TCPIP_if.i_TCPIP_if/*i_TCPIP/i_dataFIFO/g_FIFO_j[?].g_FIFO[?].i_FIFO/bl.fifo*/RST}]
#set_false_path -to [get_pins {g_TCPIP_if.i_TCPIP_if/*i_TCPIP/i_dataFIFO/FIFO6463/bl.fifo*/RST}]
#set_false_path -to [get_pins {g_TCPIP_if.i_TCPIP_if/*i_TCPIP/i_dataFIFO/FIFO65/bl.fifo*/RST}]
#set_false_path -to [get_pins {i_TCPIP_if/g_evt_FIFO[?].i_evt_FIFO/g_FIFO[?].i_FIFO/bl.fifo*/RST}]
set_false_path -to [get_pins {g_TCPIP_if.i_TCPIP_if/g_evt_FIFO[?].i_evt_fifo/bl.fifo*/RST}]
#set_multicycle_path -from [get_pins i_counter_?/ramb_bl.ramb??_dp_bl.ram??_bl/CLKARDCLK] -to [get_pins i_counter_?/ramb_bl.ramb??_dp_bl.ram??_bl/CLKARD] 2
set_property ASYNC_REG true [get_cells *SyncRegs*]
set_property LOC BUFHCE_X0Y80 [get_cells i_SPI_SCK_buf]
#create_clock -name CDRclk_p -period 6.000 [get_ports CDRclk_p]
#set_output_delay -clock CDRclk_p -max 5 [get_ports DIV_nRST]
#set_output_delay -clock CDRclk_p -max 4 [get_ports TTCdata_p]
#set_input_delay -clock CDRclk_p -max 3.5 [get_ports CDRdata_p]
#set_input_delay -clock CDRclk_p -min 2.5 [get_ports CDRdata_p]
#set_property IOB TRUE [get_ports DIV_nRST]
#set_property IOB TRUE [get_ports TTCdata_p]
#set_property IOB TRUE [get_ports CDRdata_p]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXN[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXP[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXN[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXP[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXN[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXP[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXN[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXP[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXN[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXP[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXN[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXP[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXN[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXP[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXN[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXP[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXN[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXP[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXN[12]}]
set_property LOC XADC_X0Y0 [get_cells i_sysmon_if/I_XADC]
set_property PACKAGE_PIN J28 [get_ports {VAUXN[3]}]
set_property PACKAGE_PIN L23 [get_ports {VAUXN[8]}]
set_property PACKAGE_PIN L27 [get_ports {VAUXN[12]}]
set_property PACKAGE_PIN H29 [get_ports {VAUXN[10]}]
set_property PACKAGE_PIN J22 [get_ports {VAUXN[2]}]
set_property PACKAGE_PIN L26 [get_ports {VAUXP[12]}]
set_property PACKAGE_PIN L30 [get_ports {VAUXP[11]}]
set_property PACKAGE_PIN J27 [get_ports {VAUXP[3]}]
set_property PACKAGE_PIN J21 [get_ports {VAUXP[2]}]
set_property PACKAGE_PIN L22 [get_ports {VAUXP[8]}]
set_property PACKAGE_PIN K21 [get_ports {VAUXN[9]}]
set_property PACKAGE_PIN L25 [get_ports {VAUXP[5]}]
set_property PACKAGE_PIN J23 [get_ports {VAUXP[0]}]
set_property PACKAGE_PIN J26 [get_ports {VAUXN[4]}]
set_property PACKAGE_PIN K30 [get_ports {VAUXN[11]}]
set_property PACKAGE_PIN K25 [get_ports {VAUXN[5]}]
set_property PACKAGE_PIN L21 [get_ports {VAUXP[9]}]
set_property PACKAGE_PIN K26 [get_ports {VAUXP[4]}]
set_property PACKAGE_PIN J29 [get_ports {VAUXP[10]}]
set_property PACKAGE_PIN J24 [get_ports {VAUXN[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VAUXP[12]}]
set_property PACKAGE_PIN D13 [get_ports SPI_SCK]
set_property IOSTANDARD LVCMOS25 [get_ports SPI_SCK]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets SPI_SCK]
set_property PACKAGE_PIN A13 [get_ports SPI_CS_b]
set_property IOSTANDARD LVCMOS25 [get_ports SPI_CS_b]
set_property PACKAGE_PIN A11 [get_ports SPI_MOSI]
set_property IOSTANDARD LVCMOS25 [get_ports SPI_MOSI]
set_property PACKAGE_PIN A12 [get_ports SPI_MISO]
set_property IOSTANDARD LVCMOS25 [get_ports SPI_MISO]
set_property SLEW SLOW [get_ports SPI_MISO]
set_property PACKAGE_PIN AJ27 [get_ports DIV4]
set_property IOSTANDARD LVCMOS25 [get_ports DIV4]
set_property SLEW SLOW [get_ports DIV4]
set_property IOSTANDARD LVCMOS25 [get_ports DIV_nRST]
set_property DRIVE 12 [get_ports DIV_nRST]
set_property SLEW FAST [get_ports DIV_nRST]
set_output_delay -clock CDRclk_p -max 3.000 [get_ports DIV_nRST]
set_output_delay -clock CDRclk_p -min 1.000 [get_ports DIV_nRST]
set_property PACKAGE_PIN AE28 [get_ports CDRclk_p]
set_property PACKAGE_PIN AG30 [get_ports TTS_out_p]
set_property PACKAGE_PIN AG29 [get_ports TTCclk_p]
#TTCdata_p has reversed polarity
set_property PACKAGE_PIN N24 [get_ports TTC_LOS]
set_property IOSTANDARD LVCMOS33 [get_ports TTC_LOS]
set_property PACKAGE_PIN P23 [get_ports TTC_LOL]
set_property IOSTANDARD LVCMOS33 [get_ports TTC_LOL]
set_property PACKAGE_PIN G8 [get_ports GbE_REFCLK_P]
set_property PACKAGE_PIN G7 [get_ports GbE_REFCLK_N]
set_property PACKAGE_PIN E8 [get_ports SFP_REFCLK_P]
set_property PACKAGE_PIN E7 [get_ports SFP_REFCLK_N]
set_property PACKAGE_PIN N8 [get_ports AMC_REFCLK_P]
set_property PACKAGE_PIN N7 [get_ports AMC_REFCLK_N]
#AMC1
set_property LOC GTXE2_CHANNEL_X0Y0 [get_cells i_AMC_if/i_AMC_wrapper/i_AMC_GTX5Gpd_init/amc_gtx5Gpd_i/gt0_amc_gtx5Gpd_i/gtxe2_i]
set_property PACKAGE_PIN AA3 [get_ports {AMC_RXN[1]}]
set_property PACKAGE_PIN Y2 [get_ports {AMC_TXP[1]}]
set_property PACKAGE_PIN Y1 [get_ports {AMC_TXN[1]}]
set_property PACKAGE_PIN AA4 [get_ports {AMC_RXP[1]}]
#AMC2
set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells i_AMC_if/i_AMC_wrapper/i_AMC_GTX5Gpd_init/amc_gtx5Gpd_i/gt1_amc_gtx5Gpd_i/gtxe2_i]
set_property PACKAGE_PIN Y5 [get_ports {AMC_RXN[2]}]
set_property PACKAGE_PIN V2 [get_ports {AMC_TXP[2]}]
set_property PACKAGE_PIN V1 [get_ports {AMC_TXN[2]}]
set_property PACKAGE_PIN Y6 [get_ports {AMC_RXP[2]}]
#AMC3
set_property LOC GTXE2_CHANNEL_X0Y2 [get_cells i_AMC_if/i_AMC_wrapper/i_AMC_GTX5Gpd_init/amc_gtx5Gpd_i/gt2_amc_gtx5Gpd_i/gtxe2_i]
set_property PACKAGE_PIN W3 [get_ports {AMC_RXN[3]}]
set_property PACKAGE_PIN U4 [get_ports {AMC_TXP[3]}]
set_property PACKAGE_PIN U3 [get_ports {AMC_TXN[3]}]
set_property PACKAGE_PIN W4 [get_ports {AMC_RXP[3]}]
#AMC4
set_property LOC GTXE2_CHANNEL_X0Y3 [get_cells i_AMC_if/i_AMC_wrapper/i_AMC_GTX5Gpd_init/amc_gtx5Gpd_i/gt3_amc_gtx5Gpd_i/gtxe2_i]
set_property PACKAGE_PIN V5 [get_ports {AMC_RXN[4]}]
set_property PACKAGE_PIN T2 [get_ports {AMC_TXP[4]}]
set_property PACKAGE_PIN T1 [get_ports {AMC_TXN[4]}]
set_property PACKAGE_PIN V6 [get_ports {AMC_RXP[4]}]
#AMC5
set_property LOC GTXE2_CHANNEL_X0Y5 [get_cells i_AMC_if/i_AMC_wrapper/i_AMC_GTX5Gpd_init/amc_gtx5Gpd_i/gt4_amc_gtx5Gpd_i/gtxe2_i]
set_property PACKAGE_PIN R3 [get_ports {AMC_RXN[5]}]
set_property PACKAGE_PIN N4 [get_ports {AMC_TXP[5]}]
set_property PACKAGE_PIN N3 [get_ports {AMC_TXN[5]}]
set_property PACKAGE_PIN R4 [get_ports {AMC_RXP[5]}]
#AMC6
set_property LOC GTXE2_CHANNEL_X0Y4 [get_cells i_AMC_if/i_AMC_wrapper/i_AMC_GTX5Gpd_init/amc_gtx5Gpd_i/gt5_amc_gtx5Gpd_i/gtxe2_i]
set_property PACKAGE_PIN T5 [get_ports {AMC_RXN[6]}]
set_property PACKAGE_PIN P2 [get_ports {AMC_TXP[6]}]
set_property PACKAGE_PIN P1 [get_ports {AMC_TXN[6]}]
set_property PACKAGE_PIN T6 [get_ports {AMC_RXP[6]}]
#AMC7
set_property LOC GTXE2_CHANNEL_X0Y7 [get_cells i_AMC_if/i_AMC_wrapper/i_AMC_GTX5Gpd_init/amc_gtx5Gpd_i/gt6_amc_gtx5Gpd_i/gtxe2_i]
set_property PACKAGE_PIN M5 [get_ports {AMC_RXN[7]}]
set_property PACKAGE_PIN L4 [get_ports {AMC_TXP[7]}]
set_property PACKAGE_PIN L3 [get_ports {AMC_TXN[7]}]
set_property PACKAGE_PIN M6 [get_ports {AMC_RXP[7]}]
#AMC8
set_property LOC GTXE2_CHANNEL_X0Y6 [get_cells i_AMC_if/i_AMC_wrapper/i_AMC_GTX5Gpd_init/amc_gtx5Gpd_i/gt7_amc_gtx5Gpd_i/gtxe2_i]
set_property PACKAGE_PIN P5 [get_ports {AMC_RXN[8]}]
set_property PACKAGE_PIN M2 [get_ports {AMC_TXP[8]}]
set_property PACKAGE_PIN M1 [get_ports {AMC_TXN[8]}]
set_property PACKAGE_PIN P6 [get_ports {AMC_RXP[8]}]
#AMC9
set_property LOC GTXE2_CHANNEL_X0Y8 [get_cells i_AMC_if/i_AMC_wrapper/i_AMC_GTX5Gpd_init/amc_gtx5Gpd_i/gt8_amc_gtx5Gpd_i/gtxe2_i]
set_property PACKAGE_PIN K5 [get_ports {AMC_RXN[9]}]
set_property PACKAGE_PIN K2 [get_ports {AMC_TXP[9]}]
set_property PACKAGE_PIN K1 [get_ports {AMC_TXN[9]}]
set_property PACKAGE_PIN K6 [get_ports {AMC_RXP[9]}]
#AMC10
set_property LOC GTXE2_CHANNEL_X0Y9 [get_cells i_AMC_if/i_AMC_wrapper/i_AMC_GTX5Gpd_init/amc_gtx5Gpd_i/gt9_amc_gtx5Gpd_i/gtxe2_i]
set_property PACKAGE_PIN H5 [get_ports {AMC_RXN[10]}]
set_property PACKAGE_PIN J4 [get_ports {AMC_TXP[10]}]
set_property PACKAGE_PIN J3 [get_ports {AMC_TXN[10]}]
set_property PACKAGE_PIN H6 [get_ports {AMC_RXP[10]}]
#AMC11
set_property LOC GTXE2_CHANNEL_X0Y10 [get_cells i_AMC_if/i_AMC_wrapper/i_AMC_GTX5Gpd_init/amc_gtx5Gpd_i/gt10_amc_gtx5Gpd_i/gtxe2_i]
set_property PACKAGE_PIN G3 [get_ports {AMC_RXN[11]}]
set_property PACKAGE_PIN H2 [get_ports {AMC_TXP[11]}]
set_property PACKAGE_PIN H1 [get_ports {AMC_TXN[11]}]
set_property PACKAGE_PIN G4 [get_ports {AMC_RXP[11]}]
#AMC12
set_property LOC GTXE2_CHANNEL_X0Y11 [get_cells i_AMC_if/i_AMC_wrapper/i_AMC_GTX5Gpd_init/amc_gtx5Gpd_i/gt11_amc_gtx5Gpd_i/gtxe2_i]
set_property PACKAGE_PIN F5 [get_ports {AMC_RXN[12]}]
set_property PACKAGE_PIN F2 [get_ports {AMC_TXP[12]}]
set_property PACKAGE_PIN F1 [get_ports {AMC_TXN[12]}]
set_property PACKAGE_PIN F6 [get_ports {AMC_RXP[12]}]
set_property PACKAGE_PIN AF22 [get_ports S2V_p]
#set_property IOSTANDARD LVCMOS25 [get_ports S2V_p]
#set_property PACKAGE_PIN AK23 [get_ports V2S_p]
#set_property IOSTANDARD LVCMOS25 [get_ports V2S_p]
set_property PACKAGE_PIN AG28 [get_ports {SFP_ABS[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {SFP_ABS[2]}]
set_property PACKAGE_PIN R30 [get_ports {SFP_ABS[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {SFP_ABS[1]}]
set_property PACKAGE_PIN A22 [get_ports {SFP_ABS[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {SFP_ABS[0]}]
set_property PACKAGE_PIN AC29 [get_ports {SFP_ABS[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {SFP_ABS[3]}]
set_property PACKAGE_PIN AG27 [get_ports {SFP_LOS[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {SFP_LOS[2]}]
set_property PACKAGE_PIN P29 [get_ports {SFP_LOS[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {SFP_LOS[1]}]
set_property PACKAGE_PIN A21 [get_ports {SFP_LOS[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {SFP_LOS[0]}]
set_property PACKAGE_PIN AB30 [get_ports {TxFault[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {TxFault[2]}]
set_property PACKAGE_PIN R29 [get_ports {TxFault[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {TxFault[1]}]
set_property PACKAGE_PIN B22 [get_ports {TxFault[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {TxFault[0]}]
set_property PACKAGE_PIN AJ24 [get_ports {TxFault[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {TxFault[3]}]
set_property PACKAGE_PIN G29 [get_ports {TxDisable[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {TxDisable[2]}]
set_property SLEW SLOW [get_ports {TxDisable[2]}]
set_property PACKAGE_PIN C29 [get_ports {TxDisable[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {TxDisable[1]}]
set_property SLEW SLOW [get_ports {TxDisable[1]}]
set_property PACKAGE_PIN C30 [get_ports {TxDisable[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {TxDisable[0]}]
set_property SLEW SLOW [get_ports {TxDisable[0]}]
set_property PACKAGE_PIN H30 [get_ports {TxDisable[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {TxDisable[3]}]
set_property SLEW SLOW [get_ports {TxDisable[3]}]
set_property PACKAGE_PIN G30 [get_ports {SFP_SDA[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SFP_SDA[2]}]
set_property DRIVE 4 [get_ports {SFP_SDA[2]}]
set_property SLEW SLOW [get_ports {SFP_SDA[2]}]
set_property PACKAGE_PIN E30 [get_ports {SFP_SDA[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SFP_SDA[1]}]
set_property DRIVE 4 [get_ports {SFP_SDA[1]}]
set_property SLEW SLOW [get_ports {SFP_SDA[1]}]
set_property PACKAGE_PIN B30 [get_ports {SFP_SDA[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SFP_SDA[0]}]
set_property DRIVE 4 [get_ports {SFP_SDA[0]}]
set_property SLEW SLOW [get_ports {SFP_SDA[0]}]
set_property PACKAGE_PIN N30 [get_ports {SFP_SDA[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SFP_SDA[3]}]
set_property DRIVE 4 [get_ports {SFP_SDA[3]}]
set_property SLEW SLOW [get_ports {SFP_SDA[3]}]
set_property PACKAGE_PIN F30 [get_ports {SFP_SCL[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SFP_SCL[2]}]
set_property DRIVE 4 [get_ports {SFP_SCL[2]}]
set_property SLEW SLOW [get_ports {SFP_SCL[2]}]
set_property PACKAGE_PIN E29 [get_ports {SFP_SCL[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SFP_SCL[1]}]
set_property DRIVE 4 [get_ports {SFP_SCL[1]}]
set_property SLEW SLOW [get_ports {SFP_SCL[1]}]
set_property PACKAGE_PIN A30 [get_ports {SFP_SCL[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SFP_SCL[0]}]
set_property DRIVE 4 [get_ports {SFP_SCL[0]}]
set_property SLEW SLOW [get_ports {SFP_SCL[0]}]
set_property PACKAGE_PIN N29 [get_ports {SFP_SCL[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SFP_SCL[3]}]
set_property DRIVE 4 [get_ports {SFP_SCL[3]}]
set_property SLEW SLOW [get_ports {SFP_SCL[3]}]
set_property PACKAGE_PIN AC30 [get_ports CLK_SCL]
set_property IOSTANDARD LVCMOS25 [get_ports CLK_SCL]
set_property DRIVE 4 [get_ports CLK_SCL]
set_property SLEW SLOW [get_ports CLK_SCL]
set_property PACKAGE_PIN U30 [get_ports CLK_SDA]
set_property IOSTANDARD LVCMOS25 [get_ports CLK_SDA]
set_property DRIVE 4 [get_ports CLK_SDA]
set_property SLEW SLOW [get_ports CLK_SDA]
#set_property LOC GTXE2_CHANNEL_X0Y15 [get_cells i_ipbus_if/i_S6Linkv_init/S6LINKv_i/U0/gt0_S6LINKv_i/gtxe2_i]
set_property PACKAGE_PIN A7 [get_ports S6LINK_RXN]
set_property PACKAGE_PIN A4 [get_ports S6LINK_TXP]
set_property PACKAGE_PIN A3 [get_ports S6LINK_TXN]
set_property PACKAGE_PIN A8 [get_ports S6LINK_RXP]
#set_property LOC GTXE2_CHANNEL_X0Y13 [get_cells i_TCPIP_if/i_SFP3_init/SFP3_i/U0/gt0_SFP3_i/gtxe2_i]
set_property PACKAGE_PIN D5 [get_ports SFP2_RXN]
set_property PACKAGE_PIN C4 [get_ports SFP2_TXP]
set_property PACKAGE_PIN C3 [get_ports SFP2_TXN]
set_property PACKAGE_PIN D6 [get_ports SFP2_RXP]
#set_property LOC GTXE2_CHANNEL_X0Y14 [get_cells i_TCPIP_if/i_SFP3_init/SFP3_i/U0/gt1_SFP3_i/gtxe2_i]
set_property PACKAGE_PIN B5 [get_ports SFP1_RXN]
set_property PACKAGE_PIN B6 [get_ports SFP1_RXP]
set_property PACKAGE_PIN B1 [get_ports SFP1_TXN]
set_property PACKAGE_PIN B2 [get_ports SFP1_TXP]
#set_property LOC GTXE2_CHANNEL_X0Y12 [get_cells i_TCPIP_if/i_SFP3_init/SFP3_i/U0/gt2_SFP3_i/gtxe2_i]
set_property PACKAGE_PIN E3 [get_ports SFP0_RXN]
set_property PACKAGE_PIN E4 [get_ports SFP0_RXP]
set_property PACKAGE_PIN D1 [get_ports SFP0_TXN]
set_property PACKAGE_PIN D2 [get_ports SFP0_TXP]
set_property LOC OUT_FIFO_X1Y7 [get_cells i_ddr_if/i_ddr3/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo]
#set_output_delay -clock CDRclk_p -max 1.000 [get_ports DIV_nRST]
#set_output_delay -clock CDRclk_p -max 2.000 [get_ports TTCdata_p]
#set_output_delay -clock CDRclk_p -min -2.000 [get_ports TTCdata_p]
#set_property LOC ILOGIC_X0Y68 [get_cells {i_ttc_if/CDRdata_q_reg[0]}]
set_input_delay -clock CDRclk_p -max -1.2 [get_ports CDRdata_p]
set_input_delay -clock CDRclk_p -min -4.3 [get_ports CDRdata_p]
set_property PACKAGE_PIN AE30 [get_ports CDRdata_p]
set_property PACKAGE_PIN AF30 [get_ports CDRdata_n]
set_property LOC SLICE_X0Y52 [get_cells i_ttc_if/TTCdata_reg]
set_property PACKAGE_PIN AJ26 [get_ports TTCdata_p]
set_property PACKAGE_PIN AK26 [get_ports TTCdata_n]
set_max_delay -from [get_pins i_ttc_if/TTCdata_reg/C] 5.5 -to [get_ports TTCdata_p]
#set_property LOC OLOGIC_X0Y59 [get_cells i_ttc_if/DIV_nRST_reg]
set_max_delay -from [get_pins i_ddr_if/i_ddr_wportB/ipb_wddr_reg/C] -to [get_pins i_ddr_if/i_ddr_wportB/ipb_wddrSyncRegs_reg[0]/D] 2 -datapath_only
set_max_delay -from [get_pins i_ddr_if/i_ddr_wportB/ipb_weToggle_reg/C] -to [get_pins i_ddr_if/i_ddr_wportB/ipb_weToggleSyncRegs_reg[0]/D] 2 -datapath_only
#set_max_delay -from [get_pins i_ttc_if/DIV_nRST_reg/C] 5.0 -to [get_ports DIV_nRST]
#set_output_delay -clock CDRclk_p -max 1.000 [get_ports DIV_nRST]
#set_property LOC OLOGIC_X0Y59 [get_cells i_ttc_if/DIV_nRST_reg]
set_property PACKAGE_PIN AK28 [get_ports DIV_nRST]
set_property LOC PLLE2_ADV_X0Y1 [get_cells i_ttc_if/i_MMCM_CDRclk]
set_property LOC BUFGCTRL_X0Y1 [get_cells i_ttc_if/i_CDRclk_buf]
#set CDR_str_group get_cells -hierarchical {DIV_nRST_reg div_rst_cnt_reg[*] Bcnt_l_reg[*] busy_l_reg SendBC0_reg SendEvnRst_reg TTC_cmd_avl_reg TTC_cmd_reg[*]}
#set_multicycle_path 3 -from CDR_str_group -to CDR_str_group
#set_multicycle_path -from [get_pins i_counter_?/ramb_bl.ramb??_dp_bl.ram??_bl/CLKARDCLK] -to [get_pins {i_counter_?/ramb_bl.ramb??_dp_bl.ram??_bl/DIADI[*]}] 2
#set_multicycle_path -from [get_pins i_AMC_if/i_counter_?/ramb_bl.ramb??_dp_bl.ram??_bl/CLKARDCLK] -to [get_pins {i_AMC_if/i_counter_?/ramb_bl.ramb??_dp_bl.ram??_bl/DIADI[*]}] 2

#set_multicycle_path -setup -from [get_pins i_counter_?/ramb_bl.ramb??_dp_bl.ram??_bl/CLKARDCLK] -to [get_pins {i_counter_?/ramb_bl.ramb??_dp_bl.ram??_bl/DIADI[*]}] 2
#set_multicycle_path -hold -from [get_pins i_counter_?/ramb_bl.ramb??_dp_bl.ram??_bl/CLKARDCLK] -to [get_pins {i_counter_?/ramb_bl.ramb??_dp_bl.ram??_bl/DIADI[*]}] 1
#set_multicycle_path -setup -from [get_pins i_AMC_if/i_counter_?/ramb_bl.ramb??_dp_bl.ram??_bl/CLKARDCLK] -to [get_pins {i_AMC_if/i_counter_?/ramb_bl.ramb??_dp_bl.ram??_bl/DIADI[*]}] 2
#set_multicycle_path -hold -from [get_pins i_AMC_if/i_counter_?/ramb_bl.ramb??_dp_bl.ram??_bl/CLKARDCLK] -to [get_pins {i_AMC_if/i_counter_?/ramb_bl.ramb??_dp_bl.ram??_bl/DIADI[*]}] 1
#set_multicycle_path -setup -from [get_pins i_AMC_if/i_counter_L/ramb_bl.ramb??_dp_bl.ram??_bl/CLKARDCLK] -to [get_pins {i_AMC_if/i_counter_H/ramb_bl.ramb??_dp_bl.ram??_bl/WEA[*]}] 2
#set_multicycle_path -hold -from [get_pins i_AMC_if/i_counter_L/ramb_bl.ramb??_dp_bl.ram??_bl/CLKARDCLK] -to [get_pins {i_AMC_if/i_counter_H/ramb_bl.ramb??_dp_bl.ram??_bl/WEA[*]}] 1
set_property LOC DNA_PORT_X0Y0 [get_cells i_DNA_PORT]
set_max_delay -from [get_pins i_TTC_cntr/cntr_reg[*]/C] 5
set_max_delay -from [get_pins i_AMC_if/i_AMC_cntr/data_reg[*]/C] 5
set_max_delay -from [get_pins i_AMC_if/i_AMC_cntr/div_l2_reg[*]/C] 5
set_max_delay -from [get_pins i_AMC_if/i_AMC_cntr/DataType_l2_reg[*]/C] 5