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Command: %s
53*	vivadotcl27
#write_bitstream -force AMC13_T1.bit2default:defaultZ4-113h px 
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@Attempting to get a license for feature '%s' and/or device '%s'
308*common2"
Implementation2default:default2
xc7k325t2default:defaultZ17-347h px 
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0Got license for feature '%s' and/or device '%s'
310*common2"
Implementation2default:default2
xc7k325t2default:defaultZ17-349h px 
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The version limit for your license is '%s' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
719*common2
2021.012default:defaultZ17-1540h px 
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,Running DRC as a precondition to command %s
1349*	planAhead2#
write_bitstream2default:defaultZ12-1349h px 
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IP Catalog is up to date.1232*coregenZ19-1839h px 
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Running DRC with %s threads
24*drc2
22default:defaultZ23-27h px 
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ÎPhase shift check: The MMCME2_ADV cell %s has a fractional CLKOUT0_DIVIDE_F value (3.430) which is not a multiple of the hardware granularity (0.125) and will be adjusted to the nearest supportable value.%s*DRC2™
 "‚
5i_ddr_if/i_ddr3/u_ddr3_infrastructure/gen_mmcm.mmcm_i	5i_ddr_if/i_ddr3/u_ddr3_infrastructure/gen_mmcm.mmcm_i2default:default2default:default2O
 7DRC|Netlist|Instance|Invalid attribute value|MMCME2_ADV2default:default8ZAVAL-139h px 
Ë
‚Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.%s*DRC2(
 DRC|Pin Planning2default:default8ZCFGBVS-1h px 
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YReport rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.%s*DRC29
 !DRC|DRC System|Rule limit reached2default:default8ZCHECK-3h px 
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fInput pipelining: DSP %s input %s is not pipelined. Pipelining DSP48 input will improve performance.%s*DRC2p
 "Z
!i_ttc_if/i_Threshold/DSP48E1_inst	!i_ttc_if/i_Threshold/DSP48E1_inst2default:default2default:default2z
 "d
)i_ttc_if/i_Threshold/DSP48E1_inst/A[29:0]#i_ttc_if/i_Threshold/DSP48E1_inst/A2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E12default:default8ZDPIP-1h px 
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¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2¿
 "¨
Hi_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R	Hi_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R2default:default2default:default2É
 "²
Pi_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R/P[47:0]Ji_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E12default:default8ZDPOP-1h px 
ž
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2Å
 "®
Ki_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__0	Ki_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__02default:default2default:default2Ï
 "¸
Si_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__0/P[47:0]Mi_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__0/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E12default:default8ZDPOP-1h px 
ž
¨PREG Output pipelining: DSP %s output %s is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.%s*DRC2Å
 "®
Ki_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__1	Ki_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__12default:default2default:default2Ï
 "¸
Si_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__1/P[47:0]Mi_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__1/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E12default:default8ZDPOP-1h px 
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—MREG Output pipelining: DSP %s multiplier stage %s is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.%s*DRC2¿
 "¨
Hi_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R	Hi_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R2default:default2default:default2É
 "²
Pi_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R/P[47:0]Ji_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E12default:default8ZDPOP-2h px 
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—MREG Output pipelining: DSP %s multiplier stage %s is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.%s*DRC2Å
 "®
Ki_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__0	Ki_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__02default:default2default:default2Ï
 "¸
Si_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__0/P[47:0]Mi_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__0/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E12default:default8ZDPOP-2h px 
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—MREG Output pipelining: DSP %s multiplier stage %s is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.%s*DRC2Å
 "®
Ki_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__1	Ki_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__12default:default2default:default2Ï
 "¸
Si_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__1/P[47:0]Mi_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__1/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E12default:default8ZDPOP-2h px 
á
—MREG Output pipelining: DSP %s multiplier stage %s is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.%s*DRC2p
 "Z
!i_ttc_if/i_Threshold/DSP48E1_inst	!i_ttc_if/i_Threshold/DSP48E1_inst2default:default2default:default2z
 "d
)i_ttc_if/i_Threshold/DSP48E1_inst/P[47:0]#i_ttc_if/i_Threshold/DSP48E1_inst/P2default:default2default:default2=
 %DRC|Netlist|Instance|Pipeline|DSP48E12default:default8ZDPOP-2h px 
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ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
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Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2ƒ
 "ì
jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[10]jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[10]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[9]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[9]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[9]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[9]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
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ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
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Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2ƒ
 "ì
jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[11]jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[11]2default:default2default:default2¹
 "¢
Eg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[10]Eg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[10]2default:default2default:default2­
 "–
?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[10]	?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[10]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
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ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2ƒ
 "ì
jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[12]jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[12]2default:default2default:default2¹
 "¢
Eg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[11]Eg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[11]2default:default2default:default2­
 "–
?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[11]	?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[11]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
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ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
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Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2ƒ
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jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[13]jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[13]2default:default2default:default2¹
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Eg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[12]Eg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[12]2default:default2default:default2­
 "–
?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[12]	?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[12]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
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ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
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Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[1]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[1]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[0]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[0]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[0]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[0]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
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ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
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Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[2]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[2]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[1]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[1]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[1]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[1]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[3]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[3]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[2]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[2]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[2]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[2]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[4]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[4]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[3]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[3]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[3]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[3]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[5]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[5]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[4]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[4]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[4]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[4]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[6]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[6]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[5]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[5]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[5]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[5]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[7]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[7]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[6]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[6]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[6]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[6]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[8]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[8]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[7]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[7]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[7]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[7]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[9]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[9]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[8]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[8]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[8]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[8]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
¯
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2ƒ
 "ì
jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[10]jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[10]2default:default2default:default2½
 "¦
Gg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[9]Gg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[9]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[9]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[9]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
³
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2ƒ
 "ì
jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[11]jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[11]2default:default2default:default2¿
 "¨
Hg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[10]Hg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[10]2default:default2default:default2­
 "–
?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[10]	?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[10]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
³
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2ƒ
 "ì
jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[12]jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[12]2default:default2default:default2¿
 "¨
Hg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[11]Hg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[11]2default:default2default:default2­
 "–
?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[11]	?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[11]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
³
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2ƒ
 "ì
jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[13]jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[13]2default:default2default:default2¿
 "¨
Hg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[12]Hg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[12]2default:default2default:default2­
 "–
?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[12]	?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[12]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
­
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[7]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[7]2default:default2default:default2½
 "¦
Gg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[6]Gg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[6]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[6]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[6]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
­
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[8]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[8]2default:default2default:default2½
 "¦
Gg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[7]Gg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[7]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[7]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[7]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
­
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[9]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[9]2default:default2default:default2½
 "¦
Gg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[8]Gg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[8]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[8]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[8]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
âenum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2X
 "B
i_sysmon_if/I_DSP48E1	i_sysmon_if/I_DSP48E12default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E12default:default8ZAVAL-4h px 
¿
âenum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: %s: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.%s*DRC2p
 "Z
!i_ttc_if/i_Threshold/DSP48E1_inst	!i_ttc_if/i_Threshold/DSP48E1_inst2default:default2default:default2L
 4DRC|Netlist|Instance|Invalid attribute value|DSP48E12default:default8ZAVAL-4h px 
˜
Éwritefirst: Synchronous clocking is detected for BRAM (%s) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2é
 "Ò
]g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_EMAC_Rx_if/i_buf/sdp_bl.ramb18_sdp_bl3.ram18sd_bl3	]g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_EMAC_Rx_if/i_buf/sdp_bl.ramb18_sdp_bl3.ram18sd_bl32default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8ZREQP-165h px 
˜
Éwritefirst: Synchronous clocking is detected for BRAM (%s) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2é
 "Ò
]g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_EMAC_Rx_if/i_buf/sdp_bl.ramb18_sdp_bl3.ram18sd_bl3	]g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_EMAC_Rx_if/i_buf/sdp_bl.ramb18_sdp_bl3.ram18sd_bl32default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8ZREQP-165h px 
˜
Éwritefirst: Synchronous clocking is detected for BRAM (%s) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2é
 "Ò
]g_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_EMAC_Rx_if/i_buf/sdp_bl.ramb18_sdp_bl3.ram18sd_bl3	]g_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_EMAC_Rx_if/i_buf/sdp_bl.ramb18_sdp_bl3.ram18sd_bl32default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8ZREQP-165h px 
Æ
Éwritefirst: Synchronous clocking is detected for BRAM (%s) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2—
 "€
4i_AMC_if/i_L1A_buf/sdp_bl.ramb18_sdp_bl3.ram18sd_bl3	4i_AMC_if/i_L1A_buf/sdp_bl.ramb18_sdp_bl3.ram18sd_bl32default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8ZREQP-165h px 
Á
Éwritefirst: Synchronous clocking is detected for BRAM (%s) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2’
 "|
2i_AMC_if/i_CDF/sdp_bl.ramb36_sdp_bl_2.ram36sd_bl_2	2i_AMC_if/i_CDF/sdp_bl.ramb36_sdp_bl_2.ram36sd_bl_22default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8ZREQP-181h px 
Á
Éwritefirst: Synchronous clocking is detected for BRAM (%s) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.%s*DRC2’
 "|
2i_AMC_if/i_evn/sdp_bl.ramb36_sdp_bl_2.ram36sd_bl_2	2i_AMC_if/i_evn/sdp_bl.ramb36_sdp_bl_2.ram36sd_bl_22default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB36E12default:default8ZREQP-181h px 
u
DRC finished with %s
1905*	planAhead27
#0 Errors, 31 Warnings, 8 Advisories2default:defaultZ12-3199h px 
i
BPlease refer to the DRC report (report_drc) for more information.
1906*	planAheadZ12-3200h px 
i
)Running write_bitstream with %s threads.
1750*designutils2
22default:defaultZ20-2272h px 
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Loading data files...
1271*designutilsZ12-1165h px 
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Loading site data...
1273*designutilsZ12-1167h px 
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Loading route data...
1272*designutilsZ12-1166h px 
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Processing options...
1362*designutilsZ12-1514h px 
<
Creating bitmap...
1249*designutilsZ12-1141h px 
7
Creating bitstream...
7*	bitstreamZ40-7h px 
_
Writing bitstream %s...
11*	bitstream2"
./AMC13_T1.bit2default:defaultZ40-11h px 
F
Bitgen Completed Successfully.
1606*	planAheadZ12-1842h px 
s
QWebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
118*projectZ1-118h px 

†'%s' has been successfully sent to Xilinx on %s. For additional details about this file, please refer to the Webtalk help file at %s.
186*common2k
WD:/amc13-firmware/proj/AMC13_T1_g2/AMC13_T1_g2.runs/impl_1/usage_statistics_webtalk.xml2default:default2,
Fri Mar 12 16:01:52 20212default:default2I
5D:/Xilinx/Vivado/2020.2/doc/webtalk_introduction.html2default:defaultZ17-186h px 
Z
Releasing license: %s
83*common2"
Implementation2default:defaultZ17-83h px 
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G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28*	vivadotcl2
192default:default2
312default:default2
02default:default2
02default:defaultZ4-41h px 
a
%s completed successfully
29*	vivadotcl2#
write_bitstream2default:defaultZ4-42h px 
‰
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2%
write_bitstream: 2default:default2
00:01:532default:default2
00:01:132default:default2
4346.1252default:default2
712.7232default:defaultZ17-268h px 


End Record