*** Running vivado with args -log AMC13_T1.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source AMC13_T1.tcl -notrace ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source AMC13_T1.tcl -notrace Command: link_design -top AMC13_T1 -part xc7k325tffg900-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7k325tffg900-2 Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1029.055 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 8275 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [D:/amc13-firmware/src/common/DDR/ddr3_1_9a.xdc] INFO: [Timing 38-35] Done setting XDC timing constraints. [D:/amc13-firmware/src/common/DDR/ddr3_1_9a.xdc:27] INFO: [Vivado 12-2286] Implicit search of objects for pattern 'sys_clk_p' matched to 'port' objects. [D:/amc13-firmware/src/common/DDR/ddr3_1_9a.xdc:27] Resolution: To avoid ambiguous patterns, provide proper objects using get commands e.g. [get_nets xyz]. set_propagated_clock: Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1957.195 ; gain = 679.461 Finished Parsing XDC File [D:/amc13-firmware/src/common/DDR/ddr3_1_9a.xdc] Parsing XDC File [D:/amc13-firmware/src/top/AMC13_T1_g2.xdc] INFO: [Timing 38-2] Deriving generated clocks [D:/amc13-firmware/src/top/AMC13_T1_g2.xdc:38] Finished Parsing XDC File [D:/amc13-firmware/src/top/AMC13_T1_g2.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1989.934 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1163 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 4 instances IOBUFDS_DCIEN => IOBUFDS_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 4 instances IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 32 instances OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 32 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 394 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 239 instances RAM64M => RAM64M (RAMD64E(x4)): 1 instance RAM64X1D => RAM64X1D (RAMD64E(x2)): 441 instances RAM64X1D_1 => RAM64X1D (inverted pins: WCLK) (RAMD64E(x2)): 14 instances ROM256X1 => ROM256X1 (LUT6(x4), MUXF7(x2), MUXF8): 1 instance 10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:01 ; elapsed = 00:00:58 . Memory (MB): peak = 1989.934 ; gain = 960.879 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-1540] The version limit for your license is '2021.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 2 threads WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port CLK_SDA expects both input and output buffering but the buffers are incomplete. INFO: [Project 1-461] DRC finished with 0 Errors, 1 Warnings INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 1989.934 ; gain = 0.000 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1e54f42f1 Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2003.645 ; gain = 13.711 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 15 inverter(s) to 16 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 29a2df5ec Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2218.039 ; gain = 0.410 INFO: [Opt 31-389] Phase Retarget created 37 cells and removed 125 cells INFO: [Opt 31-1021] In phase Retarget, 38 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 28deb637c Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2218.039 ; gain = 0.410 INFO: [Opt 31-389] Phase Constant propagation created 50 cells and removed 85 cells Phase 3 Sweep Phase 3 Sweep | Checksum: 16deb0c3c Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 2218.039 ; gain = 0.410 INFO: [Opt 31-389] Phase Sweep created 4 cells and removed 200 cells Phase 4 BUFG optimization Phase 4 BUFG optimization | Checksum: 16deb0c3c Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 2218.039 ; gain = 0.410 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: 16f102526 Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 2218.039 ; gain = 0.410 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 1f8f25716 Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2218.039 ; gain = 0.410 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 37 | 125 | 38 | | Constant propagation | 50 | 85 | 0 | | Sweep | 4 | 200 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.295 . Memory (MB): peak = 2218.039 ; gain = 0.000 Ending Logic Optimization Task | Checksum: 1267f72db Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 2218.039 ; gain = 0.410 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for i_DNA_PORT INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 70 BRAM(s) out of a total of 125 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 2 WE to EN ports Number of BRAM Ports augmented: 73 newly gated: 14 Total Ports: 250 Ending PowerOpt Patch Enables Task | Checksum: c5088347 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.925 . Memory (MB): peak = 3191.246 ; gain = 0.000 Ending Power Optimization Task | Checksum: c5088347 Time (s): cpu = 00:00:51 ; elapsed = 00:00:28 . Memory (MB): peak = 3191.246 ; gain = 973.207 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 10dc25550 Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 3191.246 ; gain = 0.000 Ending Final Cleanup Task | Checksum: 10dc25550 Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 3191.246 ; gain = 0.000 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.049 . Memory (MB): peak = 3191.246 ; gain = 0.000 Ending Netlist Obfuscation Task | Checksum: 10dc25550 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.049 . Memory (MB): peak = 3191.246 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 36 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:01:46 ; elapsed = 00:01:11 . Memory (MB): peak = 3191.246 ; gain = 1201.313 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.125 . Memory (MB): peak = 3191.246 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/amc13-firmware/proj/AMC13_T1_g2/AMC13_T1_g2.runs/impl_1/AMC13_T1_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:30 ; elapsed = 00:00:22 . Memory (MB): peak = 3191.246 ; gain = 0.000 INFO: [runtcl-4] Executing : report_drc -file AMC13_T1_drc_opted.rpt -pb AMC13_T1_drc_opted.pb -rpx AMC13_T1_drc_opted.rpx Command: report_drc -file AMC13_T1_drc_opted.rpt -pb AMC13_T1_drc_opted.pb -rpx AMC13_T1_drc_opted.rpx INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2020.2/data/ip'. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file D:/amc13-firmware/proj/AMC13_T1_g2/AMC13_T1_g2.runs/impl_1/AMC13_T1_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:33 ; elapsed = 00:00:18 . Memory (MB): peak = 3191.246 ; gain = 0.000 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-1540] The version limit for your license is '2021.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 2 threads WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[10] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[9]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[11] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[10]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[12] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[11]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[13] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[12]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[1] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[0]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[2] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[1]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[3] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[2]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[4] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[3]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[5] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[4]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[6] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[5]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[7] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[6]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[8] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[7]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[9] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[8]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[10] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[9]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[11] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[10]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[12] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[11]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[13] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[12]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[7] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[6]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[8] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[7]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[9] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[8]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port CLK_SDA expects both input and output buffering but the buffers are incomplete. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 22 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c4d5ea71 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.077 . Memory (MB): peak = 3191.246 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.050 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-87] Partially locked IO Bus is found. Following components of the IO Bus VAUXN are not locked: 'VAUXN[7]' 'VAUXN[6]' 'VAUXN[1]' WARNING: [Place 30-87] Partially locked IO Bus is found. Following components of the IO Bus VAUXP are not locked: 'VAUXP[7]' 'VAUXP[6]' 'VAUXP[1]' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: c774584e Time (s): cpu = 00:00:21 ; elapsed = 00:00:14 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1be1170b4 Time (s): cpu = 00:00:59 ; elapsed = 00:00:41 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1be1170b4 Time (s): cpu = 00:01:00 ; elapsed = 00:00:42 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 1 Placer Initialization | Checksum: 1be1170b4 Time (s): cpu = 00:01:00 ; elapsed = 00:00:42 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 16950bff3 Time (s): cpu = 00:01:12 ; elapsed = 00:00:49 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1a08b4bf2 Time (s): cpu = 00:01:21 ; elapsed = 00:00:55 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 15 LUTNM shape to break, 4036 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 12, two critical 3, total 15, new lutff created 1 INFO: [Physopt 32-775] End 1 Pass. Optimized 1684 nets or cells. Created 15 new cells, deleted 1669 existing cells and moved 0 existing cell INFO: [Physopt 32-76] Pass 1. Identified 1 candidate net for fanout optimization. INFO: [Physopt 32-81] Processed net i_AMC_if/CntrRst. Replicated 22 times. INFO: [Physopt 32-232] Optimized 1 net. Created 22 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 22 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.274 . Memory (MB): peak = 3191.246 ; gain = 0.000 INFO: [Physopt 32-76] Pass 1. Identified 1 candidate net for fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.142 . Memory (MB): peak = 3191.246 ; gain = 0.000 INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_175 could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__129 could not be replicated INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/WREN could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_2__6 could not be replicated INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_186 could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__137 could not be replicated INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_154 could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__113 could not be replicated INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_196 could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__145 could not be replicated INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_165 could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__121 could not be replicated INFO: [Physopt 32-117] Net i_AMC_if/g_AMC_Link[3].i_AMC_Link/i_AMC_DATA/g_FIFO[3].i_FIFO_o/RDEN2_out could not be optimized because driver i_AMC_if/g_AMC_Link[3].i_AMC_Link/i_AMC_DATA/g_FIFO[3].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__23 could not be replicated INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/g_we_re[6].fifo_we_reg[1]_185 could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__136 could not be replicated INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/WREN could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_2__7 could not be replicated INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_144 could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__105 could not be replicated INFO: [Physopt 32-117] Net i_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[1].i_FIFO_o/RDEN0_out could not be optimized because driver i_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[1].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__42 could not be replicated INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[5].i_FIFO/g_we_re[5].fifo_we_reg[1]_184 could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[5].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__135 could not be replicated INFO: [Physopt 32-117] Net i_AMC_if/g_AMC_Link[11].i_AMC_Link/i_AMC_DATA/g_FIFO[0].i_FIFO_o/RDEN could not be optimized because driver i_AMC_if/g_AMC_Link[11].i_AMC_Link/i_AMC_DATA/g_FIFO[0].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__76 could not be replicated INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[4].i_FIFO/g_we_re[4].fifo_we_reg[1]_193 could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[4].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__142 could not be replicated INFO: [Physopt 32-117] Net i_AMC_if/g_AMC_Link[7].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/RDEN4_out could not be optimized because driver i_AMC_if/g_AMC_Link[7].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__53 could not be replicated INFO: [Physopt 32-117] Net i_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[2].i_FIFO_o/RDEN1_out could not be optimized because driver i_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[2].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__43 could not be replicated INFO: [Physopt 32-117] Net i_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[6].i_FIFO_o/RDEN5_out could not be optimized because driver i_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[6].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__47 could not be replicated INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/WREN could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_2__4 could not be replicated INFO: [Physopt 32-117] Net i_AMC_if/g_AMC_Link[11].i_AMC_Link/i_AMC_DATA/g_FIFO[4].i_FIFO_o/RDEN3_out could not be optimized because driver i_AMC_if/g_AMC_Link[11].i_AMC_Link/i_AMC_DATA/g_FIFO[4].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__80 could not be replicated INFO: [Physopt 32-117] Net i_AMC_if/g_AMC_Link[1].i_AMC_Link/i_AMC_DATA/g_FIFO[4].i_FIFO_o/RDEN3_out could not be optimized because driver i_AMC_if/g_AMC_Link[1].i_AMC_Link/i_AMC_DATA/g_FIFO[4].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__10 could not be replicated INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/WREN could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_2__2 could not be replicated INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[0].i_FIFO/g_we_re[0].fifo_we_reg[1]_158 could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[0].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__114 could not be replicated INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[0].i_FIFO/g_we_re[0].fifo_we_reg[1]_147 could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[0].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__106 could not be replicated INFO: [Physopt 32-117] Net i_AMC_if/g_AMC_Link[8].i_AMC_Link/i_AMC_DATA/g_FIFO[3].i_FIFO_o/RDEN2_out could not be optimized because driver i_AMC_if/g_AMC_Link[8].i_AMC_Link/i_AMC_DATA/g_FIFO[3].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__58 could not be replicated INFO: [Physopt 32-117] Net i_AMC_if/g_AMC_Link[8].i_AMC_Link/i_AMC_DATA/g_FIFO[2].i_FIFO_o/RDEN1_out could not be optimized because driver i_AMC_if/g_AMC_Link[8].i_AMC_Link/i_AMC_DATA/g_FIFO[2].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__57 could not be replicated INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[2].i_FIFO/g_we_re[2].fifo_we_reg[1]_181 could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[2].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__132 could not be replicated INFO: [Physopt 32-117] Net i_AMC_if/i_evt_bldr0/AMC_DATA_RdEn[10] could not be optimized because driver i_AMC_if/i_evt_bldr0/bl.fifo_36_inst_bl.fifo_36_bl_i_1__93 could not be replicated INFO: [Physopt 32-117] Net g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[2].i_FIFO/g_we_re[2].fifo_we_reg[1]_170 could not be optimized because driver g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[2].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__124 could not be replicated INFO: [Physopt 32-117] Net i_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/RDEN4_out could not be optimized because driver i_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__46 could not be replicated INFO: [Physopt 32-117] Net i_AMC_if/g_AMC_Link[2].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/RDEN4_out could not be optimized because driver i_AMC_if/g_AMC_Link[2].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__18 could not be replicated INFO: [Physopt 32-46] Identified 7 candidate nets for critical-cell optimization. INFO: [Physopt 32-571] Net g_TCPIP_if.i_TCPIP_if/DDR2TCPdata[26] was not replicated. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 12 nets or cells. Created 12 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.313 . Memory (MB): peak = 3191.246 ; gain = 0.000 INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[0].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[0].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[0].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[0].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[0].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[10].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[10].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[10].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[10].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[10].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[11].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[11].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[11].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[11].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[11].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[1].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[1].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[1].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[1].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[1].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[2].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[2].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[2].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[2].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[2].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[3].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[3].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[3].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[3].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[3].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[4].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[4].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[4].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[4].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[4].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[5].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[5].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[5].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[5].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[5].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[6].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[6].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[6].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[6].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[6].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[7].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[8].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[8].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[8].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[8].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[8].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[9].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[9].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[9].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[9].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'i_AMC_if/g_AMC_Link[9].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl' Port 'B' is 0. Skip BRAM Register Optimization on the port INFO: [Physopt 32-527] Pass 1: Identified 5 candidate cells for BRAM register optimization INFO: [Physopt 32-666] Processed cell i_AMC_if/g_AMC_Link[3].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl. No change. INFO: [Physopt 32-666] Processed cell i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl. No change. INFO: [Physopt 32-666] Processed cell i_AMC_if/g_AMC_Link[1].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl. No change. INFO: [Physopt 32-666] Processed cell i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl. No change. INFO: [Physopt 32-666] Processed cell i_AMC_if/g_AMC_Link[11].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl. No change. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.068 . Memory (MB): peak = 3191.246 ; gain = 0.000 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 3191.246 ; gain = 0.000 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 15 | 1669 | 1684 | 0 | 1 | 00:00:03 | | Very High Fanout | 22 | 0 | 1 | 0 | 1 | 00:00:01 | | Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 12 | 0 | 12 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 49 | 1669 | 1697 | 0 | 10 | 00:00:05 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 1d96e5605 Time (s): cpu = 00:03:30 ; elapsed = 00:02:21 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 2.3 Global Placement Core | Checksum: 160dbd4ac Time (s): cpu = 00:03:37 ; elapsed = 00:02:26 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 2 Global Placement | Checksum: 160dbd4ac Time (s): cpu = 00:03:37 ; elapsed = 00:02:26 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 14d2de81b Time (s): cpu = 00:03:48 ; elapsed = 00:02:33 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 15c9a46ad Time (s): cpu = 00:04:10 ; elapsed = 00:02:48 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 151b0598f Time (s): cpu = 00:04:11 ; elapsed = 00:02:49 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 20e174859 Time (s): cpu = 00:04:12 ; elapsed = 00:02:50 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 188e806c7 Time (s): cpu = 00:04:34 ; elapsed = 00:03:03 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 1a6918886 Time (s): cpu = 00:05:19 ; elapsed = 00:03:48 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 1a3581e8a Time (s): cpu = 00:05:25 ; elapsed = 00:03:56 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 14f20bc84 Time (s): cpu = 00:05:27 ; elapsed = 00:03:58 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 192a46bf5 Time (s): cpu = 00:06:05 ; elapsed = 00:04:22 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 3 Detail Placement | Checksum: 192a46bf5 Time (s): cpu = 00:06:05 ; elapsed = 00:04:23 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1d2b98fe0 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.238 | TNS=-26.473 | Phase 1 Physical Synthesis Initialization | Checksum: 152236f4c Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3191.246 ; gain = 0.000 INFO: [Place 46-33] Processed net g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_EMAC_Rx_if/cmd_reg[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 13fddcd1a Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 4.1.1.1 BUFG Insertion | Checksum: 1d2b98fe0 Time (s): cpu = 00:06:54 ; elapsed = 00:04:55 . Memory (MB): peak = 3191.246 ; gain = 0.000 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.045. For the most accurate timing information please run report_timing. Time (s): cpu = 00:08:31 ; elapsed = 00:06:19 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 4.1 Post Commit Optimization | Checksum: 22f4095f4 Time (s): cpu = 00:08:32 ; elapsed = 00:06:20 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 22f4095f4 Time (s): cpu = 00:08:33 ; elapsed = 00:06:20 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 4x4| |___________|___________________|___________________| | South| 2x2| 4x4| |___________|___________________|___________________| | East| 4x4| 4x4| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 22f4095f4 Time (s): cpu = 00:08:34 ; elapsed = 00:06:21 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 4.3 Placer Reporting | Checksum: 22f4095f4 Time (s): cpu = 00:08:35 ; elapsed = 00:06:22 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 3191.246 ; gain = 0.000 Time (s): cpu = 00:08:35 ; elapsed = 00:06:22 . Memory (MB): peak = 3191.246 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 265456f09 Time (s): cpu = 00:08:35 ; elapsed = 00:06:23 . Memory (MB): peak = 3191.246 ; gain = 0.000 Ending Placer Task | Checksum: 17975e261 Time (s): cpu = 00:08:35 ; elapsed = 00:06:23 . Memory (MB): peak = 3191.246 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 182 Infos, 25 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:08:44 ; elapsed = 00:06:28 . Memory (MB): peak = 3191.246 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:22 ; elapsed = 00:00:08 . Memory (MB): peak = 3191.246 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/amc13-firmware/proj/AMC13_T1_g2/AMC13_T1_g2.runs/impl_1/AMC13_T1_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:32 ; elapsed = 00:00:18 . Memory (MB): peak = 3191.246 ; gain = 0.000 INFO: [runtcl-4] Executing : report_io -file AMC13_T1_io_placed.rpt report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.150 . Memory (MB): peak = 3191.246 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file AMC13_T1_utilization_placed.rpt -pb AMC13_T1_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file AMC13_T1_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.496 . Memory (MB): peak = 3191.246 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-1540] The version limit for your license is '2021.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 2 threads WARNING: [DRC PLIO-3] Placement Constraints Check for IO constraints: Partially locked IO Bus is found. Following components of the IO Bus VAUXN[12:0] are not locked: VAUXN[7] VAUXN[6] VAUXN[1] WARNING: [DRC PLIO-3] Placement Constraints Check for IO constraints: Partially locked IO Bus is found. Following components of the IO Bus VAUXP[12:0] are not locked: VAUXP[7] VAUXP[6] VAUXP[1] INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 2 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs Checksum: PlaceDB: 93160556 ConstDB: 0 ShapeSum: e65fdd0b RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 15926b39d Time (s): cpu = 00:00:47 ; elapsed = 00:00:22 . Memory (MB): peak = 3282.934 ; gain = 91.688 Post Restoration Checksum: NetGraph: 6b5cc2fa NumContArr: edc9f0a3 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 15926b39d Time (s): cpu = 00:00:48 ; elapsed = 00:00:23 . Memory (MB): peak = 3282.934 ; gain = 91.688 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 15926b39d Time (s): cpu = 00:00:49 ; elapsed = 00:00:24 . Memory (MB): peak = 3285.590 ; gain = 94.344 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 15926b39d Time (s): cpu = 00:00:50 ; elapsed = 00:00:24 . Memory (MB): peak = 3285.590 ; gain = 94.344 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 192e307f7 Time (s): cpu = 00:01:47 ; elapsed = 00:01:04 . Memory (MB): peak = 3362.457 ; gain = 171.211 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.056 | TNS=-0.185 | WHS=-0.902 | THS=-5875.594| Phase 2 Router Initialization | Checksum: 1a872eaf5 Time (s): cpu = 00:02:15 ; elapsed = 00:01:21 . Memory (MB): peak = 3389.512 ; gain = 198.266 Router Utilization Summary Global Vertical Routing Utilization = 0.00469603 % Global Horizontal Routing Utilization = 0.00310329 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 105087 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 105086 Number of Partially Routed Nets = 1 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 1a872eaf5 Time (s): cpu = 00:02:16 ; elapsed = 00:01:21 . Memory (MB): peak = 3389.512 ; gain = 198.266 Phase 3 Initial Routing | Checksum: 19ca2f0db Time (s): cpu = 00:03:05 ; elapsed = 00:01:47 . Memory (MB): peak = 3389.512 ; gain = 198.266 INFO: [Route 35-580] Design has 280 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | oserdes_clk_1 | oserdes_clkdiv_1 |i_ddr_if/i_ddr3/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.ddr.oserdes_dq_i/RST| | oserdes_clk_3 | oserdes_clkdiv_3 |i_ddr_if/i_ddr3/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.sdr.oserdes_dq_i/RST| | oserdes_clk_4 | oserdes_clkdiv_4 |i_ddr_if/i_ddr3/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/RST| | oserdes_clk_6 | oserdes_clkdiv_6 |i_ddr_if/i_ddr3/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST| | oserdes_clk_1 | oserdes_clkdiv_1 |i_ddr_if/i_ddr3/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/RST| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 10966 Number of Nodes with overlaps = 1105 Number of Nodes with overlaps = 297 Number of Nodes with overlaps = 110 Number of Nodes with overlaps = 30 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.257 | TNS=-1.160 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1a6d62ae7 Time (s): cpu = 00:05:06 ; elapsed = 00:03:24 . Memory (MB): peak = 3395.219 ; gain = 203.973 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 602 Number of Nodes with overlaps = 133 Number of Nodes with overlaps = 30 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.186 | TNS=-0.904 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 1fe52110a Time (s): cpu = 00:05:36 ; elapsed = 00:03:50 . Memory (MB): peak = 3395.246 ; gain = 204.000 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 476 Number of Nodes with overlaps = 65 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.058 | TNS=-0.452 | WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: 154def2ce Time (s): cpu = 00:05:53 ; elapsed = 00:04:05 . Memory (MB): peak = 3395.246 ; gain = 204.000 Phase 4 Rip-up And Reroute | Checksum: 154def2ce Time (s): cpu = 00:05:53 ; elapsed = 00:04:05 . Memory (MB): peak = 3395.246 ; gain = 204.000 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 186635e48 Time (s): cpu = 00:06:03 ; elapsed = 00:04:12 . Memory (MB): peak = 3395.246 ; gain = 204.000 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.056 | TNS=-0.131 | WHS=N/A | THS=N/A | Phase 5.1 Delay CleanUp | Checksum: 186635e48 Time (s): cpu = 00:06:05 ; elapsed = 00:04:13 . Memory (MB): peak = 3395.246 ; gain = 204.000 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 186635e48 Time (s): cpu = 00:06:05 ; elapsed = 00:04:13 . Memory (MB): peak = 3395.246 ; gain = 204.000 Phase 5 Delay and Skew Optimization | Checksum: 186635e48 Time (s): cpu = 00:06:06 ; elapsed = 00:04:13 . Memory (MB): peak = 3395.246 ; gain = 204.000 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: e7f286ee Time (s): cpu = 00:06:17 ; elapsed = 00:04:21 . Memory (MB): peak = 3395.246 ; gain = 204.000 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.056 | TNS=-0.131 | WHS=0.010 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: d752d5bc Time (s): cpu = 00:06:18 ; elapsed = 00:04:22 . Memory (MB): peak = 3395.246 ; gain = 204.000 Phase 6 Post Hold Fix | Checksum: d752d5bc Time (s): cpu = 00:06:18 ; elapsed = 00:04:22 . Memory (MB): peak = 3395.246 ; gain = 204.000 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 12.4602 % Global Horizontal Routing Utilization = 11.9936 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 85.5856%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X62Y102 -> INT_L_X62Y102 South Dir 1x1 Area, Max Cong = 81.982%, No Congested Regions. East Dir 1x1 Area, Max Cong = 98.5294%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X62Y88 -> INT_L_X62Y88 INT_L_X62Y84 -> INT_L_X62Y84 INT_L_X74Y84 -> INT_L_X74Y84 West Dir 1x1 Area, Max Cong = 94.1176%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_R_X57Y92 -> INT_R_X57Y92 INT_R_X59Y91 -> INT_R_X59Y91 INT_L_X58Y89 -> INT_L_X58Y89 INT_L_X60Y88 -> INT_L_X60Y88 ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 1 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5 Phase 7 Route finalize | Checksum: 102d9c546 Time (s): cpu = 00:06:19 ; elapsed = 00:04:23 . Memory (MB): peak = 3395.246 ; gain = 204.000 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 102d9c546 Time (s): cpu = 00:06:20 ; elapsed = 00:04:23 . Memory (MB): peak = 3395.246 ; gain = 204.000 Phase 9 Depositing Routes INFO: [Route 35-467] Router swapped GT pin g_TCPIP_if.i_TCPIP_if/i_SFP3_init/SFP3_v2_7_i/gtxe2_common_0_i/GTREFCLK0 to physical pin GTXE2_COMMON_X0Y3/GTREFCLK1 INFO: [Route 35-467] Router swapped GT pin i_ipbus_if/i_S6Link_init/S6Link_i/gt0_S6Link_i/gtxe2_i/GTREFCLK0 to physical pin GTXE2_CHANNEL_X0Y15/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin i_AMC_if/i_AMC_wrapper/i_common0/gtxe2_common_i/GTREFCLK0 to physical pin GTXE2_COMMON_X0Y0/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin i_AMC_if/i_AMC_wrapper/i_common1/gtxe2_common_i/GTREFCLK0 to physical pin GTXE2_COMMON_X0Y1/GTREFCLK1 INFO: [Route 35-467] Router swapped GT pin i_AMC_if/i_AMC_wrapper/i_common2/gtxe2_common_i/GTREFCLK0 to physical pin GTXE2_COMMON_X0Y2/GTNORTHREFCLK1 Phase 9 Depositing Routes | Checksum: b2c3dda5 Time (s): cpu = 00:06:31 ; elapsed = 00:04:35 . Memory (MB): peak = 3395.246 ; gain = 204.000 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.056 | TNS=-0.131 | WHS=0.010 | THS=0.000 | WARNING: [Route 35-328] Router estimated timing not met. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. Phase 10 Post Router Timing | Checksum: b2c3dda5 Time (s): cpu = 00:06:32 ; elapsed = 00:04:36 . Memory (MB): peak = 3395.246 ; gain = 204.000 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:06:32 ; elapsed = 00:04:36 . Memory (MB): peak = 3395.246 ; gain = 204.000 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 208 Infos, 28 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:07:15 ; elapsed = 00:04:59 . Memory (MB): peak = 3395.246 ; gain = 204.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:28 ; elapsed = 00:00:11 . Memory (MB): peak = 3395.246 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/amc13-firmware/proj/AMC13_T1_g2/AMC13_T1_g2.runs/impl_1/AMC13_T1_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:35 ; elapsed = 00:00:19 . Memory (MB): peak = 3395.246 ; gain = 0.000 INFO: [runtcl-4] Executing : report_drc -file AMC13_T1_drc_routed.rpt -pb AMC13_T1_drc_routed.pb -rpx AMC13_T1_drc_routed.rpx Command: report_drc -file AMC13_T1_drc_routed.rpt -pb AMC13_T1_drc_routed.pb -rpx AMC13_T1_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file D:/amc13-firmware/proj/AMC13_T1_g2/AMC13_T1_g2.runs/impl_1/AMC13_T1_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:01:06 ; elapsed = 00:00:34 . Memory (MB): peak = 3613.816 ; gain = 218.570 INFO: [runtcl-4] Executing : report_methodology -file AMC13_T1_methodology_drc_routed.rpt -pb AMC13_T1_methodology_drc_routed.pb -rpx AMC13_T1_methodology_drc_routed.rpx Command: report_methodology -file AMC13_T1_methodology_drc_routed.rpt -pb AMC13_T1_methodology_drc_routed.pb -rpx AMC13_T1_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 2 threads INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/amc13-firmware/proj/AMC13_T1_g2/AMC13_T1_g2.runs/impl_1/AMC13_T1_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:00:46 ; elapsed = 00:00:28 . Memory (MB): peak = 3613.816 ; gain = 0.000 INFO: [runtcl-4] Executing : report_power -file AMC13_T1_power_routed.rpt -pb AMC13_T1_power_summary_routed.pb -rpx AMC13_T1_power_routed.rpx Command: report_power -file AMC13_T1_power_routed.rpt -pb AMC13_T1_power_summary_routed.pb -rpx AMC13_T1_power_routed.rpx INFO: [Power 33-23] Power model is not available for i_DNA_PORT INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 221 Infos, 29 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:01:07 ; elapsed = 00:00:40 . Memory (MB): peak = 3617.465 ; gain = 3.648 INFO: [runtcl-4] Executing : report_route_status -file AMC13_T1_route_status.rpt -pb AMC13_T1_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file AMC13_T1_timing_summary_routed.rpt -pb AMC13_T1_timing_summary_routed.pb -rpx AMC13_T1_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs report_timing_summary: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 3622.328 ; gain = 4.863 INFO: [runtcl-4] Executing : report_incremental_reuse -file AMC13_T1_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file AMC13_T1_clock_utilization_routed.rpt report_clock_utilization: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 3632.094 ; gain = 9.766 Command: write_bitstream -force AMC13_T1.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-1540] The version limit for your license is '2021.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads WARNING: [DRC AVAL-139] Phase shift check: The MMCME2_ADV cell i_ddr_if/i_ddr3/u_ddr3_infrastructure/gen_mmcm.mmcm_i has a fractional CLKOUT0_DIVIDE_F value (3.430) which is not a multiple of the hardware granularity (0.125) and will be adjusted to the nearest supportable value. WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ttc_if/i_Threshold/DSP48E1_inst input i_ttc_if/i_Threshold/DSP48E1_inst/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP i_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R output i_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP i_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__0 output i_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP i_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__1 output i_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R multiplier stage i_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__0 multiplier stage i_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__1 multiplier stage i_ipbus_if/i_S6Link_init/gt0_eq_lpm_mode.gt0_adapt_top_lpm_i/i_lock/I2/R__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ttc_if/i_Threshold/DSP48E1_inst multiplier stage i_ttc_if/i_Threshold/DSP48E1_inst/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[10] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[9]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[11] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[10]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[12] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[11]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[13] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[12]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[1] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[0]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[2] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[1]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[3] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[2]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[4] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[3]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[5] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[4]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[6] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[5]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[7] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[6]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[8] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[7]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[9] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[8]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[10] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[9]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[11] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[10]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[12] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[11]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[13] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[12]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[7] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[6]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[8] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[7]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl has an input control pin g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[9] (net: g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[8]) which is driven by a register (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_sysmon_if/I_DSP48E1: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: i_ttc_if/i_Threshold/DSP48E1_inst: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_EMAC_Rx_if/i_buf/sdp_bl.ramb18_sdp_bl3.ram18sd_bl3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_EMAC_Rx_if/i_buf/sdp_bl.ramb18_sdp_bl3.ram18sd_bl3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (g_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_EMAC_Rx_if/i_buf/sdp_bl.ramb18_sdp_bl3.ram18sd_bl3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (i_AMC_if/i_L1A_buf/sdp_bl.ramb18_sdp_bl3.ram18sd_bl3) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (i_AMC_if/i_CDF/sdp_bl.ramb36_sdp_bl_2.ram36sd_bl_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (i_AMC_if/i_evn/sdp_bl.ramb36_sdp_bl_2.ram36sd_bl_2) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 31 Warnings, 8 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./AMC13_T1.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). INFO: [Common 17-186] 'D:/amc13-firmware/proj/AMC13_T1_g2/AMC13_T1_g2.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Fri Mar 12 16:01:52 2021. For additional details about this file, please refer to the WebTalk help file at D:/Xilinx/Vivado/2020.2/doc/webtalk_introduction.html. INFO: [Common 17-83] Releasing license: Implementation 19 Infos, 31 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:53 ; elapsed = 00:01:13 . Memory (MB): peak = 4346.125 ; gain = 712.723 INFO: [Common 17-206] Exiting Vivado at Fri Mar 12 16:01:53 2021...