Q Command: %s 53* vivadotcl2 route_design2default:defaultZ4-113hpx  @Attempting to get a license for feature '%s' and/or device '%s' 308*common2" Implementation2default:default2 xc7k325t2default:defaultZ17-347hpx  0Got license for feature '%s' and/or device '%s' 310*common2" Implementation2default:default2 xc7k325t2default:defaultZ17-349hpx  The version limit for your license is '%s' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. 719*common2 2021.012default:defaultZ17-1540hpx p ,Running DRC as a precondition to command %s 22* vivadotcl2 route_design2default:defaultZ4-22hpx P Running DRC with %s threads 24*drc2 22default:defaultZ23-27hpx  Placement Constraints Check for IO constraints: Partially locked IO Bus is found. Following components of the IO Bus %s are not locked: %s %s %s%s*DRC2> "( VAUXN[12:0]VAUXN2default:default2default:default2> "( VAUXN[7]VAUXN[7]2default:default2default:default2> "( VAUXN[6]VAUXN[6]2default:default2default:default2> "( VAUXN[1]VAUXN[1]2default:default2default:default28  DRC|Implementation|Placement|IOs2default:default8ZPLIO-3hpx  Placement Constraints Check for IO constraints: Partially locked IO Bus is found. Following components of the IO Bus %s are not locked: %s %s %s%s*DRC2> "( VAUXP[12:0]VAUXP2default:default2default:default2> "( VAUXP[7]VAUXP[7]2default:default2default:default2> "( VAUXP[6]VAUXP[6]2default:default2default:default2> "( VAUXP[1]VAUXP[1]2default:default2default:default28  DRC|Implementation|Placement|IOs2default:default8ZPLIO-3hpx b DRC finished with %s 79* vivadotcl2( 0 Errors, 2 Warnings2default:defaultZ4-198hpx e BPlease refer to the DRC report (report_drc) for more information. 80* vivadotclZ4-199hpx V  Starting %s Task 103* constraints2 Routing2default:defaultZ18-103hpx } BMultithreading enabled for route_design using a maximum of %s CPUs17* routeflow2 22default:defaultZ35-254hpx p Phase %s%s 101* constraints2 1 2default:default2# Build RT Design2default:defaultZ18-101hpx C .Phase 1 Build RT Design | Checksum: 15926b39d *commonhpx   %s * constraints2p \Time (s): cpu = 00:00:47 ; elapsed = 00:00:22 . Memory (MB): peak = 3282.934 ; gain = 91.6882default:defaulthpx v Phase %s%s 101* constraints2 2 2default:default2) Router Initialization2default:defaultZ18-101hpx o Phase %s%s 101* constraints2 2.1 2default:default2 Create Timer2default:defaultZ18-101hpx B -Phase 2.1 Create Timer | Checksum: 15926b39d *commonhpx   %s * constraints2p \Time (s): cpu = 00:00:48 ; elapsed = 00:00:23 . Memory (MB): peak = 3282.934 ; gain = 91.6882default:defaulthpx { Phase %s%s 101* constraints2 2.2 2default:default2, Fix Topology Constraints2default:defaultZ18-101hpx N 9Phase 2.2 Fix Topology Constraints | Checksum: 15926b39d *commonhpx   %s * constraints2p \Time (s): cpu = 00:00:49 ; elapsed = 00:00:24 . Memory (MB): peak = 3285.590 ; gain = 94.3442default:defaulthpx t Phase %s%s 101* constraints2 2.3 2default:default2% Pre Route Cleanup2default:defaultZ18-101hpx G 2Phase 2.3 Pre Route Cleanup | Checksum: 15926b39d *commonhpx   %s * constraints2p \Time (s): cpu = 00:00:50 ; elapsed = 00:00:24 . Memory (MB): peak = 3285.590 ; gain = 94.3442default:defaulthpx p Phase %s%s 101* constraints2 2.4 2default:default2! Update Timing2default:defaultZ18-101hpx C .Phase 2.4 Update Timing | Checksum: 192e307f7 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:01:47 ; elapsed = 00:01:04 . Memory (MB): peak = 3362.457 ; gain = 171.2112default:defaulthpx  Intermediate Timing Summary %s164*route2L 8| WNS=-0.056 | TNS=-0.185 | WHS=-0.902 | THS=-5875.594| 2default:defaultZ35-416hpx I 4Phase 2 Router Initialization | Checksum: 1a872eaf5 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:02:15 ; elapsed = 00:01:21 . Memory (MB): peak = 3389.512 ; gain = 198.2662default:defaulthpx p Phase %s%s 101* constraints2 3 2default:default2# Initial Routing2default:defaultZ18-101hpx q Phase %s%s 101* constraints2 3.1 2default:default2" Global Routing2default:defaultZ18-101hpx D /Phase 3.1 Global Routing | Checksum: 1a872eaf5 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:02:16 ; elapsed = 00:01:21 . Memory (MB): peak = 3389.512 ; gain = 198.2662default:defaulthpx C .Phase 3 Initial Routing | Checksum: 19ca2f0db *commonhpx   %s * constraints2q ]Time (s): cpu = 00:03:05 ; elapsed = 00:01:47 . Memory (MB): peak = 3389.512 ; gain = 198.2662default:defaulthpx  >Design has %s pins with tight setup and hold constraints. %s 244*route2 2802default:default2 The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | oserdes_clk_1 | oserdes_clkdiv_1 |i_ddr_if/i_ddr3/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.ddr.oserdes_dq_i/RST| | oserdes_clk_3 | oserdes_clkdiv_3 |i_ddr_if/i_ddr3/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.sdr.oserdes_dq_i/RST| | oserdes_clk_4 | oserdes_clkdiv_4 |i_ddr_if/i_ddr3/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/RST| | oserdes_clk_6 | oserdes_clkdiv_6 |i_ddr_if/i_ddr3/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST| | oserdes_clk_1 | oserdes_clkdiv_1 |i_ddr_if/i_ddr3/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/RST| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt 2default:defaultZ35-580hpx s Phase %s%s 101* constraints2 4 2default:default2& Rip-up And Reroute2default:defaultZ18-101hpx u Phase %s%s 101* constraints2 4.1 2default:default2& Global Iteration 02default:defaultZ18-101hpx  Intermediate Timing Summary %s164*route2J 6| WNS=-0.257 | TNS=-1.160 | WHS=N/A | THS=N/A | 2default:defaultZ35-416hpx H 3Phase 4.1 Global Iteration 0 | Checksum: 1a6d62ae7 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:05:06 ; elapsed = 00:03:24 . Memory (MB): peak = 3395.219 ; gain = 203.9732default:defaulthpx u Phase %s%s 101* constraints2 4.2 2default:default2& Global Iteration 12default:defaultZ18-101hpx  Intermediate Timing Summary %s164*route2J 6| WNS=-0.186 | TNS=-0.904 | WHS=N/A | THS=N/A | 2default:defaultZ35-416hpx H 3Phase 4.2 Global Iteration 1 | Checksum: 1fe52110a *commonhpx   %s * constraints2q ]Time (s): cpu = 00:05:36 ; elapsed = 00:03:50 . Memory (MB): peak = 3395.246 ; gain = 204.0002default:defaulthpx u Phase %s%s 101* constraints2 4.3 2default:default2& Global Iteration 22default:defaultZ18-101hpx  Intermediate Timing Summary %s164*route2J 6| WNS=-0.058 | TNS=-0.452 | WHS=N/A | THS=N/A | 2default:defaultZ35-416hpx H 3Phase 4.3 Global Iteration 2 | Checksum: 154def2ce *commonhpx   %s * constraints2q ]Time (s): cpu = 00:05:53 ; elapsed = 00:04:05 . Memory (MB): peak = 3395.246 ; gain = 204.0002default:defaulthpx F 1Phase 4 Rip-up And Reroute | Checksum: 154def2ce *commonhpx   %s * constraints2q ]Time (s): cpu = 00:05:53 ; elapsed = 00:04:05 . Memory (MB): peak = 3395.246 ; gain = 204.0002default:defaulthpx | Phase %s%s 101* constraints2 5 2default:default2/ Delay and Skew Optimization2default:defaultZ18-101hpx p Phase %s%s 101* constraints2 5.1 2default:default2! Delay CleanUp2default:defaultZ18-101hpx r Phase %s%s 101* constraints2 5.1.1 2default:default2! Update Timing2default:defaultZ18-101hpx E 0Phase 5.1.1 Update Timing | Checksum: 186635e48 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:06:03 ; elapsed = 00:04:12 . Memory (MB): peak = 3395.246 ; gain = 204.0002default:defaulthpx  Intermediate Timing Summary %s164*route2J 6| WNS=-0.056 | TNS=-0.131 | WHS=N/A | THS=N/A | 2default:defaultZ35-416hpx C .Phase 5.1 Delay CleanUp | Checksum: 186635e48 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:06:05 ; elapsed = 00:04:13 . Memory (MB): peak = 3395.246 ; gain = 204.0002default:defaulthpx z Phase %s%s 101* constraints2 5.2 2default:default2+ Clock Skew Optimization2default:defaultZ18-101hpx M 8Phase 5.2 Clock Skew Optimization | Checksum: 186635e48 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:06:05 ; elapsed = 00:04:13 . Memory (MB): peak = 3395.246 ; gain = 204.0002default:defaulthpx O :Phase 5 Delay and Skew Optimization | Checksum: 186635e48 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:06:06 ; elapsed = 00:04:13 . Memory (MB): peak = 3395.246 ; gain = 204.0002default:defaulthpx n Phase %s%s 101* constraints2 6 2default:default2! Post Hold Fix2default:defaultZ18-101hpx p Phase %s%s 101* constraints2 6.1 2default:default2! Hold Fix Iter2default:defaultZ18-101hpx r Phase %s%s 101* constraints2 6.1.1 2default:default2! Update Timing2default:defaultZ18-101hpx D /Phase 6.1.1 Update Timing | Checksum: e7f286ee *commonhpx   %s * constraints2q ]Time (s): cpu = 00:06:17 ; elapsed = 00:04:21 . Memory (MB): peak = 3395.246 ; gain = 204.0002default:defaulthpx  Intermediate Timing Summary %s164*route2J 6| WNS=-0.056 | TNS=-0.131 | WHS=0.010 | THS=0.000 | 2default:defaultZ35-416hpx B -Phase 6.1 Hold Fix Iter | Checksum: d752d5bc *commonhpx   %s * constraints2q ]Time (s): cpu = 00:06:18 ; elapsed = 00:04:22 . Memory (MB): peak = 3395.246 ; gain = 204.0002default:defaulthpx @ +Phase 6 Post Hold Fix | Checksum: d752d5bc *commonhpx   %s * constraints2q ]Time (s): cpu = 00:06:18 ; elapsed = 00:04:22 . Memory (MB): peak = 3395.246 ; gain = 204.0002default:defaulthpx o Phase %s%s 101* constraints2 7 2default:default2" Route finalize2default:defaultZ18-101hpx B -Phase 7 Route finalize | Checksum: 102d9c546 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:06:19 ; elapsed = 00:04:23 . Memory (MB): peak = 3395.246 ; gain = 204.0002default:defaulthpx v Phase %s%s 101* constraints2 8 2default:default2) Verifying routed nets2default:defaultZ18-101hpx I 4Phase 8 Verifying routed nets | Checksum: 102d9c546 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:06:20 ; elapsed = 00:04:23 . Memory (MB): peak = 3395.246 ; gain = 204.0002default:defaulthpx r Phase %s%s 101* constraints2 9 2default:default2% Depositing Routes2default:defaultZ18-101hpx  ,Router swapped GT pin %s to physical pin %s 200*route2 Hg_TCPIP_if.i_TCPIP_if/i_SFP3_init/SFP3_v2_7_i/gtxe2_common_0_i/GTREFCLK0Hg_TCPIP_if.i_TCPIP_if/i_SFP3_init/SFP3_v2_7_i/gtxe2_common_0_i/GTREFCLK02default:default2N GTXE2_COMMON_X0Y3/GTREFCLK1GTXE2_COMMON_X0Y3/GTREFCLK12default:default8Z35-467hpx  ,Router swapped GT pin %s to physical pin %s 200*route2 @i_ipbus_if/i_S6Link_init/S6Link_i/gt0_S6Link_i/gtxe2_i/GTREFCLK0@i_ipbus_if/i_S6Link_init/S6Link_i/gt0_S6Link_i/gtxe2_i/GTREFCLK02default:default2\ "GTXE2_CHANNEL_X0Y15/GTNORTHREFCLK1"GTXE2_CHANNEL_X0Y15/GTNORTHREFCLK12default:default8Z35-467hpx  ,Router swapped GT pin %s to physical pin %s 200*route2 9i_AMC_if/i_AMC_wrapper/i_common0/gtxe2_common_i/GTREFCLK09i_AMC_if/i_AMC_wrapper/i_common0/gtxe2_common_i/GTREFCLK02default:default2X GTXE2_COMMON_X0Y0/GTSOUTHREFCLK1 GTXE2_COMMON_X0Y0/GTSOUTHREFCLK12default:default8Z35-467hpx  ,Router swapped GT pin %s to physical pin %s 200*route2 9i_AMC_if/i_AMC_wrapper/i_common1/gtxe2_common_i/GTREFCLK09i_AMC_if/i_AMC_wrapper/i_common1/gtxe2_common_i/GTREFCLK02default:default2N GTXE2_COMMON_X0Y1/GTREFCLK1GTXE2_COMMON_X0Y1/GTREFCLK12default:default8Z35-467hpx  ,Router swapped GT pin %s to physical pin %s 200*route2 9i_AMC_if/i_AMC_wrapper/i_common2/gtxe2_common_i/GTREFCLK09i_AMC_if/i_AMC_wrapper/i_common2/gtxe2_common_i/GTREFCLK02default:default2X GTXE2_COMMON_X0Y2/GTNORTHREFCLK1 GTXE2_COMMON_X0Y2/GTNORTHREFCLK12default:default8Z35-467hpx D /Phase 9 Depositing Routes | Checksum: b2c3dda5 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:06:31 ; elapsed = 00:04:35 . Memory (MB): peak = 3395.246 ; gain = 204.0002default:defaulthpx t Phase %s%s 101* constraints2 10 2default:default2& Post Router Timing2default:defaultZ18-101hpx  Estimated Timing Summary %s 57*route2J 6| WNS=-0.056 | TNS=-0.131 | WHS=0.010 | THS=0.000 | 2default:defaultZ35-57hpx B !Router estimated timing not met. 128*routeZ35-328hpx F 1Phase 10 Post Router Timing | Checksum: b2c3dda5 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:06:32 ; elapsed = 00:04:36 . Memory (MB): peak = 3395.246 ; gain = 204.0002default:defaulthpx @ Router Completed Successfully 2* routeflowZ35-16hpx   %s * constraints2q ]Time (s): cpu = 00:06:32 ; elapsed = 00:04:36 . Memory (MB): peak = 3395.246 ; gain = 204.0002default:defaulthpx Z Releasing license: %s 83*common2" Implementation2default:defaultZ17-83hpx  G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered. 28* vivadotcl2 2082default:default2 282default:default2 02default:default2 02default:defaultZ4-41hpx ^ %s completed successfully 29* vivadotcl2 route_design2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2" route_design: 2default:default2 00:07:152default:default2 00:04:592default:default2 3395.2462default:default2 204.0002default:defaultZ17-268hp x  H &Writing timing data to binary archive.266*timingZ38-480hpx D Writing placer database... 1603* designutilsZ20-1893hpx = Writing XDEF routing. 211* designutilsZ20-211hpx J #Writing XDEF routing logical nets. 209* designutilsZ20-209hpx J #Writing XDEF routing special nets. 210* designutilsZ20-210hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2) Write XDEF Complete: 2default:default2 00:00:282default:default2 00:00:112default:default2 3395.2462default:default2 0.0002default:defaultZ17-268hp x   The %s '%s' has been generated. 621*common2 checkpoint2default:default2b ND:/amc13-firmware/proj/AMC13_T1_g2/AMC13_T1_g2.runs/impl_1/AMC13_T1_routed.dcp2default:defaultZ17-1381hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2& write_checkpoint: 2default:default2 00:00:352default:default2 00:00:192default:default2 3395.2462default:default2 0.0002default:defaultZ17-268hp x   %s4*runtcl2 mExecuting : report_drc -file AMC13_T1_drc_routed.rpt -pb AMC13_T1_drc_routed.pb -rpx AMC13_T1_drc_routed.rpx 2default:defaulthpx  Command: %s 53* vivadotcl2t `report_drc -file AMC13_T1_drc_routed.rpt -pb AMC13_T1_drc_routed.pb -rpx AMC13_T1_drc_routed.rpx2default:defaultZ4-113hpx > IP Catalog is up to date.1232*coregenZ19-1839hpx P Running DRC with %s threads 24*drc2 22default:defaultZ23-27hpx  #The results of DRC are in file %s. 168*coretcl2 RD:/amc13-firmware/proj/AMC13_T1_g2/AMC13_T1_g2.runs/impl_1/AMC13_T1_drc_routed.rptRD:/amc13-firmware/proj/AMC13_T1_g2/AMC13_T1_g2.runs/impl_1/AMC13_T1_drc_routed.rpt2default:default8Z2-168hpx \ %s completed successfully 29* vivadotcl2 report_drc2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2 report_drc: 2default:default2 00:01:062default:default2 00:00:342default:default2 3613.8162default:default2 218.5702default:defaultZ17-268hp x   %s4*runtcl2 Executing : report_methodology -file AMC13_T1_methodology_drc_routed.rpt -pb AMC13_T1_methodology_drc_routed.pb -rpx AMC13_T1_methodology_drc_routed.rpx 2default:defaulthpx  Command: %s 53* vivadotcl2 report_methodology -file AMC13_T1_methodology_drc_routed.rpt -pb AMC13_T1_methodology_drc_routed.pb -rpx AMC13_T1_methodology_drc_routed.rpx2default:defaultZ4-113hpx E %Done setting XDC timing constraints. 35*timingZ38-35hpx Y $Running Methodology with %s threads 74*drc2 22default:defaultZ23-133hpx  2The results of Report Methodology are in file %s. 450*coretcl2 ^D:/amc13-firmware/proj/AMC13_T1_g2/AMC13_T1_g2.runs/impl_1/AMC13_T1_methodology_drc_routed.rpt^D:/amc13-firmware/proj/AMC13_T1_g2/AMC13_T1_g2.runs/impl_1/AMC13_T1_methodology_drc_routed.rpt2default:default8Z2-1520hpx d %s completed successfully 29* vivadotcl2& report_methodology2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2( report_methodology: 2default:default2 00:00:462default:default2 00:00:282default:default2 3613.8162default:default2 0.0002default:defaultZ17-268hp x   %s4*runtcl2 }Executing : report_power -file AMC13_T1_power_routed.rpt -pb AMC13_T1_power_summary_routed.pb -rpx AMC13_T1_power_routed.rpx 2default:defaulthpx  Command: %s 53* vivadotcl2 preport_power -file AMC13_T1_power_routed.rpt -pb AMC13_T1_power_summary_routed.pb -rpx AMC13_T1_power_routed.rpx2default:defaultZ4-113hpx s $Power model is not available for %s 23*power2, i_DNA_PORT  i_DNA_PORT2default:default8Z33-23hpx E %Done setting XDC timing constraints. 35*timingZ38-35hpx K ,Running Vector-less Activity Propagation... 51*powerZ33-51hpx P 3 Finished Running Vector-less Activity Propagation 1*powerZ33-1hpx  Detected over-assertion of set/reset/preset/clear net with high fanouts, power estimation might not be accurate. Please run Tool - Power Constraint Wizard to set proper switching activities for control signals.282*powerZ33-332hpx  G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered. 28* vivadotcl2 2212default:default2 292default:default2 02default:default2 02default:defaultZ4-41hpx ^ %s completed successfully 29* vivadotcl2 report_power2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2" report_power: 2default:default2 00:01:072default:default2 00:00:402default:default2 3617.4652default:default2 3.6482default:defaultZ17-268hp x   %s4*runtcl2q ]Executing : report_route_status -file AMC13_T1_route_status.rpt -pb AMC13_T1_route_status.pb 2default:defaulthpx  %s4*runtcl2 Executing : report_timing_summary -max_paths 10 -file AMC13_T1_timing_summary_routed.rpt -pb AMC13_T1_timing_summary_routed.pb -rpx AMC13_T1_timing_summary_routed.rpx -warn_on_violation 2default:defaulthpx r UpdateTimingParams:%s. 91*timing29 % Speed grade: -2, Delay Type: min_max2default:defaultZ38-91hpx | CMultithreading enabled for timing update using a maximum of %s CPUs155*timing2 22default:defaultZ38-191hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2+ report_timing_summary: 2default:default2 00:00:062default:default2 00:00:052default:default2 3622.3282default:default2 4.8632default:defaultZ17-268hp x   %s4*runtcl2e QExecuting : report_incremental_reuse -file AMC13_T1_incremental_reuse_routed.rpt 2default:defaulthpx g BIncremental flow is disabled. No incremental reuse Info to report.423* vivadotclZ4-1062hpx  %s4*runtcl2e QExecuting : report_clock_utilization -file AMC13_T1_clock_utilization_routed.rpt 2default:defaulthpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. report_clock_utilization: 2default:default2 00:00:062default:default2 00:00:052default:default2 3632.0942default:default2 9.7662default:defaultZ17-268hp x   End Record