
Q
Command: %s
53*	vivadotcl2 
place_design2default:defaultZ4-113h px 
¤
@Attempting to get a license for feature '%s' and/or device '%s'
308*common2"
Implementation2default:default2
xc7k325t2default:defaultZ17-347h px 
”
0Got license for feature '%s' and/or device '%s'
310*common2"
Implementation2default:default2
xc7k325t2default:defaultZ17-349h px 
Ñ
The version limit for your license is '%s' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
719*common2
2021.012default:defaultZ17-1540h px 
P
Running DRC with %s threads
24*drc2
22default:defaultZ23-27h px 
V
DRC finished with %s
79*	vivadotcl2
0 Errors2default:defaultZ4-198h px 
e
BPlease refer to the DRC report (report_drc) for more information.
80*	vivadotclZ4-199h px 
p
,Running DRC as a precondition to command %s
22*	vivadotcl2 
place_design2default:defaultZ4-22h px 
P
Running DRC with %s threads
24*drc2
22default:defaultZ23-27h px 
±
YReport rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.%s*DRC29
 !DRC|DRC System|Rule limit reached2default:default8ZCHECK-3h px 
©
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2ƒ
 "ì
jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[10]jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[10]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[9]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[9]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[9]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[9]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
­
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2ƒ
 "ì
jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[11]jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[11]2default:default2default:default2¹
 "¢
Eg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[10]Eg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[10]2default:default2default:default2­
 "–
?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[10]	?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[10]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
­
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2ƒ
 "ì
jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[12]jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[12]2default:default2default:default2¹
 "¢
Eg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[11]Eg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[11]2default:default2default:default2­
 "–
?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[11]	?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[11]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
­
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2ƒ
 "ì
jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[13]jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[13]2default:default2default:default2¹
 "¢
Eg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[12]Eg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[12]2default:default2default:default2­
 "–
?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[12]	?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[12]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[1]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[1]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[0]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[0]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[0]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[0]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[2]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[2]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[1]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[1]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[1]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[1]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[3]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[3]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[2]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[2]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[2]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[2]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[4]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[4]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[3]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[3]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[3]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[3]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[5]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[5]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[4]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[4]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[4]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[4]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[6]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[6]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[5]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[5]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[5]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[5]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[7]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[7]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[6]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[6]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[6]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[6]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[8]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[8]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[7]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[7]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[7]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[7]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
§
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[9]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRARDADDR[9]2default:default2default:default2·
 " 
Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[8]Dg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/out[8]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[8]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/ra_reg[8]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
¯
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2ƒ
 "ì
jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[10]jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[10]2default:default2default:default2½
 "¦
Gg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[9]Gg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[9]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[9]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[9]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
³
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2ƒ
 "ì
jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[11]jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[11]2default:default2default:default2¿
 "¨
Hg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[10]Hg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[10]2default:default2default:default2­
 "–
?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[10]	?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[10]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
³
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2ƒ
 "ì
jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[12]jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[12]2default:default2default:default2¿
 "¨
Hg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[11]Hg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[11]2default:default2default:default2­
 "–
?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[11]	?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[11]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
³
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2ƒ
 "ì
jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[13]jg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[13]2default:default2default:default2¿
 "¨
Hg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[12]Hg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[12]2default:default2default:default2­
 "–
?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[12]	?g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[12]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
­
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[7]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[7]2default:default2default:default2½
 "¦
Gg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[6]Gg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[6]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[6]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[6]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
­
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[8]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[8]2default:default2default:default2½
 "¦
Gg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[7]Gg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[7]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[7]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[7]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 
­
ñRAMB18 async control check: The RAMB18E1 %s has an input control pin %s (net: %s) which is driven by a register (%s) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.%s*DRC2ã
 "Ì
Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl	Zg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2default:default2
 "ê
ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[9]ig_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/sdp_bl.ramb18_dp_bl.ram18_bl/ADDRBWRADDR[9]2default:default2default:default2½
 "¦
Gg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[8]Gg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/FIFO6463/wa_reg[8]2default:default2default:default2«
 "”
>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[8]	>g_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/wa_reg[8]2default:default2default:default2B
 *DRC|Netlist|Instance|Required Pin|RAMB18E12default:default8Z	REQP-1840h px 

yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2<
 "&
CLK_SDACLK_SDA2default:default2default:default28
  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3h px 
c
DRC finished with %s
79*	vivadotcl2)
0 Errors, 22 Warnings2default:defaultZ4-198h px 
e
BPlease refer to the DRC report (report_drc) for more information.
80*	vivadotclZ4-199h px 
U

Starting %s Task
103*constraints2
Placer2default:defaultZ18-103h px 
}
BMultithreading enabled for place_design using a maximum of %s CPUs12*	placeflow2
22default:defaultZ30-611h px 
v

Phase %s%s
101*constraints2
1 2default:default2)
Placer Initialization2default:defaultZ18-101h px 
ˆ

Phase %s%s
101*constraints2
1.1 2default:default29
%Placer Initialization Netlist Sorting2default:defaultZ18-101h px 
”
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:002default:default2 
00:00:00.0492default:default2
3191.2462default:default2
0.0002default:defaultZ17-268h px 
Z
EPhase 1.1 Placer Initialization Netlist Sorting | Checksum: c4d5ea71
*commonh px 
“

%s
*constraints2s
_Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.077 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
”
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:012default:default2 
00:00:00.0502default:default2
3191.2462default:default2
0.0002default:defaultZ17-268h px 
•

Phase %s%s
101*constraints2
1.2 2default:default2F
2IO Placement/ Clock Placement/ Build Placer Device2default:defaultZ18-101h px 
€
[Partially locked IO Bus is found. Following components of the IO Bus %s are not locked: %s
87*place2
VAUXN2default:default2æ
“ '<MSGMETA::BEGIN::BLOCK>VAUXN[7]<MSGMETA::END>'  '<MSGMETA::BEGIN::BLOCK>VAUXN[6]<MSGMETA::END>'  '<MSGMETA::BEGIN::BLOCK>VAUXN[1]<MSGMETA::END>' "
VAUXN[7]2 ':'  '"
VAUXN[6]:'  '"
VAUXN[1]:' 2default:default8Z30-87h px 
€
[Partially locked IO Bus is found. Following components of the IO Bus %s are not locked: %s
87*place2
VAUXP2default:default2æ
“ '<MSGMETA::BEGIN::BLOCK>VAUXP[7]<MSGMETA::END>'  '<MSGMETA::BEGIN::BLOCK>VAUXP[6]<MSGMETA::END>'  '<MSGMETA::BEGIN::BLOCK>VAUXP[1]<MSGMETA::END>' "
VAUXP[7]2 ':'  '"
VAUXP[6]:'  '"
VAUXP[1]:' 2default:default8Z30-87h px 
g
RPhase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: c774584e
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:00:21 ; elapsed = 00:00:14 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
}

Phase %s%s
101*constraints2
1.3 2default:default2.
Build Placer Netlist Model2default:defaultZ18-101h px 
P
;Phase 1.3 Build Placer Netlist Model | Checksum: 1be1170b4
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:00:59 ; elapsed = 00:00:41 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
z

Phase %s%s
101*constraints2
1.4 2default:default2+
Constrain Clocks/Macros2default:defaultZ18-101h px 
M
8Phase 1.4 Constrain Clocks/Macros | Checksum: 1be1170b4
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:01:00 ; elapsed = 00:00:42 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
I
4Phase 1 Placer Initialization | Checksum: 1be1170b4
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:01:00 ; elapsed = 00:00:42 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
q

Phase %s%s
101*constraints2
2 2default:default2$
Global Placement2default:defaultZ18-101h px 
p

Phase %s%s
101*constraints2
2.1 2default:default2!
Floorplanning2default:defaultZ18-101h px 
C
.Phase 2.1 Floorplanning | Checksum: 16950bff3
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:01:12 ; elapsed = 00:00:49 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
„

Phase %s%s
101*constraints2
2.2 2default:default25
!Update Timing before SLR Path Opt2default:defaultZ18-101h px 
W
BPhase 2.2 Update Timing before SLR Path Opt | Checksum: 1a08b4bf2
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:01:21 ; elapsed = 00:00:55 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
x

Phase %s%s
101*constraints2
2.3 2default:default2)
Global Placement Core2default:defaultZ18-101h px 


Phase %s%s
101*constraints2
2.3.1 2default:default20
Physical Synthesis In Placer2default:defaultZ18-101h px 

FFound %s LUTNM shape to break, %s LUT instances to create LUTNM shape
553*physynth2
152default:default2
40362default:defaultZ32-1035h px 
Ü
YBreak lutnm for timing: one critical %s, two critical %s, total %s, new lutff created %s
561*physynth2
122default:default2
32default:default2
152default:default2
12default:defaultZ32-1044h px 
ò
aEnd %s Pass. Optimized %s %s. Created %s new %s, deleted %s existing %s and moved %s existing %s
415*physynth2
12default:default2
16842default:default2!
nets or cells2default:default2
152default:default2
cells2default:default2
16692default:default2
cells2default:default2
02default:default2
cell2default:defaultZ32-775h px 
¦
=Pass %s. Identified %s candidate %s for fanout optimization.
76*physynth2
12default:default2
12default:default2
net2default:defaultZ32-76h px 

'Processed net %s. Replicated %s times.
81*physynth28
i_AMC_if/CntrRsti_AMC_if/CntrRst2default:default2
222default:default8Z32-81h px 
¯
$Optimized %s %s. Created %s new %s.
216*physynth2
12default:default2
net2default:default2
222default:default2
	instances2default:defaultZ32-232h px 
é
aEnd %s Pass. Optimized %s %s. Created %s new %s, deleted %s existing %s and moved %s existing %s
415*physynth2
12default:default2
12default:default2
net or cell2default:default2
222default:default2
cells2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:defaultZ32-775h px 
”
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:012default:default2 
00:00:00.2742default:default2
3191.2462default:default2
0.0002default:defaultZ17-268h px 
¦
=Pass %s. Identified %s candidate %s for fanout optimization.
76*physynth2
12default:default2
12default:default2
net2default:defaultZ32-76h px 
­
$Optimized %s %s. Created %s new %s.
216*physynth2
02default:default2
net2default:default2
02default:default2
instance2default:defaultZ32-232h px 
ç
aEnd %s Pass. Optimized %s %s. Created %s new %s, deleted %s existing %s and moved %s existing %s
415*physynth2
12default:default2
02default:default2
net or cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:defaultZ32-775h px 
”
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:002default:default2 
00:00:00.1422default:default2
3191.2462default:default2
0.0002default:defaultZ17-268h px 
ê
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ô
ng_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_175ng_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_1752default:default2†
wg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__129	wg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__1292default:default8Z32-117h px 
¸
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2Ä
Vg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/WRENVg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/WREN2default:default2„
vg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_2__6	vg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_2__62default:default8Z32-117h px 
î
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ö
og_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_186og_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_1862default:default2ˆ
xg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__137	xg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__1372default:default8Z32-117h px 
ê
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ô
ng_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_154ng_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_1542default:default2†
wg_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__113	wg_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__1132default:default8Z32-117h px 
ê
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ô
ng_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_196ng_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_1962default:default2†
wg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__145	wg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__1452default:default8Z32-117h px 
î
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ö
og_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_165og_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_1652default:default2ˆ
xg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__121	xg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__1212default:default8Z32-117h px 
ü
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ª
Ii_AMC_if/g_AMC_Link[3].i_AMC_Link/i_AMC_DATA/g_FIFO[3].i_FIFO_o/RDEN2_outIi_AMC_if/g_AMC_Link[3].i_AMC_Link/i_AMC_DATA/g_FIFO[3].i_FIFO_o/RDEN2_out2default:default2â
ei_AMC_if/g_AMC_Link[3].i_AMC_Link/i_AMC_DATA/g_FIFO[3].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__23	ei_AMC_if/g_AMC_Link[3].i_AMC_Link/i_AMC_DATA/g_FIFO[3].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__232default:default8Z32-117h px 
î
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ö
og_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/g_we_re[6].fifo_we_reg[1]_185og_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/g_we_re[6].fifo_we_reg[1]_1852default:default2ˆ
xg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__136	xg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__1362default:default8Z32-117h px 
´
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2Â
Ug_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/WRENUg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/WREN2default:default2‚
ug_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_2__7	ug_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_2__72default:default8Z32-117h px 
î
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ö
og_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_144og_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/g_we_re[0].fifo_re_reg[1]_1442default:default2ˆ
xg_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__105	xg_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[1].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__1052default:default8Z32-117h px 
ü
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ª
Ii_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[1].i_FIFO_o/RDEN0_outIi_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[1].i_FIFO_o/RDEN0_out2default:default2â
ei_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[1].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__42	ei_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[1].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__422default:default8Z32-117h px 
î
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ö
og_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[5].i_FIFO/g_we_re[5].fifo_we_reg[1]_184og_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[5].i_FIFO/g_we_re[5].fifo_we_reg[1]_1842default:default2ˆ
xg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[5].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__135	xg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[5].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__1352default:default8Z32-117h px 
ö
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2¢
Ei_AMC_if/g_AMC_Link[11].i_AMC_Link/i_AMC_DATA/g_FIFO[0].i_FIFO_o/RDENEi_AMC_if/g_AMC_Link[11].i_AMC_Link/i_AMC_DATA/g_FIFO[0].i_FIFO_o/RDEN2default:default2ä
fi_AMC_if/g_AMC_Link[11].i_AMC_Link/i_AMC_DATA/g_FIFO[0].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__76	fi_AMC_if/g_AMC_Link[11].i_AMC_Link/i_AMC_DATA/g_FIFO[0].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__762default:default8Z32-117h px 
ê
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ô
ng_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[4].i_FIFO/g_we_re[4].fifo_we_reg[1]_193ng_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[4].i_FIFO/g_we_re[4].fifo_we_reg[1]_1932default:default2†
wg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[4].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__142	wg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[4].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__1422default:default8Z32-117h px 
ü
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ª
Ii_AMC_if/g_AMC_Link[7].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/RDEN4_outIi_AMC_if/g_AMC_Link[7].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/RDEN4_out2default:default2â
ei_AMC_if/g_AMC_Link[7].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__53	ei_AMC_if/g_AMC_Link[7].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__532default:default8Z32-117h px 
ü
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ª
Ii_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[2].i_FIFO_o/RDEN1_outIi_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[2].i_FIFO_o/RDEN1_out2default:default2â
ei_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[2].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__43	ei_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[2].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__432default:default8Z32-117h px 
ü
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ª
Ii_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[6].i_FIFO_o/RDEN5_outIi_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[6].i_FIFO_o/RDEN5_out2default:default2â
ei_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[6].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__47	ei_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[6].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__472default:default8Z32-117h px 
¸
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2Ä
Vg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/WRENVg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/WREN2default:default2„
vg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_2__4	vg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_2__42default:default8Z32-117h px 
€
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2¬
Ji_AMC_if/g_AMC_Link[11].i_AMC_Link/i_AMC_DATA/g_FIFO[4].i_FIFO_o/RDEN3_outJi_AMC_if/g_AMC_Link[11].i_AMC_Link/i_AMC_DATA/g_FIFO[4].i_FIFO_o/RDEN3_out2default:default2ä
fi_AMC_if/g_AMC_Link[11].i_AMC_Link/i_AMC_DATA/g_FIFO[4].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__80	fi_AMC_if/g_AMC_Link[11].i_AMC_Link/i_AMC_DATA/g_FIFO[4].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__802default:default8Z32-117h px 
ü
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ª
Ii_AMC_if/g_AMC_Link[1].i_AMC_Link/i_AMC_DATA/g_FIFO[4].i_FIFO_o/RDEN3_outIi_AMC_if/g_AMC_Link[1].i_AMC_Link/i_AMC_DATA/g_FIFO[4].i_FIFO_o/RDEN3_out2default:default2â
ei_AMC_if/g_AMC_Link[1].i_AMC_Link/i_AMC_DATA/g_FIFO[4].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__10	ei_AMC_if/g_AMC_Link[1].i_AMC_Link/i_AMC_DATA/g_FIFO[4].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__102default:default8Z32-117h px 
¸
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2Ä
Vg_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/WRENVg_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/WREN2default:default2„
vg_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_2__2	vg_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[6].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_2__22default:default8Z32-117h px 
î
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ö
og_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[0].i_FIFO/g_we_re[0].fifo_we_reg[1]_158og_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[0].i_FIFO/g_we_re[0].fifo_we_reg[1]_1582default:default2ˆ
xg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[0].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__114	xg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[0].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__1142default:default8Z32-117h px 
ê
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ô
ng_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[0].i_FIFO/g_we_re[0].fifo_we_reg[1]_147ng_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[0].i_FIFO/g_we_re[0].fifo_we_reg[1]_1472default:default2†
wg_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[0].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__106	wg_TCPIP_if.i_TCPIP_if/g_TCPIP[2].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[0].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__1062default:default8Z32-117h px 
ü
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ª
Ii_AMC_if/g_AMC_Link[8].i_AMC_Link/i_AMC_DATA/g_FIFO[3].i_FIFO_o/RDEN2_outIi_AMC_if/g_AMC_Link[8].i_AMC_Link/i_AMC_DATA/g_FIFO[3].i_FIFO_o/RDEN2_out2default:default2â
ei_AMC_if/g_AMC_Link[8].i_AMC_Link/i_AMC_DATA/g_FIFO[3].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__58	ei_AMC_if/g_AMC_Link[8].i_AMC_Link/i_AMC_DATA/g_FIFO[3].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__582default:default8Z32-117h px 
ü
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ª
Ii_AMC_if/g_AMC_Link[8].i_AMC_Link/i_AMC_DATA/g_FIFO[2].i_FIFO_o/RDEN1_outIi_AMC_if/g_AMC_Link[8].i_AMC_Link/i_AMC_DATA/g_FIFO[2].i_FIFO_o/RDEN1_out2default:default2â
ei_AMC_if/g_AMC_Link[8].i_AMC_Link/i_AMC_DATA/g_FIFO[2].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__57	ei_AMC_if/g_AMC_Link[8].i_AMC_Link/i_AMC_DATA/g_FIFO[2].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__572default:default8Z32-117h px 
î
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ö
og_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[2].i_FIFO/g_we_re[2].fifo_we_reg[1]_181og_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[2].i_FIFO/g_we_re[2].fifo_we_reg[1]_1812default:default2ˆ
xg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[2].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__132	xg_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_ReTx_FIFO/g_FIFO_j[0].g_FIFO[2].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__1322default:default8Z32-117h px 
ß
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2d
&i_AMC_if/i_evt_bldr0/AMC_DATA_RdEn[10]&i_AMC_if/i_evt_bldr0/AMC_DATA_RdEn[10]2default:default2Œ
:i_AMC_if/i_evt_bldr0/bl.fifo_36_inst_bl.fifo_36_bl_i_1__93	:i_AMC_if/i_evt_bldr0/bl.fifo_36_inst_bl.fifo_36_bl_i_1__932default:default8Z32-117h px 
ê
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ô
ng_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[2].i_FIFO/g_we_re[2].fifo_we_reg[1]_170ng_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[2].i_FIFO/g_we_re[2].fifo_we_reg[1]_1702default:default2†
wg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[2].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__124	wg_TCPIP_if.i_TCPIP_if/g_TCPIP[0].i_TCPIP/i_dataFIFO/g_FIFO_j[0].g_FIFO[2].i_FIFO/bl.fifo_36_inst_bl.fifo_36_bl_i_1__1242default:default8Z32-117h px 
ü
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ª
Ii_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/RDEN4_outIi_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/RDEN4_out2default:default2â
ei_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__46	ei_AMC_if/g_AMC_Link[6].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__462default:default8Z32-117h px 
ü
DNet %s could not be optimized because driver %s could not be cloned
117*physynth2ª
Ii_AMC_if/g_AMC_Link[2].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/RDEN4_outIi_AMC_if/g_AMC_Link[2].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/RDEN4_out2default:default2â
ei_AMC_if/g_AMC_Link[2].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__18	ei_AMC_if/g_AMC_Link[2].i_AMC_Link/i_AMC_DATA/g_FIFO[5].i_FIFO_o/bl.fifo_36_inst_bl.fifo_36_bl_i_1__182default:default8Z32-117h px 
Ž
;Identified %s candidate %s for critical-cell optimization.
46*physynth2
72default:default2
nets2default:defaultZ32-46h px 
µ
+Net %s was not replicated. - no resolution
314*physynth2b
%g_TCPIP_if.i_TCPIP_if/DDR2TCPdata[26]%g_TCPIP_if.i_TCPIP_if/DDR2TCPdata[26]2default:default8Z32-571h px 
­
$Optimized %s %s. Created %s new %s.
216*physynth2
02default:default2
net2default:default2
02default:default2
instance2default:defaultZ32-232h px 
ç
aEnd %s Pass. Optimized %s %s. Created %s new %s, deleted %s existing %s and moved %s existing %s
415*physynth2
12default:default2
02default:default2
net or cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:defaultZ32-775h px 
j
FNo candidate cells for DSP register optimization found in the design.
274*physynthZ32-456h px 
ç
aEnd %s Pass. Optimized %s %s. Created %s new %s, deleted %s existing %s and moved %s existing %s
415*physynth2
22default:default2
02default:default2
net or cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:defaultZ32-775h px 
i
DNo candidate cells found for Shift Register to Pipeline optimization564*physynthZ32-1123h px 
ç
aEnd %s Pass. Optimized %s %s. Created %s new %s, deleted %s existing %s and moved %s existing %s
415*physynth2
12default:default2
02default:default2
net or cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:defaultZ32-775h px 
ì
aEnd %s Pass. Optimized %s %s. Created %s new %s, deleted %s existing %s and moved %s existing %s
415*physynth2
12default:default2
122default:default2!
nets or cells2default:default2
122default:default2
cells2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:defaultZ32-775h px 
”
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:012default:default2 
00:00:00.3132default:default2
3191.2462default:default2
0.0002default:defaultZ17-268h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[0].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[0].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[0].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[0].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[0].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[0].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[0].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[0].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
æ
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2¨
Hi_AMC_if/g_AMC_Link[0].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl	Hi_AMC_if/g_AMC_Link[0].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2
B2default:default8Z32-614h px 
’
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ô
^i_AMC_if/g_AMC_Link[10].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	^i_AMC_if/g_AMC_Link[10].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
’
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ô
^i_AMC_if/g_AMC_Link[10].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	^i_AMC_if/g_AMC_Link[10].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
’
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ô
^i_AMC_if/g_AMC_Link[10].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	^i_AMC_if/g_AMC_Link[10].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
’
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ô
^i_AMC_if/g_AMC_Link[10].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	^i_AMC_if/g_AMC_Link[10].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
è
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2ª
Ii_AMC_if/g_AMC_Link[10].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl	Ii_AMC_if/g_AMC_Link[10].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2
B2default:default8Z32-614h px 
’
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ô
^i_AMC_if/g_AMC_Link[11].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	^i_AMC_if/g_AMC_Link[11].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
’
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ô
^i_AMC_if/g_AMC_Link[11].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	^i_AMC_if/g_AMC_Link[11].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
’
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ô
^i_AMC_if/g_AMC_Link[11].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	^i_AMC_if/g_AMC_Link[11].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
’
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ô
^i_AMC_if/g_AMC_Link[11].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	^i_AMC_if/g_AMC_Link[11].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
è
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2ª
Ii_AMC_if/g_AMC_Link[11].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl	Ii_AMC_if/g_AMC_Link[11].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[1].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[1].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[1].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[1].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[1].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[1].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[1].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[1].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
æ
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2¨
Hi_AMC_if/g_AMC_Link[1].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl	Hi_AMC_if/g_AMC_Link[1].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[2].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[2].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[2].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[2].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[2].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[2].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[2].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[2].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
æ
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2¨
Hi_AMC_if/g_AMC_Link[2].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl	Hi_AMC_if/g_AMC_Link[2].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[3].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[3].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[3].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[3].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[3].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[3].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[3].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[3].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
æ
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2¨
Hi_AMC_if/g_AMC_Link[3].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl	Hi_AMC_if/g_AMC_Link[3].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[4].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[4].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[4].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[4].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[4].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[4].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[4].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[4].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
æ
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2¨
Hi_AMC_if/g_AMC_Link[4].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl	Hi_AMC_if/g_AMC_Link[4].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[5].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[5].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[5].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[5].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[5].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[5].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[5].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[5].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
æ
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2¨
Hi_AMC_if/g_AMC_Link[5].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl	Hi_AMC_if/g_AMC_Link[5].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[6].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[6].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[6].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[6].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[6].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[6].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[6].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[6].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
æ
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2¨
Hi_AMC_if/g_AMC_Link[6].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl	Hi_AMC_if/g_AMC_Link[6].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
æ
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2¨
Hi_AMC_if/g_AMC_Link[7].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl	Hi_AMC_if/g_AMC_Link[7].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[8].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[8].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[8].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[8].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[8].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[8].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[8].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[8].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
æ
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2¨
Hi_AMC_if/g_AMC_Link[8].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl	Hi_AMC_if/g_AMC_Link[8].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[9].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[9].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[9].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[9].i_AMC_Link/g_EventBuffer[1].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[9].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[9].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 

\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2Ò
]i_AMC_if/g_AMC_Link[9].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[9].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default2
B2default:default8Z32-614h px 
æ
\Property '%s' on BRAM cell '%s' Port '%s' is 0. Skip BRAM Register Optimization on the port
328*physynth2 
READ_WIDTH_B2default:default2¨
Hi_AMC_if/g_AMC_Link[9].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl	Hi_AMC_if/g_AMC_Link[9].i_AMC_Link/i_L1Ainfo/sdp_bl.ramb18_dp_bl.ram18_bl2default:default2
B2default:default8Z32-614h px 
¯
BPass %s: Identified %s candidate %s for BRAM register optimization298*physynth2
12default:default2
52default:default2
cells2default:defaultZ32-527h px 
˜
Processed cell %s. No change.340*physynth2Ò
]i_AMC_if/g_AMC_Link[3].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[3].i_AMC_Link/g_EventBuffer[0].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default8Z32-666h px 
˜
Processed cell %s. No change.340*physynth2Ò
]i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default8Z32-666h px 
˜
Processed cell %s. No change.340*physynth2Ò
]i_AMC_if/g_AMC_Link[1].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[1].i_AMC_Link/g_EventBuffer[3].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default8Z32-666h px 
˜
Processed cell %s. No change.340*physynth2Ò
]i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	]i_AMC_if/g_AMC_Link[7].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default8Z32-666h px 
š
Processed cell %s. No change.340*physynth2Ô
^i_AMC_if/g_AMC_Link[11].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl	^i_AMC_if/g_AMC_Link[11].i_AMC_Link/g_EventBuffer[2].i_EventBuffer/sdp_bl.ramb36_dp_bl.ram36_bl2default:default8Z32-666h px 
ç
aEnd %s Pass. Optimized %s %s. Created %s new %s, deleted %s existing %s and moved %s existing %s
415*physynth2
12default:default2
02default:default2
net or cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:defaultZ32-775h px 
”
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:002default:default2 
00:00:00.0682default:default2
3191.2462default:default2
0.0002default:defaultZ17-268h px 
j
FNo candidate cells for URAM register optimization found in the design
437*physynthZ32-846h px 
ç
aEnd %s Pass. Optimized %s %s. Created %s new %s, deleted %s existing %s and moved %s existing %s
415*physynth2
22default:default2
02default:default2
net or cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:defaultZ32-775h px 
o
KNo candidate nets found for dynamic/static region interface net replication521*physynthZ32-949h px 
ç
aEnd %s Pass. Optimized %s %s. Created %s new %s, deleted %s existing %s and moved %s existing %s
415*physynth2
12default:default2
02default:default2
net or cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:defaultZ32-775h px 
”
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:002default:default2 
00:00:00.0482default:default2
3191.2462default:default2
0.0002default:defaultZ17-268h px 
B
-
Summary of Physical Synthesis Optimizations
*commonh px 
B
-============================================
*commonh px 


*commonh px 


*commonh px 
²
œ-----------------------------------------------------------------------------------------------------------------------------------------------------------
*commonh px 
Î
¸|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
*commonh px 
æ
Ð|  LUT Combining                                    |           15  |           1669  |                  1684  |           0  |           1  |  00:00:03  |
|  Very High Fanout                                 |           22  |              0  |                     1  |           0  |           1  |  00:00:01  |
|  Fanout                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Critical Cell                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |           12  |              0  |                    12  |           0  |           1  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |           49  |           1669  |                  1697  |           0  |          10  |  00:00:05  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
*commonh px 


*commonh px 


*commonh px 
T
?Phase 2.3.1 Physical Synthesis In Placer | Checksum: 1d96e5605
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:03:30 ; elapsed = 00:02:21 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
K
6Phase 2.3 Global Placement Core | Checksum: 160dbd4ac
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:03:37 ; elapsed = 00:02:26 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
D
/Phase 2 Global Placement | Checksum: 160dbd4ac
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:03:37 ; elapsed = 00:02:26 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
q

Phase %s%s
101*constraints2
3 2default:default2$
Detail Placement2default:defaultZ18-101h px 
}

Phase %s%s
101*constraints2
3.1 2default:default2.
Commit Multi Column Macros2default:defaultZ18-101h px 
P
;Phase 3.1 Commit Multi Column Macros | Checksum: 14d2de81b
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:03:48 ; elapsed = 00:02:33 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 


Phase %s%s
101*constraints2
3.2 2default:default20
Commit Most Macros & LUTRAMs2default:defaultZ18-101h px 
R
=Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 15c9a46ad
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:04:10 ; elapsed = 00:02:48 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
y

Phase %s%s
101*constraints2
3.3 2default:default2*
Area Swap Optimization2default:defaultZ18-101h px 
L
7Phase 3.3 Area Swap Optimization | Checksum: 151b0598f
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:04:11 ; elapsed = 00:02:49 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 


Phase %s%s
101*constraints2
3.4 2default:default22
Pipeline Register Optimization2default:defaultZ18-101h px 
T
?Phase 3.4 Pipeline Register Optimization | Checksum: 20e174859
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:04:12 ; elapsed = 00:02:50 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
t

Phase %s%s
101*constraints2
3.5 2default:default2%
Fast Optimization2default:defaultZ18-101h px 
G
2Phase 3.5 Fast Optimization | Checksum: 188e806c7
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:04:34 ; elapsed = 00:03:03 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 


Phase %s%s
101*constraints2
3.6 2default:default20
Small Shape Detail Placement2default:defaultZ18-101h px 
R
=Phase 3.6 Small Shape Detail Placement | Checksum: 1a6918886
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:05:19 ; elapsed = 00:03:48 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
u

Phase %s%s
101*constraints2
3.7 2default:default2&
Re-assign LUT pins2default:defaultZ18-101h px 
H
3Phase 3.7 Re-assign LUT pins | Checksum: 1a3581e8a
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:05:25 ; elapsed = 00:03:56 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 


Phase %s%s
101*constraints2
3.8 2default:default22
Pipeline Register Optimization2default:defaultZ18-101h px 
T
?Phase 3.8 Pipeline Register Optimization | Checksum: 14f20bc84
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:05:27 ; elapsed = 00:03:58 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
t

Phase %s%s
101*constraints2
3.9 2default:default2%
Fast Optimization2default:defaultZ18-101h px 
G
2Phase 3.9 Fast Optimization | Checksum: 192a46bf5
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:06:05 ; elapsed = 00:04:22 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
D
/Phase 3 Detail Placement | Checksum: 192a46bf5
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:06:05 ; elapsed = 00:04:23 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
‰

Phase %s%s
101*constraints2
4 2default:default2<
(Post Placement Optimization and Clean-Up2default:defaultZ18-101h px 
{

Phase %s%s
101*constraints2
4.1 2default:default2,
Post Commit Optimization2default:defaultZ18-101h px 
E
%Done setting XDC timing constraints.
35*timingZ38-35h px 
€

Phase %s%s
101*constraints2
4.1.1 2default:default2/
Post Placement Optimization2default:defaultZ18-101h px 
V
APost Placement Optimization Initialization | Checksum: 1d2b98fe0
*commonh px 
u

Phase %s%s
101*constraints2
4.1.1.1 2default:default2"
BUFG Insertion2default:defaultZ18-101h px 
a

Starting %s Task
103*constraints2&
Physical Synthesis2default:defaultZ18-103h px 
‚

Phase %s%s
101*constraints2
1 2default:default25
!Physical Synthesis Initialization2default:defaultZ18-101h px 
€
EMultithreading enabled for phys_opt_design using a maximum of %s CPUs380*physynth2
22default:defaultZ32-721h px 
º
(%s %s Timing Summary | WNS=%s | TNS=%s |333*physynth2
	Estimated2default:default2
 2default:default2
-1.2382default:default2
-26.4732default:defaultZ32-619h px 
U
@Phase 1 Physical Synthesis Initialization | Checksum: 152236f4c
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
É
PProcessed net %s, BUFG insertion was skipped due to placement/routing conflicts.32*	placeflow2T
@g_TCPIP_if.i_TCPIP_if/g_TCPIP[1].i_TCPIP/i_EMAC_Rx_if/cmd_reg[0]2default:defaultZ46-33h px 
„
ÖBUFG insertion identified %s candidate nets. Inserted BUFG: %s, Replicated BUFG Driver: %s, Skipped due to Placement/Routing Conflicts: %s, Skipped due to Timing Degradation: %s, Skipped due to Illegal Netlist: %s.43*	placeflow2
12default:default2
02default:default2
02default:default2
12default:default2
02default:default2
02default:defaultZ46-56h px 
J
5Ending Physical Synthesis Task | Checksum: 13fddcd1a
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
H
3Phase 4.1.1.1 BUFG Insertion | Checksum: 1d2b98fe0
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:06:54 ; elapsed = 00:04:55 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
¥
hPost Placement Timing Summary WNS=%s. For the most accurate timing information please run report_timing.610*place2
-0.0452default:defaultZ30-746h px 


%s
*constraints2o
[Time (s): cpu = 00:08:31 ; elapsed = 00:06:19 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
N
9Phase 4.1 Post Commit Optimization | Checksum: 22f4095f4
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:08:32 ; elapsed = 00:06:20 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
y

Phase %s%s
101*constraints2
4.2 2default:default2*
Post Placement Cleanup2default:defaultZ18-101h px 
L
7Phase 4.2 Post Placement Cleanup | Checksum: 22f4095f4
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:08:33 ; elapsed = 00:06:20 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
s

Phase %s%s
101*constraints2
4.3 2default:default2$
Placer Reporting2default:defaultZ18-101h px 


Phase %s%s
101*constraints2
4.3.1 2default:default2.
Print Estimated Congestion2default:defaultZ18-101h px 
ì
'Post-Placement Estimated Congestion %s
38*	placeflow2ž
‰
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                4x4|
|___________|___________________|___________________|
|      South|                2x2|                4x4|
|___________|___________________|___________________|
|       East|                4x4|                4x4|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|
2default:defaultZ30-612h px 
R
=Phase 4.3.1 Print Estimated Congestion | Checksum: 22f4095f4
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:08:34 ; elapsed = 00:06:21 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
F
1Phase 4.3 Placer Reporting | Checksum: 22f4095f4
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:08:35 ; elapsed = 00:06:22 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
z

Phase %s%s
101*constraints2
4.4 2default:default2+
Final Placement Cleanup2default:defaultZ18-101h px 
”
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:002default:default2 
00:00:00.0572default:default2
3191.2462default:default2
0.0002default:defaultZ17-268h px 


%s
*constraints2o
[Time (s): cpu = 00:08:35 ; elapsed = 00:06:22 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
\
GPhase 4 Post Placement Optimization and Clean-Up | Checksum: 265456f09
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:08:35 ; elapsed = 00:06:23 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
>
)Ending Placer Task | Checksum: 17975e261
*commonh px 


%s
*constraints2o
[Time (s): cpu = 00:08:35 ; elapsed = 00:06:23 . Memory (MB): peak = 3191.246 ; gain = 0.0002default:defaulth px 
Z
Releasing license: %s
83*common2"
Implementation2default:defaultZ17-83h px 
È
G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28*	vivadotcl2
1822default:default2
252default:default2
02default:default2
02default:defaultZ4-41h px 
^
%s completed successfully
29*	vivadotcl2 
place_design2default:defaultZ4-42h px 
„
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2"
place_design: 2default:default2
00:08:442default:default2
00:06:282default:default2
3191.2462default:default2
0.0002default:defaultZ17-268h px 
H
&Writing timing data to binary archive.266*timingZ38-480h px 
D
Writing placer database...
1603*designutilsZ20-1893h px 
=
Writing XDEF routing.
211*designutilsZ20-211h px 
J
#Writing XDEF routing logical nets.
209*designutilsZ20-209h px 
J
#Writing XDEF routing special nets.
210*designutilsZ20-210h px 
‹
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2)
Write XDEF Complete: 2default:default2
00:00:222default:default2
00:00:082default:default2
3191.2462default:default2
0.0002default:defaultZ17-268h px 
Ç
 The %s '%s' has been generated.
621*common2

checkpoint2default:default2b
ND:/amc13-firmware/proj/AMC13_T1_g2/AMC13_T1_g2.runs/impl_1/AMC13_T1_placed.dcp2default:defaultZ17-1381h px 
ˆ
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2&
write_checkpoint: 2default:default2
00:00:322default:default2
00:00:182default:default2
3191.2462default:default2
0.0002default:defaultZ17-268h px 
c
%s4*runtcl2G
3Executing : report_io -file AMC13_T1_io_placed.rpt
2default:defaulth px 
€
kreport_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.150 . Memory (MB): peak = 3191.246 ; gain = 0.000
*commonh px 
˜
%s4*runtcl2|
hExecuting : report_utilization -file AMC13_T1_utilization_placed.rpt -pb AMC13_T1_utilization_placed.pb
2default:defaulth px 
€
%s4*runtcl2d
PExecuting : report_control_sets -verbose -file AMC13_T1_control_sets_placed.rpt
2default:defaulth px 
Š
ureport_control_sets: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.496 . Memory (MB): peak = 3191.246 ; gain = 0.000
*commonh px 


End Record