O Command: %s 53* vivadotcl2 opt_design2default:defaultZ4-113hpx  @Attempting to get a license for feature '%s' and/or device '%s' 308*common2" Implementation2default:default2 xc7k325t2default:defaultZ17-347hpx  0Got license for feature '%s' and/or device '%s' 310*common2" Implementation2default:default2 xc7k325t2default:defaultZ17-349hpx  The version limit for your license is '%s' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. 719*common2 2021.012default:defaultZ17-1540hpx n ,Running DRC as a precondition to command %s 22* vivadotcl2 opt_design2default:defaultZ4-22hpx R  Starting %s Task 103* constraints2 DRC2default:defaultZ18-103hpx P Running DRC with %s threads 24*drc2 22default:defaultZ23-27hpx  yIO port buffering is incomplete: Device port %s expects both input and output buffering but the buffers are incomplete.%s*DRC2< "& CLK_SDACLK_SDA2default:default2default:default28  DRC|Netlist|Port|Required Buffer2default:default8ZRPBF-3hpx a DRC finished with %s 272*project2( 0 Errors, 1 Warnings2default:defaultZ1-461hpx d BPlease refer to the DRC report (report_drc) for more information. 274*projectZ1-462hpx   %s * constraints2o [Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2024.504 ; gain = 0.0002default:defaulthpx g  Starting %s Task 103* constraints2, Cache Timing Information2default:defaultZ18-103hpx E %Done setting XDC timing constraints. 35*timingZ38-35hpx O :Ending Cache Timing Information Task | Checksum: 56eb2da2 *commonhpx   %s * constraints2p \Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 2050.313 ; gain = 25.8092default:defaulthpx a  Starting %s Task 103* constraints2& Logic Optimization2default:defaultZ18-103hpx i Phase %s%s 101* constraints2 1 2default:default2 Retarget2default:defaultZ18-101hpx w )Pushed %s inverter(s) to %s load pin(s). 98*opt2 172default:default2 182default:defaultZ31-138hpx K Retargeted %s cell(s). 49*opt2 02default:defaultZ31-49hpx ; &Phase 1 Retarget | Checksum: bbb9d0e5 *commonhpx   %s * constraints2o [Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2266.879 ; gain = 0.4922default:defaulthpx  .Phase %s created %s cells and removed %s cells267*opt2 Retarget2default:default2 192default:default2 1042default:defaultZ31-389hpx  In phase %s, %s netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 510*opt2 Retarget2default:default2 382default:defaultZ31-1021hpx u Phase %s%s 101* constraints2 2 2default:default2( Constant propagation2default:defaultZ18-101hpx u )Pushed %s inverter(s) to %s load pin(s). 98*opt2 02default:default2 02default:defaultZ31-138hpx H 3Phase 2 Constant propagation | Checksum: 1b03334d3 *commonhpx   %s * constraints2o [Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2266.879 ; gain = 0.4922default:defaulthpx  .Phase %s created %s cells and removed %s cells267*opt2( Constant propagation2default:default2 502default:default2 852default:defaultZ31-389hpx f Phase %s%s 101* constraints2 3 2default:default2 Sweep2default:defaultZ18-101hpx 9 $Phase 3 Sweep | Checksum: 25e113332 *commonhpx   %s * constraints2o [Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2266.879 ; gain = 0.4922default:defaulthpx  .Phase %s created %s cells and removed %s cells267*opt2 Sweep2default:default2 42default:default2 4252default:defaultZ31-389hpx r Phase %s%s 101* constraints2 4 2default:default2% BUFG optimization2default:defaultZ18-101hpx E 0Phase 4 BUFG optimization | Checksum: 25e113332 *commonhpx   %s * constraints2o [Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 2266.879 ; gain = 0.4922default:defaulthpx  EPhase %s created %s cells of which %s are BUFGs and removed %s cells.395*opt2% BUFG optimization2default:default2 02default:default2 02default:default2 02default:defaultZ31-662hpx | Phase %s%s 101* constraints2 5 2default:default2/ Shift Register Optimization2default:defaultZ18-101hpx  dSRL Remap converted %s SRLs to %s registers and converted %s registers of register chains to %s SRLs546*opt2 02default:default2 02default:default2 02default:default2 02default:defaultZ31-1064hpx O :Phase 5 Shift Register Optimization | Checksum: 228937452 *commonhpx   %s * constraints2o [Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 2266.879 ; gain = 0.4922default:defaulthpx  .Phase %s created %s cells and removed %s cells267*opt2/ Shift Register Optimization2default:default2 12default:default2 22default:defaultZ31-389hpx x Phase %s%s 101* constraints2 6 2default:default2+ Post Processing Netlist2default:defaultZ18-101hpx K 6Phase 6 Post Processing Netlist | Checksum: 20faf2042 *commonhpx   %s * constraints2o [Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 2266.879 ; gain = 0.4922default:defaulthpx  .Phase %s created %s cells and removed %s cells267*opt2+ Post Processing Netlist2default:default2 02default:default2 02default:defaultZ31-389hpx / Opt_design Change Summary *commonhpx / ========================= *commonhpx   *commonhpx   *commonhpx  z------------------------------------------------------------------------------------------------------------------------- *commonhpx  | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- *commonhpx  | Retarget | 19 | 104 | 38 | | Constant propagation | 50 | 85 | 0 | | Sweep | 4 | 425 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 1 | 2 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- *commonhpx   *commonhpx   *commonhpx a  Starting %s Task 103* constraints2& Connectivity Check2default:defaultZ18-103hpx   %s * constraints2s _Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.223 . Memory (MB): peak = 2266.879 ; gain = 0.0002default:defaulthpx J 5Ending Logic Optimization Task | Checksum: 218582cee *commonhpx   %s * constraints2o [Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 2266.879 ; gain = 0.4922default:defaulthpx a  Starting %s Task 103* constraints2& Power Optimization2default:defaultZ18-103hpx s 7Will skip clock gating for clocks with period < %s ns. 114*pwropt2 2.002default:defaultZ34-132hpx s $Power model is not available for %s 23*power2, i_DNA_PORT  i_DNA_PORT2default:default8Z33-23hpx E %Done setting XDC timing constraints. 35*timingZ38-35hpx = Applying IDT optimizations ... 9*pwroptZ34-9hpx ? Applying ODC optimizations ... 10*pwroptZ34-10hpx K ,Running Vector-less Activity Propagation... 51*powerZ33-51hpx P 3 Finished Running Vector-less Activity Propagation 1*powerZ33-1hpx   *pwropthpx e  Starting %s Task 103* constraints2* PowerOpt Patch Enables2default:defaultZ18-103hpx  WRITE_MODE attribute of %s BRAM(s) out of a total of %s has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. 129*pwropt2 672default:default2 1202default:defaultZ34-162hpx d +Structural ODC has moved %s WE to EN ports 155*pwropt2 22default:defaultZ34-201hpx  CNumber of BRAM Ports augmented: %s newly gated: %s Total Ports: %s 65*pwropt2 772default:default2 112default:default2 2402default:defaultZ34-65hpx N 9Ending PowerOpt Patch Enables Task | Checksum: 1d8f8a179 *commonhpx   %s * constraints2s _Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.937 . Memory (MB): peak = 3209.211 ; gain = 0.0002default:defaulthpx J 5Ending Power Optimization Task | Checksum: 1d8f8a179 *commonhpx   %s * constraints2q ]Time (s): cpu = 00:00:46 ; elapsed = 00:00:25 . Memory (MB): peak = 3209.211 ; gain = 942.3322default:defaulthpx \  Starting %s Task 103* constraints2! Final Cleanup2default:defaultZ18-103hpx a  Starting %s Task 103* constraints2& Logic Optimization2default:defaultZ18-103hpx E %Done setting XDC timing constraints. 35*timingZ38-35hpx J 5Ending Logic Optimization Task | Checksum: 1cbc5ee32 *commonhpx   %s * constraints2o [Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 3209.211 ; gain = 0.0002default:defaulthpx E 0Ending Final Cleanup Task | Checksum: 1cbc5ee32 *commonhpx   %s * constraints2o [Time (s): cpu = 00:00:18 ; elapsed = 00:00:13 . Memory (MB): peak = 3209.211 ; gain = 0.0002default:defaulthpx b  Starting %s Task 103* constraints2' Netlist Obfuscation2default:defaultZ18-103hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.0502default:default2 3209.2112default:default2 0.0002default:defaultZ17-268hp x  K 6Ending Netlist Obfuscation Task | Checksum: 1cbc5ee32 *commonhpx   %s * constraints2s _Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 3209.211 ; gain = 0.0002default:defaulthpx Z Releasing license: %s 83*common2" Implementation2default:defaultZ17-83hpx  G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered. 28* vivadotcl2 392default:default2 12default:default2 02default:default2 02default:defaultZ4-41hpx \ %s completed successfully 29* vivadotcl2 opt_design2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2 opt_design: 2default:default2 00:01:362default:default2 00:01:042default:default2 3209.2112default:default2 1184.7072default:defaultZ17-268hp x  E %Done setting XDC timing constraints. 35*timingZ38-35hpx H &Writing timing data to binary archive.266*timingZ38-480hpx D Writing placer database... 1603* designutilsZ20-1893hpx = Writing XDEF routing. 211* designutilsZ20-211hpx J #Writing XDEF routing logical nets. 209* designutilsZ20-209hpx J #Writing XDEF routing special nets. 210* designutilsZ20-210hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2) Write XDEF Complete: 2default:default2 00:00:012default:default2 00:00:00.1352default:default2 3209.2112default:default2 0.0002default:defaultZ17-268hp x   The %s '%s' has been generated. 621*common2 checkpoint2default:default2g SD:/amc13-firmware/proj/AMC13_T1_CMS10G/AMC13_T1_CMS10G.runs/impl_1/AMC13_T1_opt.dcp2default:defaultZ17-1381hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2& write_checkpoint: 2default:default2 00:00:312default:default2 00:00:192default:default2 3209.2112default:default2 0.0002default:defaultZ17-268hp x   %s4*runtcl2~ jExecuting : report_drc -file AMC13_T1_drc_opted.rpt -pb AMC13_T1_drc_opted.pb -rpx AMC13_T1_drc_opted.rpx 2default:defaulthpx  Command: %s 53* vivadotcl2q ]report_drc -file AMC13_T1_drc_opted.rpt -pb AMC13_T1_drc_opted.pb -rpx AMC13_T1_drc_opted.rpx2default:defaultZ4-113hpx > Refreshing IP repositories 234*coregenZ19-234hpx G "No user IP repositories specified 1154*coregenZ19-1704hpx | "Loaded Vivado IP repository '%s'. 1332*coregen23 D:/Xilinx/Vivado/2020.2/data/ip2default:defaultZ19-2313hpx P Running DRC with %s threads 24*drc2 22default:defaultZ23-27hpx  #The results of DRC are in file %s. 168*coretcl2 YD:/amc13-firmware/proj/AMC13_T1_CMS10G/AMC13_T1_CMS10G.runs/impl_1/AMC13_T1_drc_opted.rptYD:/amc13-firmware/proj/AMC13_T1_CMS10G/AMC13_T1_CMS10G.runs/impl_1/AMC13_T1_drc_opted.rpt2default:default8Z2-168hpx \ %s completed successfully 29* vivadotcl2 report_drc2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2 report_drc: 2default:default2 00:00:352default:default2 00:00:192default:default2 3209.2112default:default2 0.0002default:defaultZ17-268hp x   End Record