u Command: %s 53* vivadotcl2D 0link_design -top AMC13_T1 -part xc7k325tffg900-22default:defaultZ4-113hpx g #Design is defaulting to srcset: %s 437* planAhead2 sources_12default:defaultZ12-437hpx j &Design is defaulting to constrset: %s 434* planAhead2 constrs_12default:defaultZ12-434hpx W Loading part %s157*device2$ xc7k325tffg900-22default:defaultZ21-403hpx  -Reading design checkpoint '%s' for cell '%s' 275*project2h TD:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/fifo_generator_0/fifo_generator_0.dcp2default:default2 qg_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[0].Inst_SLINK_opt/i1/generator_inst.i1/rnd_mem_trig/fifo_rnd2default:defaultZ1-454hpx  -Reading design checkpoint '%s' for cell '%s' 275*project2^ JD:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/lpm_fifo_dc/lpm_fifo_dc.dcp2default:default2s _g_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[0].Inst_SLINK_opt/i1/internal_FIFO/fifo_dc2default:defaultZ1-454hpx  -Reading design checkpoint '%s' for cell '%s' 275*project2d PD:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/dist_mem_gen_0/dist_mem_gen_0.dcp2default:default2a Mg_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[0].Inst_SLINK_opt/i2/mem2default:defaultZ1-454hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:012default:default2 00:00:022default:default2 1028.7422default:default2 0.0002default:defaultZ17-268hp x  h -Analyzing %s Unisim elements for replacement 17*netlist2 82652default:defaultZ29-17hpx j 2Unisim Transformation completed in %s CPU seconds 28*netlist2 32default:defaultZ29-28hpx z Netlist was created with %s %s291*project2 Vivado2default:default2 2014.3.12default:defaultZ1-479hpx K )Preparing netlist for logic optimization 349*projectZ1-570hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2{ eD:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/dist_mem_gen_0/dist_mem_gen_0/dist_mem_gen_0_early.xdc2default:default2c Mg_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[0].Inst_SLINK_opt/i2/mem 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2{ eD:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/dist_mem_gen_0/dist_mem_gen_0/dist_mem_gen_0_early.xdc2default:default2c Mg_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[0].Inst_SLINK_opt/i2/mem 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2{ eD:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/dist_mem_gen_0/dist_mem_gen_0/dist_mem_gen_0_early.xdc2default:default2c Mg_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[1].Inst_SLINK_opt/i2/mem 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2{ eD:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/dist_mem_gen_0/dist_mem_gen_0/dist_mem_gen_0_early.xdc2default:default2c Mg_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[1].Inst_SLINK_opt/i2/mem 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2{ eD:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/dist_mem_gen_0/dist_mem_gen_0/dist_mem_gen_0_early.xdc2default:default2c Mg_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[2].Inst_SLINK_opt/i2/mem 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2{ eD:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/dist_mem_gen_0/dist_mem_gen_0/dist_mem_gen_0_early.xdc2default:default2c Mg_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[2].Inst_SLINK_opt/i2/mem 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2r \D:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/lpm_fifo_dc/lpm_fifo_dc/lpm_fifo_dc_early.xdc2default:default2u _g_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[0].Inst_SLINK_opt/i1/internal_FIFO/fifo_dc 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2r \D:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/lpm_fifo_dc/lpm_fifo_dc/lpm_fifo_dc_early.xdc2default:default2u _g_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[0].Inst_SLINK_opt/i1/internal_FIFO/fifo_dc 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2r \D:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/lpm_fifo_dc/lpm_fifo_dc/lpm_fifo_dc_early.xdc2default:default2u _g_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[1].Inst_SLINK_opt/i1/internal_FIFO/fifo_dc 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2r \D:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/lpm_fifo_dc/lpm_fifo_dc/lpm_fifo_dc_early.xdc2default:default2u _g_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[1].Inst_SLINK_opt/i1/internal_FIFO/fifo_dc 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2r \D:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/lpm_fifo_dc/lpm_fifo_dc/lpm_fifo_dc_early.xdc2default:default2u _g_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[2].Inst_SLINK_opt/i1/internal_FIFO/fifo_dc 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2r \D:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/lpm_fifo_dc/lpm_fifo_dc/lpm_fifo_dc_early.xdc2default:default2u _g_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[2].Inst_SLINK_opt/i1/internal_FIFO/fifo_dc 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 kD:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/fifo_generator_0/fifo_generator_0/fifo_generator_0_early.xdc2default:default2 qg_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[0].Inst_SLINK_opt/i1/generator_inst.i1/rnd_mem_trig/fifo_rnd 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 kD:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/fifo_generator_0/fifo_generator_0/fifo_generator_0_early.xdc2default:default2 qg_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[0].Inst_SLINK_opt/i1/generator_inst.i1/rnd_mem_trig/fifo_rnd 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 kD:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/fifo_generator_0/fifo_generator_0/fifo_generator_0_early.xdc2default:default2 qg_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[1].Inst_SLINK_opt/i1/generator_inst.i1/rnd_mem_trig/fifo_rnd 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 kD:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/fifo_generator_0/fifo_generator_0/fifo_generator_0_early.xdc2default:default2 qg_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[1].Inst_SLINK_opt/i1/generator_inst.i1/rnd_mem_trig/fifo_rnd 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 kD:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/fifo_generator_0/fifo_generator_0/fifo_generator_0_early.xdc2default:default2 qg_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[2].Inst_SLINK_opt/i1/generator_inst.i1/rnd_mem_trig/fifo_rnd 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 kD:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/fifo_generator_0/fifo_generator_0/fifo_generator_0_early.xdc2default:default2 qg_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[2].Inst_SLINK_opt/i1/generator_inst.i1/rnd_mem_trig/fifo_rnd 2default:default8Z20-847hpx  Parsing XDC File [%s] 179* designutils2D .D:/amc13-firmware/src/common/DDR/ddr3_1_9a.xdc2default:default8Z20-179hpx  %Done setting XDC timing constraints. 35*timing2D .D:/amc13-firmware/src/common/DDR/ddr3_1_9a.xdc2default:default2 272default:default8@Z38-35hpx  DImplicit search of objects for pattern '%s' matched to '%s' objects.1744* planAhead2 sys_clk_p2default:default2 port2default:default2D .D:/amc13-firmware/src/common/DDR/ddr3_1_9a.xdc2default:default2 272default:default8@Z12-2286hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2* set_propagated_clock: 2default:default2 00:00:142default:default2 00:00:132default:default2 1988.1092default:default2 686.1252default:defaultZ17-268hp x   Finished Parsing XDC File [%s] 178* designutils2D .D:/amc13-firmware/src/common/DDR/ddr3_1_9a.xdc2default:default8Z20-178hpx  Parsing XDC File [%s] 179* designutils2C -D:/amc13-firmware/src/top/AMC13_T1_CMS10G.xdc2default:default8Z20-179hpx  Deriving generated clocks 2*timing2C -D:/amc13-firmware/src/top/AMC13_T1_CMS10G.xdc2default:default2 452default:default8@Z38-2hpx  Finished Parsing XDC File [%s] 178* designutils2C -D:/amc13-firmware/src/top/AMC13_T1_CMS10G.xdc2default:default8Z20-178hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2q [D:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/lpm_fifo_dc/lpm_fifo_dc/lpm_fifo_dc_late.xdc2default:default2u _g_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[0].Inst_SLINK_opt/i1/internal_FIFO/fifo_dc 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2q [D:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/lpm_fifo_dc/lpm_fifo_dc/lpm_fifo_dc_late.xdc2default:default2u _g_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[0].Inst_SLINK_opt/i1/internal_FIFO/fifo_dc 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2q [D:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/lpm_fifo_dc/lpm_fifo_dc/lpm_fifo_dc_late.xdc2default:default2u _g_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[1].Inst_SLINK_opt/i1/internal_FIFO/fifo_dc 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2q [D:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/lpm_fifo_dc/lpm_fifo_dc/lpm_fifo_dc_late.xdc2default:default2u _g_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[1].Inst_SLINK_opt/i1/internal_FIFO/fifo_dc 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2q [D:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/lpm_fifo_dc/lpm_fifo_dc/lpm_fifo_dc_late.xdc2default:default2u _g_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[2].Inst_SLINK_opt/i1/internal_FIFO/fifo_dc 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2q [D:/amc13-firmware/src/CMS_DAQ_if/10Gb/slink/ip/lpm_fifo_dc/lpm_fifo_dc/lpm_fifo_dc_late.xdc2default:default2u _g_DAQLSC_if.i_DAQLSC_if/g_10g.i_DaqLSCXG/g_SLINK_opt[2].Inst_SLINK_opt/i1/internal_FIFO/fifo_dc 2default:default8Z20-847hpx u )Pushed %s inverter(s) to %s load pin(s). 98*opt2 02default:default2 02default:defaultZ31-138hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.0512default:default2 2024.5042default:default2 0.0002default:defaultZ17-268hp x   !Unisim Transformation Summary: %s111*project2  A total of 3215 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 4 instances IOBUFDS_DCIEN => IOBUFDS_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 4 instances IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 32 instances OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 32 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 349 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 224 instances RAM64M => RAM64M (RAMD64E(x4)): 2017 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 537 instances RAM64X1D_1 => RAM64X1D (inverted pins: WCLK) (RAMD64E(x2)): 14 instances ROM256X1 => ROM256X1 (LUT6(x4), MUXF7(x2), MUXF8): 1 instance 2default:defaultZ1-111hpx  G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered. 28* vivadotcl2 132default:default2 02default:default2 02default:default2 02default:defaultZ4-41hpx ] %s completed successfully 29* vivadotcl2 link_design2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2! link_design: 2default:default2 00:01:022default:default2 00:00:592default:default2 2024.5042default:default2 995.7622default:defaultZ17-268hp x   End Record