----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:53:01 07/21/2011 
-- Design Name: 
-- Module Name:    RFREQ - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
-- module calculates new RFREQ for user selected output frequency
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_misc.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity Threshold is
    Port ( clk : in  STD_LOGIC; -- clk input
           din : in  STD_LOGIC_VECTOR(15 downto 0); -- inputs default RFREQ
           dout : out  STD_LOGIC_VECTOR(31 downto 0)); -- outputs new HS_DIV, N1 and RFREQ
end Threshold;

architecture Behavioral of Threshold is
COMPONENT sr64
  PORT (
    a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
    d : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    clk : IN STD_LOGIC;
    ce : IN STD_LOGIC;
    q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
  );
END COMPONENT;
signal old_din : std_logic_vector(15 downto 0) := (others => '0');
signal din_sr : std_logic_vector(15 downto 0) := (others => '0');
signal din_sr_cntr : std_logic_vector(4 downto 0) := (others => '0');
signal dout_sr : std_logic_vector(23 downto 0) := (others => '0');
signal new_din : std_logic_vector(3 downto 0) := (others => '0');
signal ce_din_sr : std_logic := '0';
signal start : std_logic := '0';
signal busy : std_logic := '0';
signal ratio : std_logic := '0';
signal din_srLSB : std_logic := '0';
signal LSB : std_logic := '0';
signal product_in : std_logic_vector(0 downto 0) := (others => '0');
signal sum : std_logic := '0';
signal carry : std_logic := '0';
signal sel_product : std_logic := '0';
signal multiply : std_logic := '0';
signal stop_multiply : std_logic := '0';
signal product_q : std_logic := '0';
signal product : std_logic_vector(0 downto 0) := (others => '0');
signal product_a : std_logic_vector(5 downto 0) := (others => '0');
signal ratio_a : std_logic_vector(5 downto 0) := (others => '0');
begin
dout <= x"00" & dout_sr;
process(clk)
begin
	if(clk'event and clk = '1')then
		if(start = '1')then
			old_din <= din;
		end if;
		if(start = '1')then
			busy <= '1';
		elsif(product_a(4 downto 3) = "11")then
			busy <= '0';
		end if;
		if(din = old_din or busy = '1')then
			new_din <= (others => '0');
		else
			new_din <= new_din(2 downto 0) & '1';
		end if;
		start <= not new_din(3) and new_din(2);
		if(start = '1')then
			sum <= '0';
			carry <= '0';
		else
			sum <= (din_sr(0) and ratio) xor product_q xor (carry and not LSB);
			carry <= ((ratio and product_q) or (ratio and carry) or (carry and product_q)) and din_sr(0);
		end if;
		if(start = '1' or din_srLSB = '1')then
			product_q <= '0';
		else
			product_q <= product(0);
		end if;
		if(ratio_a = "100100")then
			ce_din_sr <= '1';
		else
			ce_din_sr <= '0';
		end if;
		LSB <= ce_din_sr or start;
		if(start = '1')then
			din_sr <= din;
		elsif(ce_din_sr = '1')then
			din_sr <= din_sr(0) & din_sr(15 downto 1);
		end if;
		if(start = '1' or product_a(4 downto 3) = "11")then
			din_sr_cntr <= (others => '0');
		elsif(ce_din_sr = '1')then
			din_sr_cntr <= din_sr_cntr + 1;
		end if;
		if(start = '1')then
			din_srLSB <= '1';
		elsif(ratio_a = "100100")then
			din_srLSB <= '0';
		end if;
		if(start = '1')then
			multiply <= '1';
		elsif(din_sr_cntr(4) = '1')then
			multiply <= '0';
		end if;
		if(start = '1' or ce_din_sr = '1')then
			ratio_a <= (others => '0');
		elsif(multiply = '1')then
			ratio_a <= ratio_a + 1;
		end if;
		if(LSB = '1')then
			product_in(0) <= carry;
		else
			product_in(0) <= sum;
		end if;
		if(start = '1')then
			product_a <= "100001";
		elsif((ce_din_sr = '1' and din_sr_cntr(3 downto 0) = x"f") or product_a(4 downto 3) = "11")then
			product_a <= "000000";
		elsif(din_sr_cntr(4) = '1')then
			product_a <= product_a + 1;
		end if;
		if(din_sr_cntr(4) = '1')then
			dout_sr <= dout_sr(22 downto 0) & product_q;
		end if;
	end if;
end process;
i_product : sr64
  PORT MAP (
    a => product_a,
    d => product_in,
    clk => clk,
    ce => multiply,
    q => product
  );
i_ratio : ROM64X1
   generic map (
      INIT => X"0000000D6BF94D5E")
   port map (
      O => ratio,   -- ROM output
      A0 => ratio_a(0), -- ROM address[0]
      A1 => ratio_a(1), -- ROM address[1]
      A2 => ratio_a(2), -- ROM address[2]
      A3 => ratio_a(3), -- ROM address[3]
      A4 => ratio_a(4), -- ROM address[4]
      A5 => ratio_a(5) -- ROM address[5]
    );

end Behavioral;