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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:45:24 08/13/2012 
-- Design Name: 
-- Module Name:    sr64 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity sr64 is
    Port ( a : in  STD_LOGIC_VECTOR (5 downto 0);
           d : in  STD_LOGIC_VECTOR (0 downto 0);
           clk : in  STD_LOGIC;
           ce : in  STD_LOGIC;
           q : out  STD_LOGIC_VECTOR (0 downto 0));
end sr64;

architecture Behavioral of sr64 is
signal d_l: std_logic;
signal d_h: std_logic;
signal q_l: std_logic;
signal q_h: std_logic;
signal q31: std_logic;

begin
SRLC32E_h : SRLC32E
   generic map (
      INIT => X"00000000")
   port map (
      Q => q_h,        -- SRL data output
      Q31 => open,    -- SRL cascade output pin
      A => A(4 downto 0),        -- 5-bit shift depth select input
      CE => CE,      -- Clock enable input
      CLK => CLK,    -- Clock input
      D => q31         -- SRL data input
   );
SRLC32E_l : SRLC32E
   generic map (
      INIT => X"00000000")
   port map (
      Q => q_l,        -- SRL data output
      Q31 => q31,    -- SRL cascade output pin
      A => A(4 downto 0),        -- 5-bit shift depth select input
      CE => CE,      -- Clock enable input
      CLK => CLK,    -- Clock input
      D => D(0)         -- SRL data input
   );
q(0) <= q_l when a(5) = '0' else q_h;
end Behavioral;