--//////////////////////////////////////////////////////////////////////////////// --// ____ ____ --// / /\/ / --// /___/ \ / Vendor: Xilinx --// \ \ \/ Version : 2.5 --// \ \ Application : 7 Series FPGAs Transceivers Wizard --// / / Filename :s6link_adapt_top_lpm.vhd --// /___/ /\ --// \ \ / \ --// \___\/\___\ --// --// -- Description : This module performs TX reset and initialization. -- -- -- -- Module S6Link_adapt_top_lpm -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard -- -- -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. --***************************************************************************** library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.NUMERIC_STD.ALL; entity S6Link_ADAPT_TOP_LPM is generic ( TIMER : integer range 0 to 4095:= 150 ); port ( EN : in STD_LOGIC; GTRXRESET : in STD_LOGIC; RXPMARESET : in STD_LOGIC; RXDFELPMRESET : in STD_LOGIC; --DRP DCLK : in STD_LOGIC; DO : in STD_LOGIC_VECTOR(15 downto 0); DRDY : in STD_LOGIC; DADDR : out STD_LOGIC_VECTOR(8 downto 0); DI : out STD_LOGIC_VECTOR(15 downto 0); DEN : out STD_LOGIC; DWE : out STD_LOGIC; KLHOLD : out STD_LOGIC; KHHOLD : out STD_LOGIC; --DONE DONE : out STD_LOGIC; --Debug DEBUG : out STD_LOGIC_VECTOR(53 downto 0) ); end S6Link_ADAPT_TOP_LPM; architecture Behavioral of S6Link_ADAPT_TOP_LPM is component S6Link_adapt_starter generic( WAIT_CYC :integer range 0 to 16 := 10 ); port ( RST : in STD_LOGIC; CLK : in STD_LOGIC; DO : in STD_LOGIC_VECTOR(15 downto 0); DRDY : in STD_LOGIC; DADDR : out STD_LOGIC_VECTOR(8 downto 0); DEN : out STD_LOGIC; DWE : out STD_LOGIC; READY : out STD_LOGIC; curr_state_debug : out STD_LOGIC_VECTOR(3 downto 0); counter_debug : out STD_LOGIC_VECTOR(2 downto 0); rst_int_debug : out STD_LOGIC ); end component; component S6Link_lpm_loop_fsm is generic ( usr_clk: integer range 0 to 4095 := 3 ); Port( DCLK : in std_logic; reset : in std_logic; DRDY : in std_logic; DO : in std_logic_vector(15 downto 0); holds : out std_logic_vector(1 downto 0); DI : out std_logic_vector(15 downto 0); DADDR : out std_logic_vector(8 downto 0); DWE,DEN,kill3 : out std_logic; state : out std_logic_vector(4 downto 0); count_lock_out : out std_logic_vector(31 downto 0); store_di0 : out std_logic_vector(15 downto 0); start,enable,kill0,kill1,kill2,lock0,lock1,lock2,lock3 : out std_logic ); end component; signal rst : std_logic; signal start_done : std_logic; signal done_pre : std_logic; signal lock_done : std_logic; signal en_b : std_logic; --DRP-related signal daddr_starter : std_logic_vector(8 downto 0); signal den_starter : std_logic; signal dwe_starter : std_logic; signal daddr_lock : std_logic_vector(8 downto 0); signal den_lock : std_logic; signal dwe_lock : std_logic; signal di_lock : std_logic_vector(15 downto 0); signal holds : std_logic_vector(1 downto 0); signal rst_lock : std_logic; signal lock_done_r, lock_done_r2 : std_logic; --Debug signals signal lock_statek : std_logic_vector(4 downto 0); signal lock_countk : std_logic_vector(31 downto 0); signal lock0, lock1, lock2, lock3 : std_logic; signal starter_state : std_logic_vector(3 downto 0); signal starter_count : std_logic_vector(2 downto 0); signal starter_rst_int : std_logic; signal lock_done_rise : std_logic; signal store_di0k : std_logic_vector(15 downto 0); signal lock_state : std_logic_vector(4 downto 0); signal lock_count : std_logic_vector(31 downto 0); signal store_di0 : std_logic_vector(15 downto 0); signal start, enable, kill0, kill1, kill2 : std_logic; begin ------------------------------------------------------------/ rst <= ((GTRXRESET or RXPMARESET or RXDFELPMRESET) and EN); en_b <= not(EN); rst_lock <= not(start_done); done_pre <= lock_done; DONE <= done_pre and start_done; --So that DONE goes low immediately after any of RESET's is asserted process(DCLK) begin if rising_edge(DCLK) then lock_done_r <= lock_done; lock_done_r2 <= lock_done_r; end if; end process; lock_done_rise <= not(lock_done_r2) and lock_done_r; DEBUG <= lock_state(4 downto 0) & lock_count(31 downto 9) & store_di0(15 downto 0) & lock0 & lock1 & lock2 & lock3 & start & enable & kill0 & kill1 & kill2 & rst_lock; KLHOLD <= holds(0); KHHOLD <= holds(1); --When a block is not active, it will hold DADDR,DI,DEN,DWE low DADDR <= (others => '0') when (en_b='1') else (daddr_starter or daddr_lock); DI <= (others => '0') when (en_b='1') else di_lock; DEN <= '0' when (en_b='1') else (den_starter or den_lock); DWE <= '0' when (en_b='1') else (dwe_starter or dwe_lock); ----/*************************************** ---- Sequence of operation: ---- -adapt_starter -> triggered by any of above resets to deassert then waits for DFE LPM reset to complete ---- -agc_loop_fsm -> triggered by adapt_starter completion then waits for all loops to lock ----***************************************/ i_starter : S6Link_adapt_starter generic map( WAIT_CYC => 10 ) port map ( RST => rst, CLK => DCLK, DO => DO, DRDY => DRDY, DADDR => daddr_starter, DEN => den_starter, DWE => dwe_starter, READY => start_done, curr_state_debug => starter_state(3 downto 0), counter_debug => starter_count(2 downto 0), rst_int_debug => starter_rst_int ); i_lock : S6Link_lpm_loop_fsm generic map( usr_clk => TIMER ) port map ( DCLK => DCLK, reset => rst_lock, DRDY => DRDY, DO => DO, holds => holds, --KLHOLD,KHHOLD DI => di_lock, DADDR => daddr_lock, DWE => dwe_lock, DEN => den_lock, kill3 => lock_done, state => lock_state(4 downto 0), count_lock_out => lock_count(31 downto 0), store_di0 => store_di0, start => start, enable => enable, kill0 => kill0, kill1 => kill1, kill2 => kill2, lock0 => lock0, lock1 => lock1, lock2 => lock2, lock3 => lock3 ); end Behavioral;