AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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uhtr_trigpd_init.vhd
1 ------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : uhtr_trigpd_init.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 -- Description : This module instantiates the modules required for
13 -- reset and initialisation of the Transceiver
14 --
15 -- Module uHTR_trigPD_init
16 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
17 --
18 --
19 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
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64 
65 
66 library ieee;
67 use ieee.std_logic_1164.all;
68 use ieee.numeric_std.all;
69 use ieee.std_logic_unsigned.all;
70 library UNISIM;
71 use UNISIM.VCOMPONENTS.ALL;
72 
73 --***********************************Entity Declaration************************
74 
75 entity uHTR_trigPD_init is
76 generic
77 (
78  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
79  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
80  STABLE_CLOCK_PERIOD : integer := 20; --Period of the stable clock driving this state-machine, unit is [ns]
81  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
82 
83 );
84 port
85 (
86  SYSCLK_IN : in std_logic;
87  SOFT_RESET_IN : in std_logic;
88  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
89  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
90  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
91  GT0_DATA_VALID_IN : in std_logic;
92 
93  --_________________________________________________________________________
94  --GT0 (X1Y12)
95  --____________________________CHANNEL PORTS________________________________
96  --------------------------------- CPLL Ports -------------------------------
97  GT0_CPLLFBCLKLOST_OUT : out std_logic;
98  GT0_CPLLLOCK_OUT : out std_logic;
99  GT0_CPLLLOCKDETCLK_IN : in std_logic;
100  GT0_CPLLRESET_IN : in std_logic;
101  -------------------------- Channel - Clocking Ports ------------------------
102  GT0_GTREFCLK0_IN : in std_logic;
103  ---------------------------- Channel - DRP Ports --------------------------
104  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
105  GT0_DRPCLK_IN : in std_logic;
106  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
107  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
108  GT0_DRPEN_IN : in std_logic;
109  GT0_DRPRDY_OUT : out std_logic;
110  GT0_DRPWE_IN : in std_logic;
111  ------------------------------ Power-Down Ports ----------------------------
112  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
113  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
114  --------------------- RX Initialization and Reset Ports --------------------
115  GT0_RXUSERRDY_IN : in std_logic;
116  -------------------------- RX Margin Analysis Ports ------------------------
117  GT0_EYESCANDATAERROR_OUT : out std_logic;
118  ------------------------- Receive Ports - CDR Ports ------------------------
119  GT0_RXCDRLOCK_OUT : out std_logic;
120  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
121  GT0_RXUSRCLK_IN : in std_logic;
122  GT0_RXUSRCLK2_IN : in std_logic;
123  ------------------ Receive Ports - FPGA RX interface Ports -----------------
124  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
125  ------------------- Receive Ports - Pattern Checker Ports ------------------
126  GT0_RXPRBSERR_OUT : out std_logic;
127  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
128  ------------------- Receive Ports - Pattern Checker ports ------------------
129  GT0_RXPRBSCNTRESET_IN : in std_logic;
130  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
131  GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
132  GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
133  --------------------------- Receive Ports - RX AFE -------------------------
134  GT0_GTXRXP_IN : in std_logic;
135  ------------------------ Receive Ports - RX AFE Ports ----------------------
136  GT0_GTXRXN_IN : in std_logic;
137  ------------- Receive Ports - RX Initialization and Reset Ports ------------
138  GT0_GTRXRESET_IN : in std_logic;
139  GT0_RXPMARESET_IN : in std_logic;
140  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
141  GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
142  -------------- Receive Ports -RX Initialization and Reset Ports ------------
143  GT0_RXRESETDONE_OUT : out std_logic;
144  --------------------- TX Initialization and Reset Ports --------------------
145  GT0_GTTXRESET_IN : in std_logic;
146  GT0_TXUSERRDY_IN : in std_logic;
147  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
148  GT0_TXUSRCLK_IN : in std_logic;
149  GT0_TXUSRCLK2_IN : in std_logic;
150  ------------------ Transmit Ports - TX Data Path interface -----------------
151  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
152  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
153  GT0_GTXTXN_OUT : out std_logic;
154  GT0_GTXTXP_OUT : out std_logic;
155  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
156  GT0_TXOUTCLK_OUT : out std_logic;
157  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
158  GT0_TXOUTCLKPCS_OUT : out std_logic;
159  --------------------- Transmit Ports - TX Gearbox Ports --------------------
160  GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
161  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
162  GT0_TXRESETDONE_OUT : out std_logic;
163  ------------------ Transmit Ports - pattern Generator Ports ----------------
164  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
165 
166 
167  --____________________________COMMON PORTS________________________________
168  ---------------------- Common Block - Ref Clock Ports ---------------------
169  GT0_GTREFCLK0_COMMON_IN : in std_logic;
170  ------------------------- Common Block - QPLL Ports ------------------------
171  GT0_QPLLLOCK_OUT : out std_logic;
172  GT0_QPLLLOCKDETCLK_IN : in std_logic;
173  GT0_QPLLRESET_IN : in std_logic
174 
175 
176 );
177 
178 end uHTR_trigPD_init;
179 
180 architecture RTL of uHTR_trigPD_init is
181 
182 --**************************Component Declarations*****************************
183 
184 
185 component uHTR_trigPD
186 generic
187 (
188  -- Simulation attributes
189  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to 1 to speed up sim reset
190 
191 );
192 port
193 (
194 
195  --_________________________________________________________________________
196  --_________________________________________________________________________
197  --GT0 (X1Y12)
198  --____________________________CHANNEL PORTS________________________________
199  --------------------------------- CPLL Ports -------------------------------
200  GT0_CPLLFBCLKLOST_OUT : out std_logic;
201  GT0_CPLLLOCK_OUT : out std_logic;
202  GT0_CPLLLOCKDETCLK_IN : in std_logic;
203  GT0_CPLLREFCLKLOST_OUT : out std_logic;
204  GT0_CPLLRESET_IN : in std_logic;
205  -------------------------- Channel - Clocking Ports ------------------------
206  GT0_GTREFCLK0_IN : in std_logic;
207  ---------------------------- Channel - DRP Ports --------------------------
208  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
209  GT0_DRPCLK_IN : in std_logic;
210  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
211  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
212  GT0_DRPEN_IN : in std_logic;
213  GT0_DRPRDY_OUT : out std_logic;
214  GT0_DRPWE_IN : in std_logic;
215  ------------------------------ Power-Down Ports ----------------------------
216  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
217  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
218  --------------------- RX Initialization and Reset Ports --------------------
219  GT0_RXUSERRDY_IN : in std_logic;
220  -------------------------- RX Margin Analysis Ports ------------------------
221  GT0_EYESCANDATAERROR_OUT : out std_logic;
222  ------------------------- Receive Ports - CDR Ports ------------------------
223  GT0_RXCDRLOCK_OUT : out std_logic;
224  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
225  GT0_RXUSRCLK_IN : in std_logic;
226  GT0_RXUSRCLK2_IN : in std_logic;
227  ------------------ Receive Ports - FPGA RX interface Ports -----------------
228  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
229  ------------------- Receive Ports - Pattern Checker Ports ------------------
230  GT0_RXPRBSERR_OUT : out std_logic;
231  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
232  ------------------- Receive Ports - Pattern Checker ports ------------------
233  GT0_RXPRBSCNTRESET_IN : in std_logic;
234  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
235  GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
236  GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
237  --------------------------- Receive Ports - RX AFE -------------------------
238  GT0_GTXRXP_IN : in std_logic;
239  ------------------------ Receive Ports - RX AFE Ports ----------------------
240  GT0_GTXRXN_IN : in std_logic;
241  -------------------- Receive Ports - RX Equailizer Ports -------------------
242  GT0_RXLPMHFHOLD_IN : in std_logic;
243  GT0_RXLPMLFHOLD_IN : in std_logic;
244  --------------- Receive Ports - RX Fabric Output Control Ports -------------
245  GT0_RXOUTCLK_OUT : out std_logic;
246  ------------- Receive Ports - RX Initialization and Reset Ports ------------
247  GT0_GTRXRESET_IN : in std_logic;
248  GT0_RXPMARESET_IN : in std_logic;
249  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
250  GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
251  -------------- Receive Ports -RX Initialization and Reset Ports ------------
252  GT0_RXRESETDONE_OUT : out std_logic;
253  --------------------- TX Initialization and Reset Ports --------------------
254  GT0_GTTXRESET_IN : in std_logic;
255  GT0_TXUSERRDY_IN : in std_logic;
256  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
257  GT0_TXUSRCLK_IN : in std_logic;
258  GT0_TXUSRCLK2_IN : in std_logic;
259  ------------------ Transmit Ports - TX Data Path interface -----------------
260  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
261  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
262  GT0_GTXTXN_OUT : out std_logic;
263  GT0_GTXTXP_OUT : out std_logic;
264  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
265  GT0_TXOUTCLK_OUT : out std_logic;
266  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
267  GT0_TXOUTCLKPCS_OUT : out std_logic;
268  --------------------- Transmit Ports - TX Gearbox Ports --------------------
269  GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
270  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
271  GT0_TXRESETDONE_OUT : out std_logic;
272  ------------------ Transmit Ports - pattern Generator Ports ----------------
273  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
274 
275 
276  --____________________________COMMON PORTS________________________________
277  ---------------------- Common Block - Ref Clock Ports ---------------------
278  GT0_GTREFCLK0_COMMON_IN : in std_logic;
279  ------------------------- Common Block - QPLL Ports ------------------------
280  GT0_QPLLLOCK_OUT : out std_logic;
281  GT0_QPLLLOCKDETCLK_IN : in std_logic;
282  GT0_QPLLREFCLKLOST_OUT : out std_logic;
283  GT0_QPLLRESET_IN : in std_logic
284 
285 
286 );
287 end component;
288 
289 component uHTR_trigPD_TX_STARTUP_FSM
290  Generic(
291  GT_TYPE : string := "GTX";
292  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
293  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
294  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
295  RX_QPLL_USED : boolean := False; -- share these two generic values
296  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
297  -- is enough. For single-lane applications the automatic alignment is
298  -- sufficient
299  );
300  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
301  --or reference-clock present at startup.
302  TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
303  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
304  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
305  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
306  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
307  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
308  TXRESETDONE : in STD_LOGIC;
309  MMCM_LOCK : in STD_LOGIC;
310  GTTXRESET : out STD_LOGIC:='0';
311  MMCM_RESET : out STD_LOGIC:='0';
312  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
313  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
314  TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
315  TXUSERRDY : out STD_LOGIC:='0';
316  RUN_PHALIGNMENT : out STD_LOGIC:='0';
317  RESET_PHALIGNMENT : out STD_LOGIC:='0';
318  PHALIGNMENT_DONE : in STD_LOGIC;
319 
320  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
321  -- Retries it took to get the transceiver up and running
322  );
323 end component;
324 
325 component uHTR_trigPD_RX_STARTUP_FSM
326  Generic(
327  EXAMPLE_SIMULATION : integer := 0;
328  EQ_MODE : string := "DFE";
329  GT_TYPE : string := "GTX";
330  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
331  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
332  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
333  RX_QPLL_USED : boolean := False; -- share these two generic values
334  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
335  -- is enough. For single-lane applications the automatic alignment is
336  -- sufficient
337  );
338  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
339  --or reference-clock present at startup.
340  RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
341  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
342  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
343  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
344  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
345  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
346  RXRESETDONE : in STD_LOGIC;
347  MMCM_LOCK : in STD_LOGIC;
348  RECCLK_STABLE : in STD_LOGIC;
349  RECCLK_MONITOR_RESTART : in STD_LOGIC;
350  DATA_VALID : in STD_LOGIC;
351  TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
352  DONT_RESET_ON_DATA_ERROR : in STD_LOGIC;
353  GTRXRESET : out STD_LOGIC:='0';
354  MMCM_RESET : out STD_LOGIC:='0';
355  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
356  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
357  RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
358  RXUSERRDY : out STD_LOGIC:='0';
359  RUN_PHALIGNMENT : out STD_LOGIC;
360  PHALIGNMENT_DONE : in STD_LOGIC;
361  RESET_PHALIGNMENT : out STD_LOGIC:='0';
362  RXDFEAGCHOLD : out STD_LOGIC;
363  RXDFELFHOLD : out STD_LOGIC;
364  RXLPMLFHOLD : out STD_LOGIC;
365  RXLPMHFHOLD : out STD_LOGIC;
366  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
367  -- Retries it took to get the transceiver up and running
368  );
369 end component;
370 
371 
372 
373 
374 
375 
376  function get_cdrlock_time(is_sim : in integer) return integer is
377  variable lock_time: integer;
378  begin
379  if (is_sim = 1) then
380  lock_time := 1000;
381  else
382  lock_time := 50000 / integer(1.6); --Typical CDR lock time is 50,000UI as per DS183
383  end if;
384  return lock_time;
385  end function;
386 
387 
388 --***********************************Parameter Declarations********************
389 
390  constant DLY : time := 1 ns;
391  constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us
392  constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out
393 
394  -------------------------- GT Wrapper Wires ------------------------------
395  signal gt0_cpllreset_i : std_logic;
396  signal gt0_cpllreset_t : std_logic;
397  signal gt0_cpllrefclklost_i : std_logic;
398  signal gt0_cplllock_i : std_logic;
399  signal gt0_txresetdone_i : std_logic;
400  signal gt0_rxresetdone_i : std_logic;
401  signal gt0_gttxreset_i : std_logic;
402  signal gt0_gttxreset_t : std_logic;
403  signal gt0_gtrxreset_i : std_logic;
404  signal gt0_gtrxreset_t : std_logic;
405  signal gt0_rxdfelpmreset_i : std_logic;
406  signal gt0_txuserrdy_i : std_logic;
407  signal gt0_txuserrdy_t : std_logic;
408  signal gt0_rxuserrdy_i : std_logic;
409  signal gt0_rxuserrdy_t : std_logic;
410 
411  signal gt0_rxdfeagchold_i : std_logic;
412  signal gt0_rxdfelfhold_i : std_logic;
413  signal gt0_rxlpmlfhold_i : std_logic;
414  signal gt0_rxlpmhfhold_i : std_logic;
415 
416 
417 
418  signal gt0_qpllreset_i : std_logic;
419  signal gt0_qpllreset_t : std_logic;
420  signal gt0_qpllrefclklost_i : std_logic;
421  signal gt0_qplllock_i : std_logic;
422 
423 
424  ------------------------------- Global Signals -----------------------------
425  signal tied_to_ground_i : std_logic;
426  signal tied_to_vcc_i : std_logic;
427 
428  signal gt0_rxoutclk_i : std_logic;
429  signal gt0_recclk_stable_i : std_logic;
430 
431 
432 
433 
434 
435 
436  signal rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
437  signal rx_cdrlocked : std_logic;
438 
439 
440 
441 
442 
443 --**************************** Main Body of Code *******************************
444 begin
445  -- Static signal Assigments
446  tied_to_ground_i <= '0';
447  tied_to_vcc_i <= '1';
448 
449  ----------------------------- The GT Wrapper -----------------------------
450 
451  -- Use the instantiation template in the example directory to add the GT wrapper to your design.
452  -- In this example, the wrapper is wired up for basic operation with a frame generator and frame
453  -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
454  -- enabled, bonding should occur after alignment.
455 
456 
457  uHTR_trigPD_i : uHTR_trigPD
458  generic map
459  (
460  WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP
461  )
462  port map
463  (
464 
465  --_____________________________________________________________________
466  --_____________________________________________________________________
467  --GT0 (X1Y12)
468 
469  --------------------------------- CPLL Ports -------------------------------
470  GT0_CPLLFBCLKLOST_OUT => GT0_CPLLFBCLKLOST_OUT ,
471  GT0_CPLLLOCK_OUT => gt0_cplllock_i,
472  GT0_CPLLLOCKDETCLK_IN => GT0_CPLLLOCKDETCLK_IN ,
473  GT0_CPLLREFCLKLOST_OUT => gt0_cpllrefclklost_i ,
474  GT0_CPLLRESET_IN => gt0_cpllreset_i,
475  -------------------------- Channel - Clocking Ports ------------------------
476  GT0_GTREFCLK0_IN => GT0_GTREFCLK0_IN,
477  ---------------------------- Channel - DRP Ports --------------------------
478  GT0_DRPADDR_IN => GT0_DRPADDR_IN,
479  GT0_DRPCLK_IN => GT0_DRPCLK_IN,
480  GT0_DRPDI_IN => GT0_DRPDI_IN,
481  GT0_DRPDO_OUT => GT0_DRPDO_OUT,
482  GT0_DRPEN_IN => GT0_DRPEN_IN,
483  GT0_DRPRDY_OUT => GT0_DRPRDY_OUT,
484  GT0_DRPWE_IN => GT0_DRPWE_IN,
485  ------------------------------ Power-Down Ports ----------------------------
486  GT0_RXPD_IN => GT0_RXPD_IN,
487  GT0_TXPD_IN => GT0_TXPD_IN,
488  --------------------- RX Initialization and Reset Ports --------------------
489  GT0_RXUSERRDY_IN => gt0_rxuserrdy_i,
490  -------------------------- RX Margin Analysis Ports ------------------------
491  GT0_EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
492  ------------------------- Receive Ports - CDR Ports ------------------------
493  GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
494  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
495  GT0_RXUSRCLK_IN => GT0_RXUSRCLK_IN,
496  GT0_RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
497  ------------------ Receive Ports - FPGA RX interface Ports -----------------
498  GT0_RXDATA_OUT => GT0_RXDATA_OUT,
499  ------------------- Receive Ports - Pattern Checker Ports ------------------
500  GT0_RXPRBSERR_OUT => GT0_RXPRBSERR_OUT,
501  GT0_RXPRBSSEL_IN => GT0_RXPRBSSEL_IN,
502  ------------------- Receive Ports - Pattern Checker ports ------------------
503  GT0_RXPRBSCNTRESET_IN => GT0_RXPRBSCNTRESET_IN ,
504  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
505  GT0_RXDISPERR_OUT => GT0_RXDISPERR_OUT,
506  GT0_RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT ,
507  --------------------------- Receive Ports - RX AFE -------------------------
508  GT0_GTXRXP_IN => GT0_GTXRXP_IN,
509  ------------------------ Receive Ports - RX AFE Ports ----------------------
510  GT0_GTXRXN_IN => GT0_GTXRXN_IN,
511  -------------------- Receive Ports - RX Equailizer Ports -------------------
512  GT0_RXLPMHFHOLD_IN => gt0_rxlpmhfhold_i,
513  GT0_RXLPMLFHOLD_IN => gt0_rxlpmlfhold_i,
514  --------------- Receive Ports - RX Fabric Output Control Ports -------------
515  GT0_RXOUTCLK_OUT => gt0_rxoutclk_i,
516  ------------- Receive Ports - RX Initialization and Reset Ports ------------
517  GT0_GTRXRESET_IN => gt0_gtrxreset_i,
518  GT0_RXPMARESET_IN => GT0_RXPMARESET_IN,
519  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
520  GT0_RXCHARISK_OUT => GT0_RXCHARISK_OUT,
521  -------------- Receive Ports -RX Initialization and Reset Ports ------------
522  GT0_RXRESETDONE_OUT => gt0_rxresetdone_i,
523  --------------------- TX Initialization and Reset Ports --------------------
524  GT0_GTTXRESET_IN => gt0_gttxreset_i,
525  GT0_TXUSERRDY_IN => gt0_txuserrdy_i,
526  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
527  GT0_TXUSRCLK_IN => GT0_TXUSRCLK_IN,
528  GT0_TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
529  ------------------ Transmit Ports - TX Data Path interface -----------------
530  GT0_TXDATA_IN => GT0_TXDATA_IN,
531  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
532  GT0_GTXTXN_OUT => GT0_GTXTXN_OUT,
533  GT0_GTXTXP_OUT => GT0_GTXTXP_OUT,
534  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
535  GT0_TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
536  GT0_TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT ,
537  GT0_TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT ,
538  --------------------- Transmit Ports - TX Gearbox Ports --------------------
539  GT0_TXCHARISK_IN => GT0_TXCHARISK_IN,
540  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
541  GT0_TXRESETDONE_OUT => gt0_txresetdone_i,
542  ------------------ Transmit Ports - pattern Generator Ports ----------------
543  GT0_TXPRBSSEL_IN => GT0_TXPRBSSEL_IN,
544 
545 
546 
547 
548  --____________________________COMMON PORTS________________________________
549  ---------------------- Common Block - Ref Clock Ports ---------------------
550  GT0_GTREFCLK0_COMMON_IN => GT0_GTREFCLK0_COMMON_IN ,
551  ------------------------- Common Block - QPLL Ports ------------------------
552  GT0_QPLLLOCK_OUT => gt0_qplllock_i,
553  GT0_QPLLLOCKDETCLK_IN => GT0_QPLLLOCKDETCLK_IN ,
554  GT0_QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i ,
555  GT0_QPLLRESET_IN => gt0_qpllreset_i
556 
557  );
558 
559 
560  gt0_rxdfelpmreset_i <= tied_to_ground_i;
561 
562 
563 
564 
565  GT0_CPLLLOCK_OUT <= gt0_cplllock_i;
566  GT0_TXRESETDONE_OUT <= gt0_txresetdone_i;
567  GT0_RXRESETDONE_OUT <= gt0_rxresetdone_i;
568  GT0_QPLLLOCK_OUT <= gt0_qplllock_i;
569 
570 chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
571  gt0_cpllreset_i <= GT0_CPLLRESET_IN or gt0_cpllreset_t;
572  gt0_gttxreset_i <= GT0_GTTXRESET_IN or gt0_gttxreset_t;
573  gt0_gtrxreset_i <= GT0_GTRXRESET_IN or gt0_gtrxreset_t;
574  gt0_txuserrdy_i <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t;
575  gt0_rxuserrdy_i <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t;
576  gt0_qpllreset_i <= GT0_QPLLRESET_IN or gt0_qpllreset_t;
577 end generate chipscope;
578 
579 no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
580  gt0_cpllreset_i <= gt0_cpllreset_t;
581  gt0_gttxreset_i <= gt0_gttxreset_t;
582  gt0_gtrxreset_i <= gt0_gtrxreset_t;
583  gt0_txuserrdy_i <= gt0_txuserrdy_t;
584  gt0_rxuserrdy_i <= gt0_rxuserrdy_t;
585  gt0_qpllreset_i <= gt0_qpllreset_t;
586 end generate no_chipscope;
587 
588 
589 gt0_txresetfsm_i: uHTR_trigPD_TX_STARTUP_FSM
590 
591  generic map(
592  GT_TYPE => "GTX", --GTX or GTH or GTP
593  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
594  RETRY_COUNTER_BITWIDTH => 8,
595  TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must
596  RX_QPLL_USED => FALSE, -- share these two generic values
597  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
598  -- is enough. For single-lane applications the automatic alignment is
599  -- sufficient
600  )
601  port map (
602  STABLE_CLOCK => SYSCLK_IN,
603  TXUSERCLK => GT0_TXUSRCLK_IN,
604  SOFT_RESET => SOFT_RESET_IN,
605  QPLLREFCLKLOST => tied_to_ground_i,
606  CPLLREFCLKLOST => gt0_cpllrefclklost_i ,
607  QPLLLOCK => tied_to_vcc_i,
608  CPLLLOCK => gt0_cplllock_i,
609  TXRESETDONE => gt0_txresetdone_i,
610  MMCM_LOCK => tied_to_vcc_i,
611  GTTXRESET => gt0_gttxreset_t,
612  MMCM_RESET => open,
613  QPLL_RESET => open,
614  CPLL_RESET => gt0_cpllreset_t,
615  TX_FSM_RESET_DONE => GT0_TX_FSM_RESET_DONE_OUT ,
616  TXUSERRDY => gt0_txuserrdy_t,
617  RUN_PHALIGNMENT => open,
618  RESET_PHALIGNMENT => open,
619  PHALIGNMENT_DONE => tied_to_vcc_i,
620  RETRY_COUNTER => open
621  );
622 
623 
624 
625 
626 
627 
628 gt0_rxresetfsm_i: uHTR_trigPD_RX_STARTUP_FSM
629 
630  generic map(
631  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
632  GT_TYPE => "GTX", --GTX or GTH or GTP
633  EQ_MODE => "LPM", --Rx Equalization Mode - Set to DFE or LPM
634  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
635  RETRY_COUNTER_BITWIDTH => 8,
636  TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must
637  RX_QPLL_USED => FALSE, -- share these two generic values
638  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
639  -- is enough. For single-lane applications the automatic alignment is
640  -- sufficient
641  )
642  port map (
643  STABLE_CLOCK => SYSCLK_IN,
644  RXUSERCLK => GT0_RXUSRCLK_IN,
645  SOFT_RESET => SOFT_RESET_IN,
646  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
647  QPLLREFCLKLOST => tied_to_ground_i,
648  CPLLREFCLKLOST => gt0_cpllrefclklost_i ,
649  QPLLLOCK => tied_to_vcc_i,
650  CPLLLOCK => gt0_cplllock_i,
651  RXRESETDONE => gt0_rxresetdone_i,
652  MMCM_LOCK => tied_to_vcc_i,
653  RECCLK_STABLE => gt0_recclk_stable_i ,
654  RECCLK_MONITOR_RESTART => tied_to_ground_i,
655  DATA_VALID => GT0_DATA_VALID_IN,
656  TXUSERRDY => gt0_txuserrdy_i,
657  GTRXRESET => gt0_gtrxreset_t,
658  MMCM_RESET => open,
659  QPLL_RESET => open,
660  CPLL_RESET => open,
661  RX_FSM_RESET_DONE => GT0_RX_FSM_RESET_DONE_OUT ,
662  RXUSERRDY => gt0_rxuserrdy_t,
663  RUN_PHALIGNMENT => open,
664  RESET_PHALIGNMENT => open,
665  PHALIGNMENT_DONE => tied_to_vcc_i,
666  RXDFEAGCHOLD => gt0_rxdfeagchold_i ,
667  RXDFELFHOLD => gt0_rxdfelfhold_i,
668  RXLPMLFHOLD => gt0_rxlpmlfhold_i,
669  RXLPMHFHOLD => gt0_rxlpmhfhold_i,
670  RETRY_COUNTER => open
671  );
672 
673 
674 
675  cdrlock_timeout:process(SYSCLK_IN)
676  begin
677  if rising_edge(SYSCLK_IN) then
678  if(gt0_gtrxreset_i = '1') then
679  rx_cdrlocked <= '0';
680  rx_cdrlock_counter <= 0 after DLY;
681  elsif (rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
682  rx_cdrlocked <= '1';
683  rx_cdrlock_counter <= rx_cdrlock_counter after DLY;
684  else
685  rx_cdrlock_counter <= rx_cdrlock_counter + 1 after DLY;
686  end if;
687  end if;
688  end process;
689 
690 gt0_recclk_stable_i <= rx_cdrlocked;
691 
692 
693 
694 
695 
696 
697 
698 end RTL;
699 
700 
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