AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
uhtr_trigpd_gt.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : uhtr_trigpd_gt.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module uHTR_trigPD_GT (a GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 library UNISIM;
68 use UNISIM.VCOMPONENTS.ALL;
69 
70 --***************************** Entity Declaration ****************************
71 
72 entity uHTR_trigPD_GT is
73 generic
74 (
75  -- Simulation attributes
76  GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
77  RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
78  PMA_RSV_IN : bit_vector := x"00018480";
79  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
80 );
81 port
82 (
83  --------------------------------- CPLL Ports -------------------------------
84  CPLLFBCLKLOST_OUT : out std_logic;
85  CPLLLOCK_OUT : out std_logic;
86  CPLLLOCKDETCLK_IN : in std_logic;
87  CPLLREFCLKLOST_OUT : out std_logic;
88  CPLLRESET_IN : in std_logic;
89  -------------------------- Channel - Clocking Ports ------------------------
90  GTREFCLK0_IN : in std_logic;
91  ---------------------------- Channel - DRP Ports --------------------------
92  DRPADDR_IN : in std_logic_vector(8 downto 0);
93  DRPCLK_IN : in std_logic;
94  DRPDI_IN : in std_logic_vector(15 downto 0);
95  DRPDO_OUT : out std_logic_vector(15 downto 0);
96  DRPEN_IN : in std_logic;
97  DRPRDY_OUT : out std_logic;
98  DRPWE_IN : in std_logic;
99  ------------------------------- Clocking Ports -----------------------------
100  QPLLCLK_IN : in std_logic;
101  QPLLREFCLK_IN : in std_logic;
102  ------------------------------ Power-Down Ports ----------------------------
103  RXPD_IN : in std_logic_vector(1 downto 0);
104  TXPD_IN : in std_logic_vector(1 downto 0);
105  --------------------- RX Initialization and Reset Ports --------------------
106  RXUSERRDY_IN : in std_logic;
107  -------------------------- RX Margin Analysis Ports ------------------------
108  EYESCANDATAERROR_OUT : out std_logic;
109  ------------------------- Receive Ports - CDR Ports ------------------------
110  RXCDRLOCK_OUT : out std_logic;
111  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
112  RXUSRCLK_IN : in std_logic;
113  RXUSRCLK2_IN : in std_logic;
114  ------------------ Receive Ports - FPGA RX interface Ports -----------------
115  RXDATA_OUT : out std_logic_vector(31 downto 0);
116  ------------------- Receive Ports - Pattern Checker Ports ------------------
117  RXPRBSERR_OUT : out std_logic;
118  RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
119  ------------------- Receive Ports - Pattern Checker ports ------------------
120  RXPRBSCNTRESET_IN : in std_logic;
121  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
122  RXDISPERR_OUT : out std_logic_vector(3 downto 0);
123  RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
124  --------------------------- Receive Ports - RX AFE -------------------------
125  GTXRXP_IN : in std_logic;
126  ------------------------ Receive Ports - RX AFE Ports ----------------------
127  GTXRXN_IN : in std_logic;
128  -------------------- Receive Ports - RX Equailizer Ports -------------------
129  RXLPMHFHOLD_IN : in std_logic;
130  RXLPMLFHOLD_IN : in std_logic;
131  --------------- Receive Ports - RX Fabric Output Control Ports -------------
132  RXOUTCLK_OUT : out std_logic;
133  ------------- Receive Ports - RX Initialization and Reset Ports ------------
134  GTRXRESET_IN : in std_logic;
135  RXPMARESET_IN : in std_logic;
136  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
137  RXCHARISK_OUT : out std_logic_vector(3 downto 0);
138  -------------- Receive Ports -RX Initialization and Reset Ports ------------
139  RXRESETDONE_OUT : out std_logic;
140  --------------------- TX Initialization and Reset Ports --------------------
141  GTTXRESET_IN : in std_logic;
142  TXUSERRDY_IN : in std_logic;
143  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
144  TXUSRCLK_IN : in std_logic;
145  TXUSRCLK2_IN : in std_logic;
146  ------------------ Transmit Ports - TX Data Path interface -----------------
147  TXDATA_IN : in std_logic_vector(31 downto 0);
148  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
149  GTXTXN_OUT : out std_logic;
150  GTXTXP_OUT : out std_logic;
151  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
152  TXOUTCLK_OUT : out std_logic;
153  TXOUTCLKFABRIC_OUT : out std_logic;
154  TXOUTCLKPCS_OUT : out std_logic;
155  --------------------- Transmit Ports - TX Gearbox Ports --------------------
156  TXCHARISK_IN : in std_logic_vector(3 downto 0);
157  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
158  TXRESETDONE_OUT : out std_logic;
159  ------------------ Transmit Ports - pattern Generator Ports ----------------
160  TXPRBSSEL_IN : in std_logic_vector(2 downto 0)
161 
162 
163 );
164 
165 
166 end uHTR_trigPD_GT;
167 
168 architecture RTL of uHTR_trigPD_GT is
169 
170 --**************************** Signal Declarations ****************************
171 
172  -- ground and tied_to_vcc_i signals
173  signal tied_to_ground_i : std_logic;
174  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
175  signal tied_to_vcc_i : std_logic;
176 
177 
178 
179  -- RX Datapath signals
180  signal rxdata_i : std_logic_vector(63 downto 0);
181  signal rxchariscomma_float_i : std_logic_vector(3 downto 0);
182  signal rxcharisk_float_i : std_logic_vector(3 downto 0);
183  signal rxdisperr_float_i : std_logic_vector(3 downto 0);
184  signal rxnotintable_float_i : std_logic_vector(3 downto 0);
185  signal rxrundisp_float_i : std_logic_vector(3 downto 0);
186 
187 
188 
189  -- TX Datapath signals
190  signal txdata_i : std_logic_vector(63 downto 0);
191  signal txkerr_float_i : std_logic_vector(3 downto 0);
192  signal txrundisp_float_i : std_logic_vector(3 downto 0);
193  signal rxstartofseq_float_i : std_logic;
194 
195 --******************************** Main Body of Code***************************
196 
197 begin
198 
199  --------------------------- Static signal Assignments ---------------------
200 
201  tied_to_ground_i <= '0';
202  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
203  tied_to_vcc_i <= '1';
204 
205  ------------------- GT Datapath byte mapping -----------------
206 
207  -- The GT provides little endian data (first byte received on RXDATA(7 downto 0))
208  RXDATA_OUT <= rxdata_i(31 downto 0);
209 
210  txdata_i <= (tied_to_ground_vec_i(31 downto 0) & TXDATA_IN);
211 
212 
213 
214  ----------------------------- GTXE2 Instance --------------------------
215 
216  gtxe2_i :GTXE2_CHANNEL
217  generic map
218  (
219 
220  --_______________________ Simulation-Only Attributes ___________________
221 
222  SIM_RECEIVER_DETECT_PASS => ("TRUE"),
223  SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP),
224  SIM_TX_EIDLE_DRIVE_LEVEL => ("X"),
225  SIM_CPLLREFCLK_SEL => ("001"),
226  SIM_VERSION => ("4.0"),
227 
228 
229  ------------------RX Byte and Word Alignment Attributes---------------
230  ALIGN_COMMA_DOUBLE => ("FALSE"),
231  ALIGN_COMMA_ENABLE => ("1111111111"),
232  ALIGN_COMMA_WORD => (4),
233  ALIGN_MCOMMA_DET => ("TRUE"),
234  ALIGN_MCOMMA_VALUE => ("1010000011"),
235  ALIGN_PCOMMA_DET => ("TRUE"),
236  ALIGN_PCOMMA_VALUE => ("0101111100"),
237  SHOW_REALIGN_COMMA => ("TRUE"),
238  RXSLIDE_AUTO_WAIT => (7),
239  RXSLIDE_MODE => ("OFF"),
240  RX_SIG_VALID_DLY => (10),
241 
242  ------------------RX 8B/10B Decoder Attributes---------------
243  RX_DISPERR_SEQ_MATCH => ("TRUE"),
244  DEC_MCOMMA_DETECT => ("TRUE"),
245  DEC_PCOMMA_DETECT => ("TRUE"),
246  DEC_VALID_COMMA_ONLY => ("FALSE"),
247 
248  ------------------------RX Clock Correction Attributes----------------------
249  CBCC_DATA_SOURCE_SEL => ("DECODED"),
250  CLK_COR_SEQ_2_USE => ("FALSE"),
251  CLK_COR_KEEP_IDLE => ("FALSE"),
252  CLK_COR_MAX_LAT => (20),
253  CLK_COR_MIN_LAT => (16),
254  CLK_COR_PRECEDENCE => ("TRUE"),
255  CLK_COR_REPEAT_WAIT => (0),
256  CLK_COR_SEQ_LEN => (1),
257  CLK_COR_SEQ_1_ENABLE => ("1111"),
258  CLK_COR_SEQ_1_1 => ("0100000000"),
259  CLK_COR_SEQ_1_2 => ("0000000000"),
260  CLK_COR_SEQ_1_3 => ("0000000000"),
261  CLK_COR_SEQ_1_4 => ("0000000000"),
262  CLK_CORRECT_USE => ("FALSE"),
263  CLK_COR_SEQ_2_ENABLE => ("1111"),
264  CLK_COR_SEQ_2_1 => ("0100000000"),
265  CLK_COR_SEQ_2_2 => ("0000000000"),
266  CLK_COR_SEQ_2_3 => ("0000000000"),
267  CLK_COR_SEQ_2_4 => ("0000000000"),
268 
269  ------------------------RX Channel Bonding Attributes----------------------
270  CHAN_BOND_KEEP_ALIGN => ("FALSE"),
271  CHAN_BOND_MAX_SKEW => (1),
272  CHAN_BOND_SEQ_LEN => (1),
273  CHAN_BOND_SEQ_1_1 => ("0000000000"),
274  CHAN_BOND_SEQ_1_2 => ("0000000000"),
275  CHAN_BOND_SEQ_1_3 => ("0000000000"),
276  CHAN_BOND_SEQ_1_4 => ("0000000000"),
277  CHAN_BOND_SEQ_1_ENABLE => ("1111"),
278  CHAN_BOND_SEQ_2_1 => ("0000000000"),
279  CHAN_BOND_SEQ_2_2 => ("0000000000"),
280  CHAN_BOND_SEQ_2_3 => ("0000000000"),
281  CHAN_BOND_SEQ_2_4 => ("0000000000"),
282  CHAN_BOND_SEQ_2_ENABLE => ("1111"),
283  CHAN_BOND_SEQ_2_USE => ("FALSE"),
284  FTS_DESKEW_SEQ_ENABLE => ("1111"),
285  FTS_LANE_DESKEW_CFG => ("1111"),
286  FTS_LANE_DESKEW_EN => ("FALSE"),
287 
288  ---------------------------RX Margin Analysis Attributes----------------------------
289  ES_CONTROL => ("000000"),
290  ES_ERRDET_EN => ("FALSE"),
291  ES_EYE_SCAN_EN => ("TRUE"),
292  ES_HORZ_OFFSET => (x"000"),
293  ES_PMA_CFG => ("0000000000"),
294  ES_PRESCALE => ("00000"),
295  ES_QUALIFIER => (x"00000000000000000000"),
296  ES_QUAL_MASK => (x"00000000000000000000"),
297  ES_SDATA_MASK => (x"00000000000000000000"),
298  ES_VERT_OFFSET => ("000000000"),
299 
300  -------------------------FPGA RX Interface Attributes-------------------------
301  RX_DATA_WIDTH => (40),
302 
303  ---------------------------PMA Attributes----------------------------
304  OUTREFCLK_SEL_INV => ("11"),
305  PMA_RSV => (PMA_RSV_IN),
306  PMA_RSV2 => (x"2040"),
307  PMA_RSV3 => ("00"),
308  PMA_RSV4 => (x"00000000"),
309  RX_BIAS_CFG => ("000000000100"),
310  DMONITOR_CFG => (x"000A00"),
311  RX_CM_SEL => ("00"),
312  RX_CM_TRIM => ("000"),
313  RX_DEBUG_CFG => ("000000000000"),
314  RX_OS_CFG => ("0000010000000"),
315  TERM_RCAL_CFG => ("10000"),
316  TERM_RCAL_OVRD => ('0'),
317  TST_RSV => (x"00000000"),
318  RX_CLK25_DIV => (7),
319  TX_CLK25_DIV => (7),
320  UCODEER_CLR => ('0'),
321 
322  ---------------------------PCI Express Attributes----------------------------
323  PCS_PCIE_EN => ("FALSE"),
324 
325  ---------------------------PCS Attributes----------------------------
326  PCS_RSVD_ATTR => (PCS_RSVD_ATTR_IN),
327 
328  -------------RX Buffer Attributes------------
329  RXBUF_ADDR_MODE => ("FAST"),
330  RXBUF_EIDLE_HI_CNT => ("1000"),
331  RXBUF_EIDLE_LO_CNT => ("0000"),
332  RXBUF_EN => ("TRUE"),
333  RX_BUFFER_CFG => ("000000"),
334  RXBUF_RESET_ON_CB_CHANGE => ("TRUE"),
335  RXBUF_RESET_ON_COMMAALIGN => ("FALSE"),
336  RXBUF_RESET_ON_EIDLE => ("FALSE"),
337  RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
338  RXBUFRESET_TIME => ("00001"),
339  RXBUF_THRESH_OVFLW => (61),
340  RXBUF_THRESH_OVRD => ("FALSE"),
341  RXBUF_THRESH_UNDFLW => (4),
342  RXDLY_CFG => (x"001F"),
343  RXDLY_LCFG => (x"030"),
344  RXDLY_TAP_CFG => (x"0000"),
345  RXPH_CFG => (x"000000"),
346  RXPHDLY_CFG => (x"084020"),
347  RXPH_MONITOR_SEL => ("00000"),
348  RX_XCLK_SEL => ("RXREC"),
349  RX_DDI_SEL => ("000000"),
350  RX_DEFER_RESET_BUF_EN => ("TRUE"),
351 
352  -----------------------CDR Attributes-------------------------
353 
354  --For GTX only: Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
355 
356  --For GTX only: Display Port, HBR2 - set RXCDR_CFG=72'h038C008bff20200010
357  RXCDR_CFG => (x"03000023ff10200020"),
358  RXCDR_FR_RESET_ON_EIDLE => ('0'),
359  RXCDR_HOLD_DURING_EIDLE => ('0'),
360  RXCDR_PH_RESET_ON_EIDLE => ('0'),
361  RXCDR_LOCK_CFG => ("010101"),
362 
363  -------------------RX Initialization and Reset Attributes-------------------
364  RXCDRFREQRESET_TIME => ("00001"),
365  RXCDRPHRESET_TIME => ("00001"),
366  RXISCANRESET_TIME => ("00001"),
367  RXPCSRESET_TIME => ("00001"),
368  RXPMARESET_TIME => ("00011"),
369 
370  -------------------RX OOB Signaling Attributes-------------------
371  RXOOB_CFG => ("0000110"),
372 
373  -------------------------RX Gearbox Attributes---------------------------
374  RXGEARBOX_EN => ("FALSE"),
375  GEARBOX_MODE => ("000"),
376 
377  -------------------------PRBS Detection Attribute-----------------------
378  RXPRBS_ERR_LOOPBACK => ('0'),
379 
380  -------------Power-Down Attributes----------
381  PD_TRANS_TIME_FROM_P2 => (x"03c"),
382  PD_TRANS_TIME_NONE_P2 => (x"3c"),
383  PD_TRANS_TIME_TO_P2 => (x"64"),
384 
385  -------------RX OOB Signaling Attributes----------
386  SAS_MAX_COM => (64),
387  SAS_MIN_COM => (36),
388  SATA_BURST_SEQ_LEN => ("1111"),
389  SATA_BURST_VAL => ("100"),
390  SATA_EIDLE_VAL => ("100"),
391  SATA_MAX_BURST => (8),
392  SATA_MAX_INIT => (21),
393  SATA_MAX_WAKE => (7),
394  SATA_MIN_BURST => (4),
395  SATA_MIN_INIT => (12),
396  SATA_MIN_WAKE => (4),
397 
398  -------------RX Fabric Clock Output Control Attributes----------
399  TRANS_TIME_RATE => (x"0E"),
400 
401  --------------TX Buffer Attributes----------------
402  TXBUF_EN => ("TRUE"),
403  TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
404  TXDLY_CFG => (x"001F"),
405  TXDLY_LCFG => (x"030"),
406  TXDLY_TAP_CFG => (x"0000"),
407  TXPH_CFG => (x"0780"),
408  TXPHDLY_CFG => (x"084020"),
409  TXPH_MONITOR_SEL => ("00000"),
410  TX_XCLK_SEL => ("TXOUT"),
411 
412  -------------------------FPGA TX Interface Attributes-------------------------
413  TX_DATA_WIDTH => (40),
414 
415  -------------------------TX Configurable Driver Attributes-------------------------
416  TX_DEEMPH0 => ("00000"),
417  TX_DEEMPH1 => ("00000"),
418  TX_EIDLE_ASSERT_DELAY => ("110"),
419  TX_EIDLE_DEASSERT_DELAY => ("100"),
420  TX_LOOPBACK_DRIVE_HIZ => ("FALSE"),
421  TX_MAINCURSOR_SEL => ('0'),
422  TX_DRIVE_MODE => ("DIRECT"),
423  TX_MARGIN_FULL_0 => ("1001110"),
424  TX_MARGIN_FULL_1 => ("1001001"),
425  TX_MARGIN_FULL_2 => ("1000101"),
426  TX_MARGIN_FULL_3 => ("1000010"),
427  TX_MARGIN_FULL_4 => ("1000000"),
428  TX_MARGIN_LOW_0 => ("1000110"),
429  TX_MARGIN_LOW_1 => ("1000100"),
430  TX_MARGIN_LOW_2 => ("1000010"),
431  TX_MARGIN_LOW_3 => ("1000000"),
432  TX_MARGIN_LOW_4 => ("1000000"),
433 
434  -------------------------TX Gearbox Attributes--------------------------
435  TXGEARBOX_EN => ("FALSE"),
436 
437  -------------------------TX Initialization and Reset Attributes--------------------------
438  TXPCSRESET_TIME => ("00001"),
439  TXPMARESET_TIME => ("00001"),
440 
441  -------------------------TX Receiver Detection Attributes--------------------------
442  TX_RXDETECT_CFG => (x"1832"),
443  TX_RXDETECT_REF => ("100"),
444 
445  ----------------------------CPLL Attributes----------------------------
446  CPLL_CFG => (x"BC07DC"),
447  CPLL_FBDIV => (2),
448  CPLL_FBDIV_45 => (5),
449  CPLL_INIT_CFG => (x"00001E"),
450  CPLL_LOCK_CFG => (x"01E8"),
451  CPLL_REFCLK_DIV => (1),
452  RXOUT_DIV => (2),
453  TXOUT_DIV => (2),
454  SATA_CPLL_CFG => ("VCO_3000MHZ"),
455 
456  --------------RX Initialization and Reset Attributes-------------
457  RXDFELPMRESET_TIME => ("0001111"),
458 
459  --------------RX Equalizer Attributes-------------
460  RXLPM_HF_CFG => ("00000011110000"),
461  RXLPM_LF_CFG => ("00000011110000"),
462  RX_DFE_GAIN_CFG => (x"020FEA"),
463  RX_DFE_H2_CFG => ("000000000000"),
464  RX_DFE_H3_CFG => ("000001000000"),
465  RX_DFE_H4_CFG => ("00011110000"),
466  RX_DFE_H5_CFG => ("00011100000"),
467  RX_DFE_KL_CFG => ("0000011111110"),
468  RX_DFE_LPM_CFG => (x"0904"),
469  RX_DFE_LPM_HOLD_DURING_EIDLE => ('0'),
470  RX_DFE_UT_CFG => ("10001111000000000"),
471  RX_DFE_VP_CFG => ("00011111100000011"),
472 
473  -------------------------Power-Down Attributes-------------------------
474  RX_CLKMUX_PD => ('1'),
475  TX_CLKMUX_PD => ('1'),
476 
477  -------------------------FPGA RX Interface Attribute-------------------------
478  RX_INT_DATAWIDTH => (1),
479 
480  -------------------------FPGA TX Interface Attribute-------------------------
481  TX_INT_DATAWIDTH => (1),
482 
483  ------------------TX Configurable Driver Attributes---------------
484  TX_QPI_STATUS_EN => ('0'),
485 
486  -------------------------RX Equalizer Attributes--------------------------
487  RX_DFE_KL_CFG2 => (RX_DFE_KL_CFG2_IN),
488  RX_DFE_XYD_CFG => ("0000000000000"),
489 
490  -------------------------TX Configurable Driver Attributes--------------------------
491  TX_PREDRIVER_MODE => ('0')
492 
493 
494  )
495  port map
496  (
497  --------------------------------- CPLL Ports -------------------------------
498  CPLLFBCLKLOST => CPLLFBCLKLOST_OUT,
499  CPLLLOCK => CPLLLOCK_OUT,
500  CPLLLOCKDETCLK => CPLLLOCKDETCLK_IN,
501  CPLLLOCKEN => tied_to_vcc_i,
502  CPLLPD => tied_to_ground_i,
503  CPLLREFCLKLOST => CPLLREFCLKLOST_OUT,
504  CPLLREFCLKSEL => "001",
505  CPLLRESET => CPLLRESET_IN,
506  GTRSVD => "0000000000000000",
507  PCSRSVDIN => "0000000000000000",
508  PCSRSVDIN2 => "00000",
509  PMARSVDIN => "00000",
510  PMARSVDIN2 => "00000",
511  TSTIN => "11111111111111111111" ,
512  TSTOUT => open,
513  ---------------------------------- Channel ---------------------------------
514  CLKRSVD => "0000",
515  -------------------------- Channel - Clocking Ports ------------------------
516  GTGREFCLK => tied_to_ground_i,
517  GTNORTHREFCLK0 => tied_to_ground_i,
518  GTNORTHREFCLK1 => tied_to_ground_i,
519  GTREFCLK0 => GTREFCLK0_IN,
520  GTREFCLK1 => tied_to_ground_i,
521  GTSOUTHREFCLK0 => tied_to_ground_i,
522  GTSOUTHREFCLK1 => tied_to_ground_i,
523  ---------------------------- Channel - DRP Ports --------------------------
524  DRPADDR => DRPADDR_IN,
525  DRPCLK => DRPCLK_IN ,
526  DRPDI => DRPDI_IN,
527  DRPDO => DRPDO_OUT ,
528  DRPEN => DRPEN_IN,
529  DRPRDY => DRPRDY_OUT,
530  DRPWE => DRPWE_IN,
531  ------------------------------- Clocking Ports -----------------------------
532  GTREFCLKMONITOR => open,
533  QPLLCLK => QPLLCLK_IN,
534  QPLLREFCLK => QPLLREFCLK_IN,
535  RXSYSCLKSEL => "00",
536  TXSYSCLKSEL => "00",
537  --------------------------- Digital Monitor Ports --------------------------
538  DMONITOROUT => open,
539  ----------------- FPGA TX Interface Datapath Configuration ----------------
540  TX8B10BEN => tied_to_vcc_i,
541  ------------------------------- Loopback Ports -----------------------------
542  LOOPBACK => tied_to_ground_vec_i (2 downto 0),
543  ----------------------------- PCI Express Ports ----------------------------
544  PHYSTATUS => open,
545  RXRATE => tied_to_ground_vec_i (2 downto 0),
546  RXVALID => open,
547  ------------------------------ Power-Down Ports ----------------------------
548  RXPD => RXPD_IN,
549  TXPD => TXPD_IN,
550  -------------------------- RX 8B/10B Decoder Ports -------------------------
551  SETERRSTATUS => tied_to_ground_i,
552  --------------------- RX Initialization and Reset Ports --------------------
553  EYESCANRESET => tied_to_ground_i,
554  RXUSERRDY => RXUSERRDY_IN,
555  -------------------------- RX Margin Analysis Ports ------------------------
556  EYESCANDATAERROR => EYESCANDATAERROR_OUT ,
557  EYESCANMODE => tied_to_ground_i,
558  EYESCANTRIGGER => tied_to_ground_i,
559  ------------------------- Receive Ports - CDR Ports ------------------------
560  RXCDRFREQRESET => tied_to_ground_i,
561  RXCDRHOLD => tied_to_ground_i,
562  RXCDRLOCK => RXCDRLOCK_OUT,
563  RXCDROVRDEN => tied_to_ground_i,
564  RXCDRRESET => tied_to_ground_i,
565  RXCDRRESETRSV => tied_to_ground_i,
566  ------------------- Receive Ports - Clock Correction Ports -----------------
567  RXCLKCORCNT => open,
568  ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
569  RX8B10BEN => tied_to_vcc_i,
570  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
571  RXUSRCLK => RXUSRCLK_IN,
572  RXUSRCLK2 => RXUSRCLK2_IN,
573  ------------------ Receive Ports - FPGA RX interface Ports -----------------
574  RXDATA => rxdata_i,
575  ------------------- Receive Ports - Pattern Checker Ports ------------------
576  RXPRBSERR => RXPRBSERR_OUT,
577  RXPRBSSEL => RXPRBSSEL_IN,
578  ------------------- Receive Ports - Pattern Checker ports ------------------
579  RXPRBSCNTRESET => RXPRBSCNTRESET_IN,
580  -------------------- Receive Ports - RX Equalizer Ports -------------------
581  RXDFEXYDEN => tied_to_vcc_i,
582  RXDFEXYDHOLD => tied_to_ground_i,
583  RXDFEXYDOVRDEN => tied_to_ground_i,
584  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
585  RXDISPERR(7 downto 4) => rxdisperr_float_i,
586  RXDISPERR(3 downto 0) => RXDISPERR_OUT,
587  RXNOTINTABLE(7 downto 4) => rxnotintable_float_i,
588  RXNOTINTABLE(3 downto 0) => RXNOTINTABLE_OUT,
589  --------------------------- Receive Ports - RX AFE -------------------------
590  GTXRXP => GTXRXP_IN ,
591  ------------------------ Receive Ports - RX AFE Ports ----------------------
592  GTXRXN => GTXRXN_IN ,
593  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
594  RXBUFRESET => tied_to_ground_i,
595  RXBUFSTATUS => open,
596  RXDDIEN => tied_to_ground_i,
597  RXDLYBYPASS => tied_to_vcc_i,
598  RXDLYEN => tied_to_ground_i,
599  RXDLYOVRDEN => tied_to_ground_i,
600  RXDLYSRESET => tied_to_ground_i,
601  RXDLYSRESETDONE => open,
602  RXPHALIGN => tied_to_ground_i,
603  RXPHALIGNDONE => open,
604  RXPHALIGNEN => tied_to_ground_i,
605  RXPHDLYPD => tied_to_ground_i,
606  RXPHDLYRESET => tied_to_ground_i,
607  RXPHMONITOR => open,
608  RXPHOVRDEN => tied_to_ground_i,
609  RXPHSLIPMONITOR => open,
610  RXSTATUS => open,
611  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
612  RXBYTEISALIGNED => open,
613  RXBYTEREALIGN => open,
614  RXCOMMADET => open,
615  RXCOMMADETEN => tied_to_vcc_i,
616  RXMCOMMAALIGNEN => tied_to_vcc_i,
617  RXPCOMMAALIGNEN => tied_to_vcc_i,
618  ------------------ Receive Ports - RX Channel Bonding Ports ----------------
619  RXCHANBONDSEQ => open,
620  RXCHBONDEN => tied_to_ground_i,
621  RXCHBONDLEVEL => tied_to_ground_vec_i (2 downto 0),
622  RXCHBONDMASTER => tied_to_ground_i,
623  RXCHBONDO => open,
624  RXCHBONDSLAVE => tied_to_ground_i,
625  ----------------- Receive Ports - RX Channel Bonding Ports ----------------
626  RXCHANISALIGNED => open,
627  RXCHANREALIGN => open,
628  -------------------- Receive Ports - RX Equailizer Ports -------------------
629  RXLPMHFHOLD => RXLPMHFHOLD_IN,
630  RXLPMHFOVRDEN => tied_to_ground_i,
631  RXLPMLFHOLD => RXLPMLFHOLD_IN,
632  --------------------- Receive Ports - RX Equalizer Ports -------------------
633  RXDFEAGCHOLD => tied_to_ground_i,
634  RXDFEAGCOVRDEN => tied_to_ground_i,
635  RXDFECM1EN => tied_to_ground_i,
636  RXDFELFHOLD => tied_to_ground_i,
637  RXDFELFOVRDEN => tied_to_ground_i,
638  RXDFELPMRESET => tied_to_ground_i,
639  RXDFETAP2HOLD => tied_to_ground_i,
640  RXDFETAP2OVRDEN => tied_to_ground_i,
641  RXDFETAP3HOLD => tied_to_ground_i,
642  RXDFETAP3OVRDEN => tied_to_ground_i,
643  RXDFETAP4HOLD => tied_to_ground_i,
644  RXDFETAP4OVRDEN => tied_to_ground_i,
645  RXDFETAP5HOLD => tied_to_ground_i,
646  RXDFETAP5OVRDEN => tied_to_ground_i,
647  RXDFEUTHOLD => tied_to_ground_i,
648  RXDFEUTOVRDEN => tied_to_ground_i,
649  RXDFEVPHOLD => tied_to_ground_i,
650  RXDFEVPOVRDEN => tied_to_ground_i,
651  RXDFEVSEN => tied_to_ground_i,
652  RXLPMLFKLOVRDEN => tied_to_ground_i,
653  RXMONITOROUT => open,
654  RXMONITORSEL => "00",
655  RXOSHOLD => tied_to_ground_i,
656  RXOSOVRDEN => tied_to_ground_i,
657  ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
658  RXRATEDONE => open,
659  --------------- Receive Ports - RX Fabric Output Control Ports -------------
660  RXOUTCLK => RXOUTCLK_OUT,
661  RXOUTCLKFABRIC => open,
662  RXOUTCLKPCS => open,
663  RXOUTCLKSEL => "010",
664  ---------------------- Receive Ports - RX Gearbox Ports --------------------
665  RXDATAVALID => open,
666  RXHEADER => open,
667  RXHEADERVALID => open,
668  RXSTARTOFSEQ => open,
669  --------------------- Receive Ports - RX Gearbox Ports --------------------
670  RXGEARBOXSLIP => tied_to_ground_i,
671  ------------- Receive Ports - RX Initialization and Reset Ports ------------
672  GTRXRESET => GTRXRESET_IN,
673  RXOOBRESET => tied_to_ground_i,
674  RXPCSRESET => tied_to_ground_i,
675  RXPMARESET => RXPMARESET_IN,
676  ------------------ Receive Ports - RX Margin Analysis ports ----------------
677  RXLPMEN => tied_to_vcc_i,
678  ------------------- Receive Ports - RX OOB Signaling ports -----------------
679  RXCOMSASDET => open,
680  RXCOMWAKEDET => open,
681  ------------------ Receive Ports - RX OOB Signaling ports -----------------
682  RXCOMINITDET => open,
683  ------------------ Receive Ports - RX OOB signalling Ports -----------------
684  RXELECIDLE => open,
685  RXELECIDLEMODE => "11",
686  ----------------- Receive Ports - RX Polarity Control Ports ----------------
687  RXPOLARITY => tied_to_ground_i,
688  ---------------------- Receive Ports - RX gearbox ports --------------------
689  RXSLIDE => tied_to_ground_i,
690  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
691  RXCHARISCOMMA => open,
692  RXCHARISK(7 downto 4) => rxcharisk_float_i,
693  RXCHARISK(3 downto 0) => RXCHARISK_OUT,
694  ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
695  RXCHBONDI => "00000",
696  -------------- Receive Ports -RX Initialization and Reset Ports ------------
697  RXRESETDONE => RXRESETDONE_OUT,
698  -------------------------------- Rx AFE Ports ------------------------------
699  RXQPIEN => tied_to_ground_i,
700  RXQPISENN => open,
701  RXQPISENP => open,
702  --------------------------- TX Buffer Bypass Ports -------------------------
703  TXPHDLYTSTCLK => tied_to_ground_i,
704  ------------------------ TX Configurable Driver Ports ----------------------
705  TXPOSTCURSOR => "00000",
706  TXPOSTCURSORINV => tied_to_ground_i,
707  TXPRECURSOR => tied_to_ground_vec_i (4 downto 0),
708  TXPRECURSORINV => tied_to_ground_i,
709  TXQPIBIASEN => tied_to_ground_i,
710  TXQPISTRONGPDOWN => tied_to_ground_i,
711  TXQPIWEAKPUP => tied_to_ground_i,
712  --------------------- TX Initialization and Reset Ports --------------------
713  CFGRESET => tied_to_ground_i,
714  GTTXRESET => GTTXRESET_IN,
715  PCSRSVDOUT => open,
716  TXUSERRDY => TXUSERRDY_IN,
717  ---------------------- Transceiver Reset Mode Operation --------------------
718  GTRESETSEL => tied_to_ground_i,
719  RESETOVRD => tied_to_ground_i,
720  ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
721  TXCHARDISPMODE => tied_to_ground_vec_i (7 downto 0),
722  TXCHARDISPVAL => tied_to_ground_vec_i (7 downto 0),
723  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
724  TXUSRCLK => TXUSRCLK_IN,
725  TXUSRCLK2 => TXUSRCLK2_IN,
726  --------------------- Transmit Ports - PCI Express Ports -------------------
727  TXELECIDLE => tied_to_ground_i,
728  TXMARGIN => tied_to_ground_vec_i (2 downto 0),
729  TXRATE => tied_to_ground_vec_i (2 downto 0),
730  TXSWING => tied_to_ground_i,
731  ------------------ Transmit Ports - Pattern Generator Ports ----------------
732  TXPRBSFORCEERR => tied_to_ground_i,
733  ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
734  TXDLYBYPASS => tied_to_vcc_i,
735  TXDLYEN => tied_to_ground_i,
736  TXDLYHOLD => tied_to_ground_i,
737  TXDLYOVRDEN => tied_to_ground_i,
738  TXDLYSRESET => tied_to_ground_i,
739  TXDLYSRESETDONE => open,
740  TXDLYUPDOWN => tied_to_ground_i,
741  TXPHALIGN => tied_to_ground_i,
742  TXPHALIGNDONE => open,
743  TXPHALIGNEN => tied_to_ground_i,
744  TXPHDLYPD => tied_to_ground_i,
745  TXPHDLYRESET => tied_to_ground_i,
746  TXPHINIT => tied_to_ground_i,
747  TXPHINITDONE => open,
748  TXPHOVRDEN => tied_to_ground_i,
749  ---------------------- Transmit Ports - TX Buffer Ports --------------------
750  TXBUFSTATUS => open,
751  --------------- Transmit Ports - TX Configurable Driver Ports --------------
752  TXBUFDIFFCTRL => "100",
753  TXDEEMPH => tied_to_ground_i,
754  TXDIFFCTRL => "1000",
755  TXDIFFPD => tied_to_ground_i,
756  TXINHIBIT => tied_to_ground_i,
757  TXMAINCURSOR => "0000000" ,
758  TXPISOPD => tied_to_ground_i,
759  ------------------ Transmit Ports - TX Data Path interface -----------------
760  TXDATA => txdata_i,
761  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
762  GTXTXN => GTXTXN_OUT,
763  GTXTXP => GTXTXP_OUT,
764  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
765  TXOUTCLK => TXOUTCLK_OUT,
766  TXOUTCLKFABRIC => TXOUTCLKFABRIC_OUT ,
767  TXOUTCLKPCS => TXOUTCLKPCS_OUT,
768  TXOUTCLKSEL => "010",
769  TXRATEDONE => open,
770  --------------------- Transmit Ports - TX Gearbox Ports --------------------
771  TXCHARISK(7 downto 4) => tied_to_ground_vec_i (3 downto 0),
772  TXCHARISK(3 downto 0) => TXCHARISK_IN,
773  TXGEARBOXREADY => open,
774  TXHEADER => tied_to_ground_vec_i (2 downto 0),
775  TXSEQUENCE => tied_to_ground_vec_i (6 downto 0),
776  TXSTARTSEQ => tied_to_ground_i,
777  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
778  TXPCSRESET => tied_to_ground_i,
779  TXPMARESET => tied_to_ground_i,
780  TXRESETDONE => TXRESETDONE_OUT,
781  ------------------ Transmit Ports - TX OOB signalling Ports ----------------
782  TXCOMFINISH => open,
783  TXCOMINIT => tied_to_ground_i,
784  TXCOMSAS => tied_to_ground_i,
785  TXCOMWAKE => tied_to_ground_i,
786  TXPDELECIDLEMODE => tied_to_ground_i,
787  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
788  TXPOLARITY => tied_to_ground_i,
789  --------------- Transmit Ports - TX Receiver Detection Ports --------------
790  TXDETECTRX => tied_to_ground_i,
791  ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
792  TX8B10BBYPASS => tied_to_ground_vec_i (7 downto 0),
793  ------------------ Transmit Ports - pattern Generator Ports ----------------
794  TXPRBSSEL => TXPRBSSEL_IN,
795  ----------------------- Tx Configurable Driver Ports ----------------------
796  TXQPISENN => open,
797  TXQPISENP => open
798 
799  );
800 
801  end RTL;
802 
803 
804 
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