AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
uhtr_trig_gt.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : uhtr_trig_gt.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module uHTR_trig_GT (a GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 library UNISIM;
68 use UNISIM.VCOMPONENTS.ALL;
69 
70 --***************************** Entity Declaration ****************************
71 
72 entity uHTR_trig_GT is
73 generic
74 (
75  -- Simulation attributes
76  GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
77  RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
78  PMA_RSV_IN : bit_vector := x"00018480";
79  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
80 );
81 port
82 (
83  --------------------------------- CPLL Ports -------------------------------
84  CPLLFBCLKLOST_OUT : out std_logic;
85  CPLLLOCK_OUT : out std_logic;
86  CPLLLOCKDETCLK_IN : in std_logic;
87  CPLLREFCLKLOST_OUT : out std_logic;
88  CPLLRESET_IN : in std_logic;
89  -------------------------- Channel - Clocking Ports ------------------------
90  GTREFCLK0_IN : in std_logic;
91  ---------------------------- Channel - DRP Ports --------------------------
92  DRPADDR_IN : in std_logic_vector(8 downto 0);
93  DRPCLK_IN : in std_logic;
94  DRPDI_IN : in std_logic_vector(15 downto 0);
95  DRPDO_OUT : out std_logic_vector(15 downto 0);
96  DRPEN_IN : in std_logic;
97  DRPRDY_OUT : out std_logic;
98  DRPWE_IN : in std_logic;
99  ------------------------------- Clocking Ports -----------------------------
100  QPLLCLK_IN : in std_logic;
101  QPLLREFCLK_IN : in std_logic;
102  --------------------- RX Initialization and Reset Ports --------------------
103  RXUSERRDY_IN : in std_logic;
104  -------------------------- RX Margin Analysis Ports ------------------------
105  EYESCANDATAERROR_OUT : out std_logic;
106  ------------------------- Receive Ports - CDR Ports ------------------------
107  RXCDRLOCK_OUT : out std_logic;
108  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
109  RXUSRCLK_IN : in std_logic;
110  RXUSRCLK2_IN : in std_logic;
111  ------------------ Receive Ports - FPGA RX interface Ports -----------------
112  RXDATA_OUT : out std_logic_vector(31 downto 0);
113  ------------------- Receive Ports - Pattern Checker Ports ------------------
114  RXPRBSERR_OUT : out std_logic;
115  RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
116  ------------------- Receive Ports - Pattern Checker ports ------------------
117  RXPRBSCNTRESET_IN : in std_logic;
118  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
119  RXDISPERR_OUT : out std_logic_vector(3 downto 0);
120  RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
121  --------------------------- Receive Ports - RX AFE -------------------------
122  GTXRXP_IN : in std_logic;
123  ------------------------ Receive Ports - RX AFE Ports ----------------------
124  GTXRXN_IN : in std_logic;
125  -------------------- Receive Ports - RX Equailizer Ports -------------------
126  RXLPMHFHOLD_IN : in std_logic;
127  RXLPMLFHOLD_IN : in std_logic;
128  --------------- Receive Ports - RX Fabric Output Control Ports -------------
129  RXOUTCLK_OUT : out std_logic;
130  ------------- Receive Ports - RX Initialization and Reset Ports ------------
131  GTRXRESET_IN : in std_logic;
132  RXPMARESET_IN : in std_logic;
133  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
134  RXCHARISK_OUT : out std_logic_vector(3 downto 0);
135  -------------- Receive Ports -RX Initialization and Reset Ports ------------
136  RXRESETDONE_OUT : out std_logic;
137  --------------------- TX Initialization and Reset Ports --------------------
138  GTTXRESET_IN : in std_logic;
139  TXUSERRDY_IN : in std_logic;
140  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
141  TXUSRCLK_IN : in std_logic;
142  TXUSRCLK2_IN : in std_logic;
143  ------------------ Transmit Ports - TX Data Path interface -----------------
144  TXDATA_IN : in std_logic_vector(31 downto 0);
145  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
146  GTXTXN_OUT : out std_logic;
147  GTXTXP_OUT : out std_logic;
148  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
149  TXOUTCLK_OUT : out std_logic;
150  TXOUTCLKFABRIC_OUT : out std_logic;
151  TXOUTCLKPCS_OUT : out std_logic;
152  --------------------- Transmit Ports - TX Gearbox Ports --------------------
153  TXCHARISK_IN : in std_logic_vector(3 downto 0);
154  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
155  TXRESETDONE_OUT : out std_logic;
156  ------------------ Transmit Ports - pattern Generator Ports ----------------
157  TXPRBSSEL_IN : in std_logic_vector(2 downto 0)
158 
159 
160 );
161 
162 
163 end uHTR_trig_GT;
164 
165 architecture RTL of uHTR_trig_GT is
166 
167 --**************************** Signal Declarations ****************************
168 
169  -- ground and tied_to_vcc_i signals
170  signal tied_to_ground_i : std_logic;
171  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
172  signal tied_to_vcc_i : std_logic;
173 
174 
175 
176  -- RX Datapath signals
177  signal rxdata_i : std_logic_vector(63 downto 0);
178  signal rxchariscomma_float_i : std_logic_vector(3 downto 0);
179  signal rxcharisk_float_i : std_logic_vector(3 downto 0);
180  signal rxdisperr_float_i : std_logic_vector(3 downto 0);
181  signal rxnotintable_float_i : std_logic_vector(3 downto 0);
182  signal rxrundisp_float_i : std_logic_vector(3 downto 0);
183 
184 
185 
186  -- TX Datapath signals
187  signal txdata_i : std_logic_vector(63 downto 0);
188  signal txkerr_float_i : std_logic_vector(3 downto 0);
189  signal txrundisp_float_i : std_logic_vector(3 downto 0);
190  signal rxstartofseq_float_i : std_logic;
191 
192 --******************************** Main Body of Code***************************
193 
194 begin
195 
196  --------------------------- Static signal Assignments ---------------------
197 
198  tied_to_ground_i <= '0';
199  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
200  tied_to_vcc_i <= '1';
201 
202  ------------------- GT Datapath byte mapping -----------------
203 
204  -- The GT provides little endian data (first byte received on RXDATA(7 downto 0))
205  RXDATA_OUT <= rxdata_i(31 downto 0);
206 
207  txdata_i <= (tied_to_ground_vec_i(31 downto 0) & TXDATA_IN);
208 
209 
210 
211  ----------------------------- GTXE2 Instance --------------------------
212 
213  gtxe2_i :GTXE2_CHANNEL
214  generic map
215  (
216 
217  --_______________________ Simulation-Only Attributes ___________________
218 
219  SIM_RECEIVER_DETECT_PASS => ("TRUE"),
220  SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP),
221  SIM_TX_EIDLE_DRIVE_LEVEL => ("X"),
222  SIM_CPLLREFCLK_SEL => ("001"),
223  SIM_VERSION => ("4.0"),
224 
225 
226  ------------------RX Byte and Word Alignment Attributes---------------
227  ALIGN_COMMA_DOUBLE => ("FALSE"),
228  ALIGN_COMMA_ENABLE => ("1111111111"),
229  ALIGN_COMMA_WORD => (4),
230  ALIGN_MCOMMA_DET => ("TRUE"),
231  ALIGN_MCOMMA_VALUE => ("1010000011"),
232  ALIGN_PCOMMA_DET => ("TRUE"),
233  ALIGN_PCOMMA_VALUE => ("0101111100"),
234  SHOW_REALIGN_COMMA => ("TRUE"),
235  RXSLIDE_AUTO_WAIT => (7),
236  RXSLIDE_MODE => ("OFF"),
237  RX_SIG_VALID_DLY => (10),
238 
239  ------------------RX 8B/10B Decoder Attributes---------------
240  RX_DISPERR_SEQ_MATCH => ("TRUE"),
241  DEC_MCOMMA_DETECT => ("TRUE"),
242  DEC_PCOMMA_DETECT => ("TRUE"),
243  DEC_VALID_COMMA_ONLY => ("FALSE"),
244 
245  ------------------------RX Clock Correction Attributes----------------------
246  CBCC_DATA_SOURCE_SEL => ("DECODED"),
247  CLK_COR_SEQ_2_USE => ("FALSE"),
248  CLK_COR_KEEP_IDLE => ("FALSE"),
249  CLK_COR_MAX_LAT => (20),
250  CLK_COR_MIN_LAT => (16),
251  CLK_COR_PRECEDENCE => ("TRUE"),
252  CLK_COR_REPEAT_WAIT => (0),
253  CLK_COR_SEQ_LEN => (1),
254  CLK_COR_SEQ_1_ENABLE => ("1111"),
255  CLK_COR_SEQ_1_1 => ("0100000000"),
256  CLK_COR_SEQ_1_2 => ("0000000000"),
257  CLK_COR_SEQ_1_3 => ("0000000000"),
258  CLK_COR_SEQ_1_4 => ("0000000000"),
259  CLK_CORRECT_USE => ("FALSE"),
260  CLK_COR_SEQ_2_ENABLE => ("1111"),
261  CLK_COR_SEQ_2_1 => ("0100000000"),
262  CLK_COR_SEQ_2_2 => ("0000000000"),
263  CLK_COR_SEQ_2_3 => ("0000000000"),
264  CLK_COR_SEQ_2_4 => ("0000000000"),
265 
266  ------------------------RX Channel Bonding Attributes----------------------
267  CHAN_BOND_KEEP_ALIGN => ("FALSE"),
268  CHAN_BOND_MAX_SKEW => (1),
269  CHAN_BOND_SEQ_LEN => (1),
270  CHAN_BOND_SEQ_1_1 => ("0000000000"),
271  CHAN_BOND_SEQ_1_2 => ("0000000000"),
272  CHAN_BOND_SEQ_1_3 => ("0000000000"),
273  CHAN_BOND_SEQ_1_4 => ("0000000000"),
274  CHAN_BOND_SEQ_1_ENABLE => ("1111"),
275  CHAN_BOND_SEQ_2_1 => ("0000000000"),
276  CHAN_BOND_SEQ_2_2 => ("0000000000"),
277  CHAN_BOND_SEQ_2_3 => ("0000000000"),
278  CHAN_BOND_SEQ_2_4 => ("0000000000"),
279  CHAN_BOND_SEQ_2_ENABLE => ("1111"),
280  CHAN_BOND_SEQ_2_USE => ("FALSE"),
281  FTS_DESKEW_SEQ_ENABLE => ("1111"),
282  FTS_LANE_DESKEW_CFG => ("1111"),
283  FTS_LANE_DESKEW_EN => ("FALSE"),
284 
285  ---------------------------RX Margin Analysis Attributes----------------------------
286  ES_CONTROL => ("000000"),
287  ES_ERRDET_EN => ("FALSE"),
288  ES_EYE_SCAN_EN => ("TRUE"),
289  ES_HORZ_OFFSET => (x"000"),
290  ES_PMA_CFG => ("0000000000"),
291  ES_PRESCALE => ("00000"),
292  ES_QUALIFIER => (x"00000000000000000000"),
293  ES_QUAL_MASK => (x"00000000000000000000"),
294  ES_SDATA_MASK => (x"00000000000000000000"),
295  ES_VERT_OFFSET => ("000000000"),
296 
297  -------------------------FPGA RX Interface Attributes-------------------------
298  RX_DATA_WIDTH => (40),
299 
300  ---------------------------PMA Attributes----------------------------
301  OUTREFCLK_SEL_INV => ("11"),
302  PMA_RSV => (PMA_RSV_IN),
303  PMA_RSV2 => (x"2040"),
304  PMA_RSV3 => ("00"),
305  PMA_RSV4 => (x"00000000"),
306  RX_BIAS_CFG => ("000000000100"),
307  DMONITOR_CFG => (x"000A00"),
308  RX_CM_SEL => ("00"),
309  RX_CM_TRIM => ("000"),
310  RX_DEBUG_CFG => ("000000000000"),
311  RX_OS_CFG => ("0000010000000"),
312  TERM_RCAL_CFG => ("10000"),
313  TERM_RCAL_OVRD => ('0'),
314  TST_RSV => (x"00000000"),
315  RX_CLK25_DIV => (7),
316  TX_CLK25_DIV => (7),
317  UCODEER_CLR => ('0'),
318 
319  ---------------------------PCI Express Attributes----------------------------
320  PCS_PCIE_EN => ("FALSE"),
321 
322  ---------------------------PCS Attributes----------------------------
323  PCS_RSVD_ATTR => (PCS_RSVD_ATTR_IN),
324 
325  -------------RX Buffer Attributes------------
326  RXBUF_ADDR_MODE => ("FAST"),
327  RXBUF_EIDLE_HI_CNT => ("1000"),
328  RXBUF_EIDLE_LO_CNT => ("0000"),
329  RXBUF_EN => ("TRUE"),
330  RX_BUFFER_CFG => ("000000"),
331  RXBUF_RESET_ON_CB_CHANGE => ("TRUE"),
332  RXBUF_RESET_ON_COMMAALIGN => ("FALSE"),
333  RXBUF_RESET_ON_EIDLE => ("FALSE"),
334  RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
335  RXBUFRESET_TIME => ("00001"),
336  RXBUF_THRESH_OVFLW => (61),
337  RXBUF_THRESH_OVRD => ("FALSE"),
338  RXBUF_THRESH_UNDFLW => (4),
339  RXDLY_CFG => (x"001F"),
340  RXDLY_LCFG => (x"030"),
341  RXDLY_TAP_CFG => (x"0000"),
342  RXPH_CFG => (x"000000"),
343  RXPHDLY_CFG => (x"084020"),
344  RXPH_MONITOR_SEL => ("00000"),
345  RX_XCLK_SEL => ("RXREC"),
346  RX_DDI_SEL => ("000000"),
347  RX_DEFER_RESET_BUF_EN => ("TRUE"),
348 
349  -----------------------CDR Attributes-------------------------
350 
351  --For GTX only: Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
352 
353  --For GTX only: Display Port, HBR2 - set RXCDR_CFG=72'h038C008bff20200010
354  RXCDR_CFG => (x"03000023ff10200020"),
355  RXCDR_FR_RESET_ON_EIDLE => ('0'),
356  RXCDR_HOLD_DURING_EIDLE => ('0'),
357  RXCDR_PH_RESET_ON_EIDLE => ('0'),
358  RXCDR_LOCK_CFG => ("010101"),
359 
360  -------------------RX Initialization and Reset Attributes-------------------
361  RXCDRFREQRESET_TIME => ("00001"),
362  RXCDRPHRESET_TIME => ("00001"),
363  RXISCANRESET_TIME => ("00001"),
364  RXPCSRESET_TIME => ("00001"),
365  RXPMARESET_TIME => ("00011"),
366 
367  -------------------RX OOB Signaling Attributes-------------------
368  RXOOB_CFG => ("0000110"),
369 
370  -------------------------RX Gearbox Attributes---------------------------
371  RXGEARBOX_EN => ("FALSE"),
372  GEARBOX_MODE => ("000"),
373 
374  -------------------------PRBS Detection Attribute-----------------------
375  RXPRBS_ERR_LOOPBACK => ('0'),
376 
377  -------------Power-Down Attributes----------
378  PD_TRANS_TIME_FROM_P2 => (x"03c"),
379  PD_TRANS_TIME_NONE_P2 => (x"3c"),
380  PD_TRANS_TIME_TO_P2 => (x"64"),
381 
382  -------------RX OOB Signaling Attributes----------
383  SAS_MAX_COM => (64),
384  SAS_MIN_COM => (36),
385  SATA_BURST_SEQ_LEN => ("1111"),
386  SATA_BURST_VAL => ("100"),
387  SATA_EIDLE_VAL => ("100"),
388  SATA_MAX_BURST => (8),
389  SATA_MAX_INIT => (21),
390  SATA_MAX_WAKE => (7),
391  SATA_MIN_BURST => (4),
392  SATA_MIN_INIT => (12),
393  SATA_MIN_WAKE => (4),
394 
395  -------------RX Fabric Clock Output Control Attributes----------
396  TRANS_TIME_RATE => (x"0E"),
397 
398  --------------TX Buffer Attributes----------------
399  TXBUF_EN => ("TRUE"),
400  TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
401  TXDLY_CFG => (x"001F"),
402  TXDLY_LCFG => (x"030"),
403  TXDLY_TAP_CFG => (x"0000"),
404  TXPH_CFG => (x"0780"),
405  TXPHDLY_CFG => (x"084020"),
406  TXPH_MONITOR_SEL => ("00000"),
407  TX_XCLK_SEL => ("TXOUT"),
408 
409  -------------------------FPGA TX Interface Attributes-------------------------
410  TX_DATA_WIDTH => (40),
411 
412  -------------------------TX Configurable Driver Attributes-------------------------
413  TX_DEEMPH0 => ("00000"),
414  TX_DEEMPH1 => ("00000"),
415  TX_EIDLE_ASSERT_DELAY => ("110"),
416  TX_EIDLE_DEASSERT_DELAY => ("100"),
417  TX_LOOPBACK_DRIVE_HIZ => ("FALSE"),
418  TX_MAINCURSOR_SEL => ('0'),
419  TX_DRIVE_MODE => ("DIRECT"),
420  TX_MARGIN_FULL_0 => ("1001110"),
421  TX_MARGIN_FULL_1 => ("1001001"),
422  TX_MARGIN_FULL_2 => ("1000101"),
423  TX_MARGIN_FULL_3 => ("1000010"),
424  TX_MARGIN_FULL_4 => ("1000000"),
425  TX_MARGIN_LOW_0 => ("1000110"),
426  TX_MARGIN_LOW_1 => ("1000100"),
427  TX_MARGIN_LOW_2 => ("1000010"),
428  TX_MARGIN_LOW_3 => ("1000000"),
429  TX_MARGIN_LOW_4 => ("1000000"),
430 
431  -------------------------TX Gearbox Attributes--------------------------
432  TXGEARBOX_EN => ("FALSE"),
433 
434  -------------------------TX Initialization and Reset Attributes--------------------------
435  TXPCSRESET_TIME => ("00001"),
436  TXPMARESET_TIME => ("00001"),
437 
438  -------------------------TX Receiver Detection Attributes--------------------------
439  TX_RXDETECT_CFG => (x"1832"),
440  TX_RXDETECT_REF => ("100"),
441 
442  ----------------------------CPLL Attributes----------------------------
443  CPLL_CFG => (x"BC07DC"),
444  CPLL_FBDIV => (2),
445  CPLL_FBDIV_45 => (5),
446  CPLL_INIT_CFG => (x"00001E"),
447  CPLL_LOCK_CFG => (x"01E8"),
448  CPLL_REFCLK_DIV => (1),
449  RXOUT_DIV => (2),
450  TXOUT_DIV => (2),
451  SATA_CPLL_CFG => ("VCO_3000MHZ"),
452 
453  --------------RX Initialization and Reset Attributes-------------
454  RXDFELPMRESET_TIME => ("0001111"),
455 
456  --------------RX Equalizer Attributes-------------
457  RXLPM_HF_CFG => ("00000011110000"),
458  RXLPM_LF_CFG => ("00000011110000"),
459  RX_DFE_GAIN_CFG => (x"020FEA"),
460  RX_DFE_H2_CFG => ("000000000000"),
461  RX_DFE_H3_CFG => ("000001000000"),
462  RX_DFE_H4_CFG => ("00011110000"),
463  RX_DFE_H5_CFG => ("00011100000"),
464  RX_DFE_KL_CFG => ("0000011111110"),
465  RX_DFE_LPM_CFG => (x"0904"),
466  RX_DFE_LPM_HOLD_DURING_EIDLE => ('0'),
467  RX_DFE_UT_CFG => ("10001111000000000"),
468  RX_DFE_VP_CFG => ("00011111100000011"),
469 
470  -------------------------Power-Down Attributes-------------------------
471  RX_CLKMUX_PD => ('1'),
472  TX_CLKMUX_PD => ('1'),
473 
474  -------------------------FPGA RX Interface Attribute-------------------------
475  RX_INT_DATAWIDTH => (1),
476 
477  -------------------------FPGA TX Interface Attribute-------------------------
478  TX_INT_DATAWIDTH => (1),
479 
480  ------------------TX Configurable Driver Attributes---------------
481  TX_QPI_STATUS_EN => ('0'),
482 
483  -------------------------RX Equalizer Attributes--------------------------
484  RX_DFE_KL_CFG2 => (RX_DFE_KL_CFG2_IN),
485  RX_DFE_XYD_CFG => ("0000000000000"),
486 
487  -------------------------TX Configurable Driver Attributes--------------------------
488  TX_PREDRIVER_MODE => ('0')
489 
490 
491  )
492  port map
493  (
494  --------------------------------- CPLL Ports -------------------------------
495  CPLLFBCLKLOST => CPLLFBCLKLOST_OUT,
496  CPLLLOCK => CPLLLOCK_OUT,
497  CPLLLOCKDETCLK => CPLLLOCKDETCLK_IN,
498  CPLLLOCKEN => tied_to_vcc_i,
499  CPLLPD => tied_to_ground_i,
500  CPLLREFCLKLOST => CPLLREFCLKLOST_OUT,
501  CPLLREFCLKSEL => "001",
502  CPLLRESET => CPLLRESET_IN,
503  GTRSVD => "0000000000000000",
504  PCSRSVDIN => "0000000000000000",
505  PCSRSVDIN2 => "00000",
506  PMARSVDIN => "00000",
507  PMARSVDIN2 => "00000",
508  TSTIN => "11111111111111111111" ,
509  TSTOUT => open,
510  ---------------------------------- Channel ---------------------------------
511  CLKRSVD => "0000",
512  -------------------------- Channel - Clocking Ports ------------------------
513  GTGREFCLK => tied_to_ground_i,
514  GTNORTHREFCLK0 => tied_to_ground_i,
515  GTNORTHREFCLK1 => tied_to_ground_i,
516  GTREFCLK0 => GTREFCLK0_IN,
517  GTREFCLK1 => tied_to_ground_i,
518  GTSOUTHREFCLK0 => tied_to_ground_i,
519  GTSOUTHREFCLK1 => tied_to_ground_i,
520  ---------------------------- Channel - DRP Ports --------------------------
521  DRPADDR => DRPADDR_IN,
522  DRPCLK => DRPCLK_IN ,
523  DRPDI => DRPDI_IN,
524  DRPDO => DRPDO_OUT ,
525  DRPEN => DRPEN_IN,
526  DRPRDY => DRPRDY_OUT,
527  DRPWE => DRPWE_IN,
528  ------------------------------- Clocking Ports -----------------------------
529  GTREFCLKMONITOR => open,
530  QPLLCLK => QPLLCLK_IN,
531  QPLLREFCLK => QPLLREFCLK_IN,
532  RXSYSCLKSEL => "00",
533  TXSYSCLKSEL => "00",
534  --------------------------- Digital Monitor Ports --------------------------
535  DMONITOROUT => open,
536  ----------------- FPGA TX Interface Datapath Configuration ----------------
537  TX8B10BEN => tied_to_vcc_i,
538  ------------------------------- Loopback Ports -----------------------------
539  LOOPBACK => tied_to_ground_vec_i (2 downto 0),
540  ----------------------------- PCI Express Ports ----------------------------
541  PHYSTATUS => open,
542  RXRATE => tied_to_ground_vec_i (2 downto 0),
543  RXVALID => open,
544  ------------------------------ Power-Down Ports ----------------------------
545  RXPD => "00",
546  TXPD => "00",
547  -------------------------- RX 8B/10B Decoder Ports -------------------------
548  SETERRSTATUS => tied_to_ground_i,
549  --------------------- RX Initialization and Reset Ports --------------------
550  EYESCANRESET => tied_to_ground_i,
551  RXUSERRDY => RXUSERRDY_IN,
552  -------------------------- RX Margin Analysis Ports ------------------------
553  EYESCANDATAERROR => EYESCANDATAERROR_OUT ,
554  EYESCANMODE => tied_to_ground_i,
555  EYESCANTRIGGER => tied_to_ground_i,
556  ------------------------- Receive Ports - CDR Ports ------------------------
557  RXCDRFREQRESET => tied_to_ground_i,
558  RXCDRHOLD => tied_to_ground_i,
559  RXCDRLOCK => RXCDRLOCK_OUT,
560  RXCDROVRDEN => tied_to_ground_i,
561  RXCDRRESET => tied_to_ground_i,
562  RXCDRRESETRSV => tied_to_ground_i,
563  ------------------- Receive Ports - Clock Correction Ports -----------------
564  RXCLKCORCNT => open,
565  ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
566  RX8B10BEN => tied_to_vcc_i,
567  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
568  RXUSRCLK => RXUSRCLK_IN,
569  RXUSRCLK2 => RXUSRCLK2_IN,
570  ------------------ Receive Ports - FPGA RX interface Ports -----------------
571  RXDATA => rxdata_i,
572  ------------------- Receive Ports - Pattern Checker Ports ------------------
573  RXPRBSERR => RXPRBSERR_OUT,
574  RXPRBSSEL => RXPRBSSEL_IN,
575  ------------------- Receive Ports - Pattern Checker ports ------------------
576  RXPRBSCNTRESET => RXPRBSCNTRESET_IN,
577  -------------------- Receive Ports - RX Equalizer Ports -------------------
578  RXDFEXYDEN => tied_to_vcc_i,
579  RXDFEXYDHOLD => tied_to_ground_i,
580  RXDFEXYDOVRDEN => tied_to_ground_i,
581  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
582  RXDISPERR(7 downto 4) => rxdisperr_float_i,
583  RXDISPERR(3 downto 0) => RXDISPERR_OUT,
584  RXNOTINTABLE(7 downto 4) => rxnotintable_float_i,
585  RXNOTINTABLE(3 downto 0) => RXNOTINTABLE_OUT,
586  --------------------------- Receive Ports - RX AFE -------------------------
587  GTXRXP => GTXRXP_IN ,
588  ------------------------ Receive Ports - RX AFE Ports ----------------------
589  GTXRXN => GTXRXN_IN ,
590  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
591  RXBUFRESET => tied_to_ground_i,
592  RXBUFSTATUS => open,
593  RXDDIEN => tied_to_ground_i,
594  RXDLYBYPASS => tied_to_vcc_i,
595  RXDLYEN => tied_to_ground_i,
596  RXDLYOVRDEN => tied_to_ground_i,
597  RXDLYSRESET => tied_to_ground_i,
598  RXDLYSRESETDONE => open,
599  RXPHALIGN => tied_to_ground_i,
600  RXPHALIGNDONE => open,
601  RXPHALIGNEN => tied_to_ground_i,
602  RXPHDLYPD => tied_to_ground_i,
603  RXPHDLYRESET => tied_to_ground_i,
604  RXPHMONITOR => open,
605  RXPHOVRDEN => tied_to_ground_i,
606  RXPHSLIPMONITOR => open,
607  RXSTATUS => open,
608  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
609  RXBYTEISALIGNED => open,
610  RXBYTEREALIGN => open,
611  RXCOMMADET => open,
612  RXCOMMADETEN => tied_to_vcc_i,
613  RXMCOMMAALIGNEN => tied_to_vcc_i,
614  RXPCOMMAALIGNEN => tied_to_vcc_i,
615  ------------------ Receive Ports - RX Channel Bonding Ports ----------------
616  RXCHANBONDSEQ => open,
617  RXCHBONDEN => tied_to_ground_i,
618  RXCHBONDLEVEL => tied_to_ground_vec_i (2 downto 0),
619  RXCHBONDMASTER => tied_to_ground_i,
620  RXCHBONDO => open,
621  RXCHBONDSLAVE => tied_to_ground_i,
622  ----------------- Receive Ports - RX Channel Bonding Ports ----------------
623  RXCHANISALIGNED => open,
624  RXCHANREALIGN => open,
625  -------------------- Receive Ports - RX Equailizer Ports -------------------
626  RXLPMHFHOLD => RXLPMHFHOLD_IN,
627  RXLPMHFOVRDEN => tied_to_ground_i,
628  RXLPMLFHOLD => RXLPMLFHOLD_IN,
629  --------------------- Receive Ports - RX Equalizer Ports -------------------
630  RXDFEAGCHOLD => tied_to_ground_i,
631  RXDFEAGCOVRDEN => tied_to_ground_i,
632  RXDFECM1EN => tied_to_ground_i,
633  RXDFELFHOLD => tied_to_ground_i,
634  RXDFELFOVRDEN => tied_to_ground_i,
635  RXDFELPMRESET => tied_to_ground_i,
636  RXDFETAP2HOLD => tied_to_ground_i,
637  RXDFETAP2OVRDEN => tied_to_ground_i,
638  RXDFETAP3HOLD => tied_to_ground_i,
639  RXDFETAP3OVRDEN => tied_to_ground_i,
640  RXDFETAP4HOLD => tied_to_ground_i,
641  RXDFETAP4OVRDEN => tied_to_ground_i,
642  RXDFETAP5HOLD => tied_to_ground_i,
643  RXDFETAP5OVRDEN => tied_to_ground_i,
644  RXDFEUTHOLD => tied_to_ground_i,
645  RXDFEUTOVRDEN => tied_to_ground_i,
646  RXDFEVPHOLD => tied_to_ground_i,
647  RXDFEVPOVRDEN => tied_to_ground_i,
648  RXDFEVSEN => tied_to_ground_i,
649  RXLPMLFKLOVRDEN => tied_to_ground_i,
650  RXMONITOROUT => open,
651  RXMONITORSEL => "00",
652  RXOSHOLD => tied_to_ground_i,
653  RXOSOVRDEN => tied_to_ground_i,
654  ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
655  RXRATEDONE => open,
656  --------------- Receive Ports - RX Fabric Output Control Ports -------------
657  RXOUTCLK => RXOUTCLK_OUT,
658  RXOUTCLKFABRIC => open,
659  RXOUTCLKPCS => open,
660  RXOUTCLKSEL => "010",
661  ---------------------- Receive Ports - RX Gearbox Ports --------------------
662  RXDATAVALID => open,
663  RXHEADER => open,
664  RXHEADERVALID => open,
665  RXSTARTOFSEQ => open,
666  --------------------- Receive Ports - RX Gearbox Ports --------------------
667  RXGEARBOXSLIP => tied_to_ground_i,
668  ------------- Receive Ports - RX Initialization and Reset Ports ------------
669  GTRXRESET => GTRXRESET_IN,
670  RXOOBRESET => tied_to_ground_i,
671  RXPCSRESET => tied_to_ground_i,
672  RXPMARESET => RXPMARESET_IN,
673  ------------------ Receive Ports - RX Margin Analysis ports ----------------
674  RXLPMEN => tied_to_vcc_i,
675  ------------------- Receive Ports - RX OOB Signaling ports -----------------
676  RXCOMSASDET => open,
677  RXCOMWAKEDET => open,
678  ------------------ Receive Ports - RX OOB Signaling ports -----------------
679  RXCOMINITDET => open,
680  ------------------ Receive Ports - RX OOB signalling Ports -----------------
681  RXELECIDLE => open,
682  RXELECIDLEMODE => "11",
683  ----------------- Receive Ports - RX Polarity Control Ports ----------------
684  RXPOLARITY => tied_to_ground_i,
685  ---------------------- Receive Ports - RX gearbox ports --------------------
686  RXSLIDE => tied_to_ground_i,
687  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
688  RXCHARISCOMMA => open,
689  RXCHARISK(7 downto 4) => rxcharisk_float_i,
690  RXCHARISK(3 downto 0) => RXCHARISK_OUT,
691  ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
692  RXCHBONDI => "00000",
693  -------------- Receive Ports -RX Initialization and Reset Ports ------------
694  RXRESETDONE => RXRESETDONE_OUT,
695  -------------------------------- Rx AFE Ports ------------------------------
696  RXQPIEN => tied_to_ground_i,
697  RXQPISENN => open,
698  RXQPISENP => open,
699  --------------------------- TX Buffer Bypass Ports -------------------------
700  TXPHDLYTSTCLK => tied_to_ground_i,
701  ------------------------ TX Configurable Driver Ports ----------------------
702  TXPOSTCURSOR => "00000",
703  TXPOSTCURSORINV => tied_to_ground_i,
704  TXPRECURSOR => tied_to_ground_vec_i (4 downto 0),
705  TXPRECURSORINV => tied_to_ground_i,
706  TXQPIBIASEN => tied_to_ground_i,
707  TXQPISTRONGPDOWN => tied_to_ground_i,
708  TXQPIWEAKPUP => tied_to_ground_i,
709  --------------------- TX Initialization and Reset Ports --------------------
710  CFGRESET => tied_to_ground_i,
711  GTTXRESET => GTTXRESET_IN,
712  PCSRSVDOUT => open,
713  TXUSERRDY => TXUSERRDY_IN,
714  ---------------------- Transceiver Reset Mode Operation --------------------
715  GTRESETSEL => tied_to_ground_i,
716  RESETOVRD => tied_to_ground_i,
717  ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
718  TXCHARDISPMODE => tied_to_ground_vec_i (7 downto 0),
719  TXCHARDISPVAL => tied_to_ground_vec_i (7 downto 0),
720  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
721  TXUSRCLK => TXUSRCLK_IN,
722  TXUSRCLK2 => TXUSRCLK2_IN,
723  --------------------- Transmit Ports - PCI Express Ports -------------------
724  TXELECIDLE => tied_to_ground_i,
725  TXMARGIN => tied_to_ground_vec_i (2 downto 0),
726  TXRATE => tied_to_ground_vec_i (2 downto 0),
727  TXSWING => tied_to_ground_i,
728  ------------------ Transmit Ports - Pattern Generator Ports ----------------
729  TXPRBSFORCEERR => tied_to_ground_i,
730  ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
731  TXDLYBYPASS => tied_to_vcc_i,
732  TXDLYEN => tied_to_ground_i,
733  TXDLYHOLD => tied_to_ground_i,
734  TXDLYOVRDEN => tied_to_ground_i,
735  TXDLYSRESET => tied_to_ground_i,
736  TXDLYSRESETDONE => open,
737  TXDLYUPDOWN => tied_to_ground_i,
738  TXPHALIGN => tied_to_ground_i,
739  TXPHALIGNDONE => open,
740  TXPHALIGNEN => tied_to_ground_i,
741  TXPHDLYPD => tied_to_ground_i,
742  TXPHDLYRESET => tied_to_ground_i,
743  TXPHINIT => tied_to_ground_i,
744  TXPHINITDONE => open,
745  TXPHOVRDEN => tied_to_ground_i,
746  ---------------------- Transmit Ports - TX Buffer Ports --------------------
747  TXBUFSTATUS => open,
748  --------------- Transmit Ports - TX Configurable Driver Ports --------------
749  TXBUFDIFFCTRL => "100",
750  TXDEEMPH => tied_to_ground_i,
751  TXDIFFCTRL => "1000",
752  TXDIFFPD => tied_to_ground_i,
753  TXINHIBIT => tied_to_ground_i,
754  TXMAINCURSOR => "0000000" ,
755  TXPISOPD => tied_to_ground_i,
756  ------------------ Transmit Ports - TX Data Path interface -----------------
757  TXDATA => txdata_i,
758  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
759  GTXTXN => GTXTXN_OUT,
760  GTXTXP => GTXTXP_OUT,
761  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
762  TXOUTCLK => TXOUTCLK_OUT,
763  TXOUTCLKFABRIC => TXOUTCLKFABRIC_OUT ,
764  TXOUTCLKPCS => TXOUTCLKPCS_OUT,
765  TXOUTCLKSEL => "010",
766  TXRATEDONE => open,
767  --------------------- Transmit Ports - TX Gearbox Ports --------------------
768  TXCHARISK(7 downto 4) => tied_to_ground_vec_i (3 downto 0),
769  TXCHARISK(3 downto 0) => TXCHARISK_IN,
770  TXGEARBOXREADY => open,
771  TXHEADER => tied_to_ground_vec_i (2 downto 0),
772  TXSEQUENCE => tied_to_ground_vec_i (6 downto 0),
773  TXSTARTSEQ => tied_to_ground_i,
774  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
775  TXPCSRESET => tied_to_ground_i,
776  TXPMARESET => tied_to_ground_i,
777  TXRESETDONE => TXRESETDONE_OUT,
778  ------------------ Transmit Ports - TX OOB signalling Ports ----------------
779  TXCOMFINISH => open,
780  TXCOMINIT => tied_to_ground_i,
781  TXCOMSAS => tied_to_ground_i,
782  TXCOMWAKE => tied_to_ground_i,
783  TXPDELECIDLEMODE => tied_to_ground_i,
784  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
785  TXPOLARITY => tied_to_ground_i,
786  --------------- Transmit Ports - TX Receiver Detection Ports --------------
787  TXDETECTRX => tied_to_ground_i,
788  ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
789  TX8B10BBYPASS => tied_to_ground_vec_i (7 downto 0),
790  ------------------ Transmit Ports - pattern Generator Ports ----------------
791  TXPRBSSEL => TXPRBSSEL_IN,
792  ----------------------- Tx Configurable Driver Ports ----------------------
793  TXQPISENN => open,
794  TXQPISENP => open
795 
796  );
797 
798  end RTL;
799 
800 
801 
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