AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
uhtr_trig.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : uhtr_trig.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module uHTR_trig (a GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 library UNISIM;
68 use UNISIM.VCOMPONENTS.ALL;
69 
70 
71 --***************************** Entity Declaration ****************************
72 
73 entity uHTR_trig is
74 generic
75 (
76  QPLL_FBDIV_TOP : integer := 16;
77 
78  -- Simulation attributes
79  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
80  RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
81  PMA_RSV_IN : bit_vector := x"00018480"
82 
83 );
84 port
85 (
86  --_________________________________________________________________________
87  --_________________________________________________________________________
88  --GT0 (X0Y12)
89  --____________________________CHANNEL PORTS________________________________
90  --------------------------------- CPLL Ports -------------------------------
91  GT0_CPLLFBCLKLOST_OUT : out std_logic;
92  GT0_CPLLLOCK_OUT : out std_logic;
93  GT0_CPLLLOCKDETCLK_IN : in std_logic;
94  GT0_CPLLREFCLKLOST_OUT : out std_logic;
95  GT0_CPLLRESET_IN : in std_logic;
96  -------------------------- Channel - Clocking Ports ------------------------
97  GT0_GTREFCLK0_IN : in std_logic;
98  ---------------------------- Channel - DRP Ports --------------------------
99  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
100  GT0_DRPCLK_IN : in std_logic;
101  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
102  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
103  GT0_DRPEN_IN : in std_logic;
104  GT0_DRPRDY_OUT : out std_logic;
105  GT0_DRPWE_IN : in std_logic;
106  --------------------- RX Initialization and Reset Ports --------------------
107  GT0_RXUSERRDY_IN : in std_logic;
108  -------------------------- RX Margin Analysis Ports ------------------------
109  GT0_EYESCANDATAERROR_OUT : out std_logic;
110  ------------------------- Receive Ports - CDR Ports ------------------------
111  GT0_RXCDRLOCK_OUT : out std_logic;
112  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
113  GT0_RXUSRCLK_IN : in std_logic;
114  GT0_RXUSRCLK2_IN : in std_logic;
115  ------------------ Receive Ports - FPGA RX interface Ports -----------------
116  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
117  ------------------- Receive Ports - Pattern Checker Ports ------------------
118  GT0_RXPRBSERR_OUT : out std_logic;
119  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
120  ------------------- Receive Ports - Pattern Checker ports ------------------
121  GT0_RXPRBSCNTRESET_IN : in std_logic;
122  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
123  GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
124  GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
125  --------------------------- Receive Ports - RX AFE -------------------------
126  GT0_GTXRXP_IN : in std_logic;
127  ------------------------ Receive Ports - RX AFE Ports ----------------------
128  GT0_GTXRXN_IN : in std_logic;
129  -------------------- Receive Ports - RX Equailizer Ports -------------------
130  GT0_RXLPMHFHOLD_IN : in std_logic;
131  GT0_RXLPMLFHOLD_IN : in std_logic;
132  --------------- Receive Ports - RX Fabric Output Control Ports -------------
133  GT0_RXOUTCLK_OUT : out std_logic;
134  ------------- Receive Ports - RX Initialization and Reset Ports ------------
135  GT0_GTRXRESET_IN : in std_logic;
136  GT0_RXPMARESET_IN : in std_logic;
137  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
138  GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
139  -------------- Receive Ports -RX Initialization and Reset Ports ------------
140  GT0_RXRESETDONE_OUT : out std_logic;
141  --------------------- TX Initialization and Reset Ports --------------------
142  GT0_GTTXRESET_IN : in std_logic;
143  GT0_TXUSERRDY_IN : in std_logic;
144  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
145  GT0_TXUSRCLK_IN : in std_logic;
146  GT0_TXUSRCLK2_IN : in std_logic;
147  ------------------ Transmit Ports - TX Data Path interface -----------------
148  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
149  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
150  GT0_GTXTXN_OUT : out std_logic;
151  GT0_GTXTXP_OUT : out std_logic;
152  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
153  GT0_TXOUTCLK_OUT : out std_logic;
154  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
155  GT0_TXOUTCLKPCS_OUT : out std_logic;
156  --------------------- Transmit Ports - TX Gearbox Ports --------------------
157  GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
158  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
159  GT0_TXRESETDONE_OUT : out std_logic;
160  ------------------ Transmit Ports - pattern Generator Ports ----------------
161  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
162 
163 
164  --____________________________COMMON PORTS________________________________
165  ---------------------- Common Block - Ref Clock Ports ---------------------
166  GT0_GTREFCLK0_COMMON_IN : in std_logic;
167  ------------------------- Common Block - QPLL Ports ------------------------
168  GT0_QPLLLOCK_OUT : out std_logic;
169  GT0_QPLLLOCKDETCLK_IN : in std_logic;
170  GT0_QPLLREFCLKLOST_OUT : out std_logic;
171  GT0_QPLLRESET_IN : in std_logic
172 
173 
174 );
175 
176 
177 end uHTR_trig;
178 
179 architecture RTL of uHTR_trig is
180 
181  attribute CORE_GENERATION_INFO : string;
182  attribute CORE_GENERATION_INFO of RTL : architecture is "uHTR_trig,gtwizard_v2_7,{protocol_file=Start_from_scratch}";
183 
184 
185 --***********************************Parameter Declarations********************
186 
187  constant DLY : time := 1 ns;
188 
189 --***************************** Signal Declarations *****************************
190 
191  -- ground and tied_to_vcc_i signals
192  signal tied_to_ground_i : std_logic;
193  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
194  signal tied_to_vcc_i : std_logic;
195  signal gt0_qplloutclk_i : std_logic;
196  signal gt0_qplloutrefclk_i : std_logic;
197 
198 
199  signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0);
200  signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0);
201 
202 
203  signal gt0_qpllclk_i : std_logic;
204  signal gt0_qpllrefclk_i : std_logic;
205 
206 
207 --*************************** Component Declarations **************************
208 component uHTR_trig_GT
209 generic
210 (
211  -- Simulation attributes
212  GT_SIM_GTRESET_SPEEDUP : string := "FALSE";
213  RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
214  PMA_RSV_IN : bit_vector := X"00000000";
215  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
216 );
217 port
218 (
219  --------------------------------- CPLL Ports -------------------------------
220  CPLLFBCLKLOST_OUT : out std_logic;
221  CPLLLOCK_OUT : out std_logic;
222  CPLLLOCKDETCLK_IN : in std_logic;
223  CPLLREFCLKLOST_OUT : out std_logic;
224  CPLLRESET_IN : in std_logic;
225  -------------------------- Channel - Clocking Ports ------------------------
226  GTREFCLK0_IN : in std_logic;
227  ---------------------------- Channel - DRP Ports --------------------------
228  DRPADDR_IN : in std_logic_vector(8 downto 0);
229  DRPCLK_IN : in std_logic;
230  DRPDI_IN : in std_logic_vector(15 downto 0);
231  DRPDO_OUT : out std_logic_vector(15 downto 0);
232  DRPEN_IN : in std_logic;
233  DRPRDY_OUT : out std_logic;
234  DRPWE_IN : in std_logic;
235  ------------------------------- Clocking Ports -----------------------------
236  QPLLCLK_IN : in std_logic;
237  QPLLREFCLK_IN : in std_logic;
238  --------------------- RX Initialization and Reset Ports --------------------
239  RXUSERRDY_IN : in std_logic;
240  -------------------------- RX Margin Analysis Ports ------------------------
241  EYESCANDATAERROR_OUT : out std_logic;
242  ------------------------- Receive Ports - CDR Ports ------------------------
243  RXCDRLOCK_OUT : out std_logic;
244  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
245  RXUSRCLK_IN : in std_logic;
246  RXUSRCLK2_IN : in std_logic;
247  ------------------ Receive Ports - FPGA RX interface Ports -----------------
248  RXDATA_OUT : out std_logic_vector(31 downto 0);
249  ------------------- Receive Ports - Pattern Checker Ports ------------------
250  RXPRBSERR_OUT : out std_logic;
251  RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
252  ------------------- Receive Ports - Pattern Checker ports ------------------
253  RXPRBSCNTRESET_IN : in std_logic;
254  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
255  RXDISPERR_OUT : out std_logic_vector(3 downto 0);
256  RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
257  --------------------------- Receive Ports - RX AFE -------------------------
258  GTXRXP_IN : in std_logic;
259  ------------------------ Receive Ports - RX AFE Ports ----------------------
260  GTXRXN_IN : in std_logic;
261  -------------------- Receive Ports - RX Equailizer Ports -------------------
262  RXLPMHFHOLD_IN : in std_logic;
263  RXLPMLFHOLD_IN : in std_logic;
264  --------------- Receive Ports - RX Fabric Output Control Ports -------------
265  RXOUTCLK_OUT : out std_logic;
266  ------------- Receive Ports - RX Initialization and Reset Ports ------------
267  GTRXRESET_IN : in std_logic;
268  RXPMARESET_IN : in std_logic;
269  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
270  RXCHARISK_OUT : out std_logic_vector(3 downto 0);
271  -------------- Receive Ports -RX Initialization and Reset Ports ------------
272  RXRESETDONE_OUT : out std_logic;
273  --------------------- TX Initialization and Reset Ports --------------------
274  GTTXRESET_IN : in std_logic;
275  TXUSERRDY_IN : in std_logic;
276  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
277  TXUSRCLK_IN : in std_logic;
278  TXUSRCLK2_IN : in std_logic;
279  ------------------ Transmit Ports - TX Data Path interface -----------------
280  TXDATA_IN : in std_logic_vector(31 downto 0);
281  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
282  GTXTXN_OUT : out std_logic;
283  GTXTXP_OUT : out std_logic;
284  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
285  TXOUTCLK_OUT : out std_logic;
286  TXOUTCLKFABRIC_OUT : out std_logic;
287  TXOUTCLKPCS_OUT : out std_logic;
288  --------------------- Transmit Ports - TX Gearbox Ports --------------------
289  TXCHARISK_IN : in std_logic_vector(3 downto 0);
290  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
291  TXRESETDONE_OUT : out std_logic;
292  ------------------ Transmit Ports - pattern Generator Ports ----------------
293  TXPRBSSEL_IN : in std_logic_vector(2 downto 0)
294 
295 
296 );
297 end component;
298 
299 
300 
301 --*************************Logic to set Attribute QPLL_FB_DIV*****************************
302  impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
303  begin
304  if (qpllfbdiv_top = 16) then
305  return "0000100000";
306  elsif (qpllfbdiv_top = 20) then
307  return "0000110000" ;
308  elsif (qpllfbdiv_top = 32) then
309  return "0001100000" ;
310  elsif (qpllfbdiv_top = 40) then
311  return "0010000000" ;
312  elsif (qpllfbdiv_top = 64) then
313  return "0011100000" ;
314  elsif (qpllfbdiv_top = 66) then
315  return "0101000000" ;
316  elsif (qpllfbdiv_top = 80) then
317  return "0100100000" ;
318  elsif (qpllfbdiv_top = 100) then
319  return "0101110000" ;
320  else
321  return "0000000000" ;
322  end if;
323  end function;
324 
325  impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
326  begin
327  if (qpllfbdiv_top = 16) then
328  return '1';
329  elsif (qpllfbdiv_top = 20) then
330  return '1' ;
331  elsif (qpllfbdiv_top = 32) then
332  return '1' ;
333  elsif (qpllfbdiv_top = 40) then
334  return '1' ;
335  elsif (qpllfbdiv_top = 64) then
336  return '1' ;
337  elsif (qpllfbdiv_top = 66) then
338  return '0' ;
339  elsif (qpllfbdiv_top = 80) then
340  return '1' ;
341  elsif (qpllfbdiv_top = 100) then
342  return '1' ;
343  else
344  return '1' ;
345  end if;
346  end function;
347 
348  constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
349  constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
350 
351 --********************************* Main Body of Code**************************
352 
353 begin
354 
355  tied_to_ground_i <= '0';
356  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
357  tied_to_vcc_i <= '1';
358 -- gt0_qpllclk_i <= gt0_qplloutclk_i;
359 -- gt0_qpllrefclk_i <= gt0_qplloutrefclk_i;
360  gt0_qpllclk_i <= '0';
361  gt0_qpllrefclk_i <= '0';
362 
363 
364 
365  --------------------------- GT Instances -------------------------------
366 
367  --_________________________________________________________________________
368  --_________________________________________________________________________
369  --GT0 (X0Y12)
370 
371  gt0_uHTR_trig_i : uHTR_trig_GT
372  generic map
373  (
374  -- Simulation attributes
375  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
376  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
377  PMA_RSV_IN => PMA_RSV_IN,
378  PCS_RSVD_ATTR_IN => X"000000000000"
379  )
380  port map
381  (
382  --------------------------------- CPLL Ports -------------------------------
383  CPLLFBCLKLOST_OUT => GT0_CPLLFBCLKLOST_OUT ,
384  CPLLLOCK_OUT => GT0_CPLLLOCK_OUT,
385  CPLLLOCKDETCLK_IN => GT0_CPLLLOCKDETCLK_IN ,
386  CPLLREFCLKLOST_OUT => GT0_CPLLREFCLKLOST_OUT ,
387  CPLLRESET_IN => GT0_CPLLRESET_IN,
388  -------------------------- Channel - Clocking Ports ------------------------
389  GTREFCLK0_IN => GT0_GTREFCLK0_IN,
390  ---------------------------- Channel - DRP Ports --------------------------
391  DRPADDR_IN => GT0_DRPADDR_IN,
392  DRPCLK_IN => GT0_DRPCLK_IN,
393  DRPDI_IN => GT0_DRPDI_IN,
394  DRPDO_OUT => GT0_DRPDO_OUT,
395  DRPEN_IN => GT0_DRPEN_IN,
396  DRPRDY_OUT => GT0_DRPRDY_OUT,
397  DRPWE_IN => GT0_DRPWE_IN,
398  ------------------------------- Clocking Ports -----------------------------
399  QPLLCLK_IN => gt0_qpllclk_i,
400  QPLLREFCLK_IN => gt0_qpllrefclk_i,
401  --------------------- RX Initialization and Reset Ports --------------------
402  RXUSERRDY_IN => GT0_RXUSERRDY_IN,
403  -------------------------- RX Margin Analysis Ports ------------------------
404  EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
405  ------------------------- Receive Ports - CDR Ports ------------------------
406  RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
407  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
408  RXUSRCLK_IN => GT0_RXUSRCLK_IN,
409  RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
410  ------------------ Receive Ports - FPGA RX interface Ports -----------------
411  RXDATA_OUT => GT0_RXDATA_OUT,
412  ------------------- Receive Ports - Pattern Checker Ports ------------------
413  RXPRBSERR_OUT => GT0_RXPRBSERR_OUT,
414  RXPRBSSEL_IN => GT0_RXPRBSSEL_IN,
415  ------------------- Receive Ports - Pattern Checker ports ------------------
416  RXPRBSCNTRESET_IN => GT0_RXPRBSCNTRESET_IN ,
417  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
418  RXDISPERR_OUT => GT0_RXDISPERR_OUT,
419  RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT ,
420  --------------------------- Receive Ports - RX AFE -------------------------
421  GTXRXP_IN => GT0_GTXRXP_IN,
422  ------------------------ Receive Ports - RX AFE Ports ----------------------
423  GTXRXN_IN => GT0_GTXRXN_IN,
424  -------------------- Receive Ports - RX Equailizer Ports -------------------
425  RXLPMHFHOLD_IN => GT0_RXLPMHFHOLD_IN,
426  RXLPMLFHOLD_IN => GT0_RXLPMLFHOLD_IN ,
427  --------------- Receive Ports - RX Fabric Output Control Ports -------------
428  RXOUTCLK_OUT => GT0_RXOUTCLK_OUT,
429  ------------- Receive Ports - RX Initialization and Reset Ports ------------
430  GTRXRESET_IN => GT0_GTRXRESET_IN,
431  RXPMARESET_IN => GT0_RXPMARESET_IN,
432  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
433  RXCHARISK_OUT => GT0_RXCHARISK_OUT,
434  -------------- Receive Ports -RX Initialization and Reset Ports ------------
435  RXRESETDONE_OUT => GT0_RXRESETDONE_OUT ,
436  --------------------- TX Initialization and Reset Ports --------------------
437  GTTXRESET_IN => GT0_GTTXRESET_IN,
438  TXUSERRDY_IN => GT0_TXUSERRDY_IN,
439  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
440  TXUSRCLK_IN => GT0_TXUSRCLK_IN,
441  TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
442  ------------------ Transmit Ports - TX Data Path interface -----------------
443  TXDATA_IN => GT0_TXDATA_IN,
444  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
445  GTXTXN_OUT => GT0_GTXTXN_OUT,
446  GTXTXP_OUT => GT0_GTXTXP_OUT,
447  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
448  TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
449  TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT ,
450  TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT ,
451  --------------------- Transmit Ports - TX Gearbox Ports --------------------
452  TXCHARISK_IN => GT0_TXCHARISK_IN,
453  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
454  TXRESETDONE_OUT => GT0_TXRESETDONE_OUT ,
455  ------------------ Transmit Ports - pattern Generator Ports ----------------
456  TXPRBSSEL_IN => GT0_TXPRBSSEL_IN
457 
458  );
459 
460  --_________________________________________________________________________
461  --_________________________________________________________________________
462  --_________________________GTXE2_COMMON____________________________________
463 
464 -- gtxe2_common_0_i : GTXE2_COMMON
465 -- generic map
466 -- (
467 -- -- Simulation attributes
468 -- SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
469 -- SIM_QPLLREFCLK_SEL => ("001"),
470 -- SIM_VERSION => "4.0",
471 --
472 --
473 -- ------------------COMMON BLOCK Attributes---------------
474 -- BIAS_CFG => (x"0000040000001000"),
475 -- COMMON_CFG => (x"00000000"),
476 -- QPLL_CFG => (x"06801C1"),
477 -- QPLL_CLKOUT_CFG => ("0000"),
478 -- QPLL_COARSE_FREQ_OVRD => ("010000"),
479 -- QPLL_COARSE_FREQ_OVRD_EN => ('0'),
480 -- QPLL_CP => ("0000011111"),
481 -- QPLL_CP_MONITOR_EN => ('0'),
482 -- QPLL_DMONITOR_SEL => ('0'),
483 -- QPLL_FBDIV => (QPLL_FBDIV_IN),
484 -- QPLL_FBDIV_MONITOR_EN => ('0'),
485 -- QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
486 -- QPLL_INIT_CFG => (x"000006"),
487 -- QPLL_LOCK_CFG => (x"21E8"),
488 -- QPLL_LPF => ("1111"),
489 -- QPLL_REFCLK_DIV => (1)
490 --
491 --
492 -- )
493 -- port map
494 -- (
495 -- ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
496 -- DRPADDR => tied_to_ground_vec_i(7 downto 0),
497 -- DRPCLK => tied_to_ground_i,
498 -- DRPDI => tied_to_ground_vec_i(15 downto 0),
499 -- DRPDO => open,
500 -- DRPEN => tied_to_ground_i,
501 -- DRPRDY => open,
502 -- DRPWE => tied_to_ground_i,
503 -- ---------------------- Common Block - Ref Clock Ports ---------------------
504 -- GTGREFCLK => tied_to_ground_i,
505 -- GTNORTHREFCLK0 => tied_to_ground_i,
506 -- GTNORTHREFCLK1 => tied_to_ground_i,
507 -- GTREFCLK0 => GT0_GTREFCLK0_COMMON_IN,
508 -- GTREFCLK1 => tied_to_ground_i,
509 -- GTSOUTHREFCLK0 => tied_to_ground_i,
510 -- GTSOUTHREFCLK1 => tied_to_ground_i,
511 -- ------------------------- Common Block - QPLL Ports -----------------------
512 -- QPLLDMONITOR => open,
513 -- ----------------------- Common Block - Clocking Ports ----------------------
514 -- QPLLOUTCLK => gt0_qplloutclk_i,
515 -- QPLLOUTREFCLK => gt0_qplloutrefclk_i,
516 -- REFCLKOUTMONITOR => open,
517 -- ------------------------- Common Block - QPLL Ports ------------------------
518 -- QPLLFBCLKLOST => open,
519 -- QPLLLOCK => GT0_QPLLLOCK_OUT,
520 -- QPLLLOCKDETCLK => GT0_QPLLLOCKDETCLK_IN,
521 -- QPLLLOCKEN => tied_to_vcc_i,
522 -- QPLLOUTRESET => tied_to_ground_i,
523 -- QPLLPD => tied_to_vcc_i,
524 -- QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_OUT,
525 -- QPLLREFCLKSEL => "001",
526 -- QPLLRESET => GT0_QPLLRESET_IN,
527 -- QPLLRSVD1 => "0000000000000000",
528 -- QPLLRSVD2 => "11111",
529 -- --------------------------------- QPLL Ports -------------------------------
530 -- BGBYPASSB => tied_to_vcc_i,
531 -- BGMONITORENB => tied_to_vcc_i,
532 -- BGPDB => tied_to_vcc_i,
533 -- BGRCALOVRD => "00000",
534 -- PMARSVD => "00000000",
535 -- RCALENB => tied_to_vcc_i
536 --
537 -- );
538 
539 
540 
541 end RTL;
Generated on Wed Apr 18 2018 10:55:28 for AMC13 by   doxygen 1.8.1