AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
sfp3_v2_7_gt.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : sfp3_v2_7_gt.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module SFP3_v2_7_GT (a GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 library UNISIM;
68 use UNISIM.VCOMPONENTS.ALL;
69 
70 --***************************** Entity Declaration ****************************
71 
72 entity SFP3_v2_7_GT is
73 generic
74 (
75  -- Simulation attributes
76  GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
77  RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
78  PMA_RSV_IN : bit_vector := x"001E7080";
79  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
80 );
81 port
82 (
83  ---------------------------- Channel - DRP Ports --------------------------
84  DRPADDR_IN : in std_logic_vector(8 downto 0);
85  DRPCLK_IN : in std_logic;
86  DRPDI_IN : in std_logic_vector(15 downto 0);
87  DRPDO_OUT : out std_logic_vector(15 downto 0);
88  DRPEN_IN : in std_logic;
89  DRPRDY_OUT : out std_logic;
90  DRPWE_IN : in std_logic;
91  ------------------------------- Clocking Ports -----------------------------
92  QPLLCLK_IN : in std_logic;
93  QPLLREFCLK_IN : in std_logic;
94  ------------------------------- Loopback Ports -----------------------------
95  LOOPBACK_IN : in std_logic_vector(2 downto 0);
96  ------------------------------ Power-Down Ports ----------------------------
97  RXPD_IN : in std_logic_vector(1 downto 0);
98  TXPD_IN : in std_logic_vector(1 downto 0);
99  --------------------- RX Initialization and Reset Ports --------------------
100  RXUSERRDY_IN : in std_logic;
101  -------------------------- RX Margin Analysis Ports ------------------------
102  EYESCANDATAERROR_OUT : out std_logic;
103  ------------------------- Receive Ports - CDR Ports ------------------------
104  RXCDRLOCK_OUT : out std_logic;
105  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
106  RXUSRCLK_IN : in std_logic;
107  RXUSRCLK2_IN : in std_logic;
108  ------------------ Receive Ports - FPGA RX interface Ports -----------------
109  RXDATA_OUT : out std_logic_vector(31 downto 0);
110  ------------------- Receive Ports - Pattern Checker Ports ------------------
111  RXPRBSERR_OUT : out std_logic;
112  RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
113  ------------------- Receive Ports - Pattern Checker ports ------------------
114  RXPRBSCNTRESET_IN : in std_logic;
115  --------------------------- Receive Ports - RX AFE -------------------------
116  GTXRXP_IN : in std_logic;
117  ------------------------ Receive Ports - RX AFE Ports ----------------------
118  GTXRXN_IN : in std_logic;
119  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
120  RXBUFRESET_IN : in std_logic;
121  RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
122  --------------------- Receive Ports - RX Equalizer Ports -------------------
123  RXDFEAGCHOLD_IN : in std_logic;
124  RXDFELFHOLD_IN : in std_logic;
125  --------------- Receive Ports - RX Fabric Output Control Ports -------------
126  RXOUTCLK_OUT : out std_logic;
127  ---------------------- Receive Ports - RX Gearbox Ports --------------------
128  RXDATAVALID_OUT : out std_logic;
129  RXHEADER_OUT : out std_logic_vector(1 downto 0);
130  RXHEADERVALID_OUT : out std_logic;
131  --------------------- Receive Ports - RX Gearbox Ports --------------------
132  RXGEARBOXSLIP_IN : in std_logic;
133  ------------- Receive Ports - RX Initialization and Reset Ports ------------
134  GTRXRESET_IN : in std_logic;
135  RXPCSRESET_IN : in std_logic;
136  RXPMARESET_IN : in std_logic;
137  ------------------ Receive Ports - RX Margin Analysis ports ----------------
138  RXLPMEN_IN : in std_logic;
139  -------------- Receive Ports -RX Initialization and Reset Ports ------------
140  RXRESETDONE_OUT : out std_logic;
141  --------------------- TX Initialization and Reset Ports --------------------
142  GTTXRESET_IN : in std_logic;
143  TXUSERRDY_IN : in std_logic;
144  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
145  TXUSRCLK_IN : in std_logic;
146  TXUSRCLK2_IN : in std_logic;
147  --------------- Transmit Ports - TX Configurable Driver Ports --------------
148  TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
149  TXINHIBIT_IN : in std_logic;
150  TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
151  ------------------ Transmit Ports - TX Data Path interface -----------------
152  TXDATA_IN : in std_logic_vector(31 downto 0);
153  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
154  GTXTXN_OUT : out std_logic;
155  GTXTXP_OUT : out std_logic;
156  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
157  TXOUTCLK_OUT : out std_logic;
158  TXOUTCLKFABRIC_OUT : out std_logic;
159  TXOUTCLKPCS_OUT : out std_logic;
160  --------------------- Transmit Ports - TX Gearbox Ports --------------------
161  TXHEADER_IN : in std_logic_vector(1 downto 0);
162  TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
163  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
164  TXPCSRESET_IN : in std_logic;
165  TXRESETDONE_OUT : out std_logic;
166  ------------------ Transmit Ports - pattern Generator Ports ----------------
167  TXPRBSSEL_IN : in std_logic_vector(2 downto 0)
168 
169 
170 );
171 
172 
173 end SFP3_v2_7_GT;
174 
175 architecture RTL of SFP3_v2_7_GT is
176 
177 --**************************** Signal Declarations ****************************
178 
179  -- ground and tied_to_vcc_i signals
180  signal tied_to_ground_i : std_logic;
181  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
182  signal tied_to_vcc_i : std_logic;
183 
184 
185 
186  -- RX Datapath signals
187  signal rxdata_i : std_logic_vector(63 downto 0);
188  signal rxchariscomma_float_i : std_logic_vector(5 downto 0);
189  signal rxcharisk_float_i : std_logic_vector(5 downto 0);
190  signal rxdisperr_float_i : std_logic_vector(5 downto 0);
191  signal rxnotintable_float_i : std_logic_vector(5 downto 0);
192  signal rxrundisp_float_i : std_logic_vector(5 downto 0);
193  signal rxheader_float_i : std_logic;
194 
195 
196 
197  -- TX Datapath signals
198  signal txdata_i : std_logic_vector(63 downto 0);
199  signal txkerr_float_i : std_logic_vector(5 downto 0);
200  signal txrundisp_float_i : std_logic_vector(5 downto 0);
201  signal rxstartofseq_float_i : std_logic;
202 
203 --******************************** Main Body of Code***************************
204 
205 begin
206 
207  --------------------------- Static signal Assignments ---------------------
208 
209  tied_to_ground_i <= '0';
210  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
211  tied_to_vcc_i <= '1';
212 
213  ------------------- GT Datapath byte mapping -----------------
214 
215  --The GT deserializes the rightmost parallel bit (LSb) first
216  RXDATA_OUT <= rxdata_i(31 downto 0);
217 
218 
219  --The GT serializes the rightmost parallel bit (LSb) first
220  txdata_i <= (tied_to_ground_vec_i(31 downto 0) & TXDATA_IN);
221 
222 
223 
224  ----------------------------- GTXE2 Instance --------------------------
225 
226  gtxe2_i :GTXE2_CHANNEL
227  generic map
228  (
229 
230  --_______________________ Simulation-Only Attributes ___________________
231 
232  SIM_RECEIVER_DETECT_PASS => ("TRUE"),
233  SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP),
234  SIM_TX_EIDLE_DRIVE_LEVEL => ("X"),
235  SIM_CPLLREFCLK_SEL => ("001"),
236  SIM_VERSION => ("4.0"),
237 
238 
239  ------------------RX Byte and Word Alignment Attributes---------------
240  ALIGN_COMMA_DOUBLE => ("FALSE"),
241  ALIGN_COMMA_ENABLE => ("1111111111"),
242  ALIGN_COMMA_WORD => (1),
243  ALIGN_MCOMMA_DET => ("FALSE"),
244  ALIGN_MCOMMA_VALUE => ("1010000011"),
245  ALIGN_PCOMMA_DET => ("FALSE"),
246  ALIGN_PCOMMA_VALUE => ("0101111100"),
247  SHOW_REALIGN_COMMA => ("TRUE"),
248  RXSLIDE_AUTO_WAIT => (7),
249  RXSLIDE_MODE => ("OFF"),
250  RX_SIG_VALID_DLY => (10),
251 
252  ------------------RX 8B/10B Decoder Attributes---------------
253  RX_DISPERR_SEQ_MATCH => ("TRUE"),
254  DEC_MCOMMA_DETECT => ("FALSE"),
255  DEC_PCOMMA_DETECT => ("FALSE"),
256  DEC_VALID_COMMA_ONLY => ("FALSE"),
257 
258  ------------------------RX Clock Correction Attributes----------------------
259  CBCC_DATA_SOURCE_SEL => ("ENCODED"),
260  CLK_COR_SEQ_2_USE => ("FALSE"),
261  CLK_COR_KEEP_IDLE => ("FALSE"),
262  CLK_COR_MAX_LAT => (19),
263  CLK_COR_MIN_LAT => (15),
264  CLK_COR_PRECEDENCE => ("TRUE"),
265  CLK_COR_REPEAT_WAIT => (0),
266  CLK_COR_SEQ_LEN => (1),
267  CLK_COR_SEQ_1_ENABLE => ("1111"),
268  CLK_COR_SEQ_1_1 => ("0100000000"),
269  CLK_COR_SEQ_1_2 => ("0000000000"),
270  CLK_COR_SEQ_1_3 => ("0000000000"),
271  CLK_COR_SEQ_1_4 => ("0000000000"),
272  CLK_CORRECT_USE => ("FALSE"),
273  CLK_COR_SEQ_2_ENABLE => ("1111"),
274  CLK_COR_SEQ_2_1 => ("0100000000"),
275  CLK_COR_SEQ_2_2 => ("0000000000"),
276  CLK_COR_SEQ_2_3 => ("0000000000"),
277  CLK_COR_SEQ_2_4 => ("0000000000"),
278 
279  ------------------------RX Channel Bonding Attributes----------------------
280  CHAN_BOND_KEEP_ALIGN => ("FALSE"),
281  CHAN_BOND_MAX_SKEW => (1),
282  CHAN_BOND_SEQ_LEN => (1),
283  CHAN_BOND_SEQ_1_1 => ("0000000000"),
284  CHAN_BOND_SEQ_1_2 => ("0000000000"),
285  CHAN_BOND_SEQ_1_3 => ("0000000000"),
286  CHAN_BOND_SEQ_1_4 => ("0000000000"),
287  CHAN_BOND_SEQ_1_ENABLE => ("1111"),
288  CHAN_BOND_SEQ_2_1 => ("0000000000"),
289  CHAN_BOND_SEQ_2_2 => ("0000000000"),
290  CHAN_BOND_SEQ_2_3 => ("0000000000"),
291  CHAN_BOND_SEQ_2_4 => ("0000000000"),
292  CHAN_BOND_SEQ_2_ENABLE => ("1111"),
293  CHAN_BOND_SEQ_2_USE => ("FALSE"),
294  FTS_DESKEW_SEQ_ENABLE => ("1111"),
295  FTS_LANE_DESKEW_CFG => ("1111"),
296  FTS_LANE_DESKEW_EN => ("FALSE"),
297 
298  ---------------------------RX Margin Analysis Attributes----------------------------
299  ES_CONTROL => ("000000"),
300  ES_ERRDET_EN => ("FALSE"),
301  ES_EYE_SCAN_EN => ("TRUE"),
302  ES_HORZ_OFFSET => (x"000"),
303  ES_PMA_CFG => ("0000000000"),
304  ES_PRESCALE => ("00000"),
305  ES_QUALIFIER => (x"00000000000000000000"),
306  ES_QUAL_MASK => (x"00000000000000000000"),
307  ES_SDATA_MASK => (x"00000000000000000000"),
308  ES_VERT_OFFSET => ("000000000"),
309 
310  -------------------------FPGA RX Interface Attributes-------------------------
311  RX_DATA_WIDTH => (32),
312 
313  ---------------------------PMA Attributes----------------------------
314  OUTREFCLK_SEL_INV => ("11"),
315  PMA_RSV => (PMA_RSV_IN),
316  PMA_RSV2 => (x"2050"),
317  PMA_RSV3 => ("00"),
318  PMA_RSV4 => (x"00000000"),
319  RX_BIAS_CFG => ("000000000100"),
320  DMONITOR_CFG => (x"000A00"),
321  RX_CM_SEL => ("11"),
322  RX_CM_TRIM => ("010"),
323  RX_DEBUG_CFG => ("000000000000"),
324  RX_OS_CFG => ("0000010000000"),
325  TERM_RCAL_CFG => ("10000"),
326  TERM_RCAL_OVRD => ('0'),
327  TST_RSV => (x"00000000"),
328  RX_CLK25_DIV => (7),
329  TX_CLK25_DIV => (7),
330  UCODEER_CLR => ('0'),
331 
332  ---------------------------PCI Express Attributes----------------------------
333  PCS_PCIE_EN => ("FALSE"),
334 
335  ---------------------------PCS Attributes----------------------------
336  PCS_RSVD_ATTR => (PCS_RSVD_ATTR_IN),
337 
338  -------------RX Buffer Attributes------------
339  RXBUF_ADDR_MODE => ("FAST"),
340  RXBUF_EIDLE_HI_CNT => ("1000"),
341  RXBUF_EIDLE_LO_CNT => ("0000"),
342  RXBUF_EN => ("TRUE"),
343  RX_BUFFER_CFG => ("000000"),
344  RXBUF_RESET_ON_CB_CHANGE => ("TRUE"),
345  RXBUF_RESET_ON_COMMAALIGN => ("FALSE"),
346  RXBUF_RESET_ON_EIDLE => ("FALSE"),
347  RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
348  RXBUFRESET_TIME => ("00001"),
349  RXBUF_THRESH_OVFLW => (61),
350  RXBUF_THRESH_OVRD => ("FALSE"),
351  RXBUF_THRESH_UNDFLW => (4),
352  RXDLY_CFG => (x"001F"),
353  RXDLY_LCFG => (x"030"),
354  RXDLY_TAP_CFG => (x"0000"),
355  RXPH_CFG => (x"000000"),
356  RXPHDLY_CFG => (x"084020"),
357  RXPH_MONITOR_SEL => ("00000"),
358  RX_XCLK_SEL => ("RXREC"),
359  RX_DDI_SEL => ("000000"),
360  RX_DEFER_RESET_BUF_EN => ("TRUE"),
361 
362  -----------------------CDR Attributes-------------------------
363 
364  --For GTX only: Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
365 
366  --For GTX only: Display Port, HBR2 - set RXCDR_CFG=72'h038C008bff20200010
367  RXCDR_CFG => (x"0b000023ff10400020"),
368  RXCDR_FR_RESET_ON_EIDLE => ('0'),
369  RXCDR_HOLD_DURING_EIDLE => ('0'),
370  RXCDR_PH_RESET_ON_EIDLE => ('0'),
371  RXCDR_LOCK_CFG => ("010101"),
372 
373  -------------------RX Initialization and Reset Attributes-------------------
374  RXCDRFREQRESET_TIME => ("00001"),
375  RXCDRPHRESET_TIME => ("00001"),
376  RXISCANRESET_TIME => ("00001"),
377  RXPCSRESET_TIME => ("00001"),
378  RXPMARESET_TIME => ("00011"),
379 
380  -------------------RX OOB Signaling Attributes-------------------
381  RXOOB_CFG => ("0000110"),
382 
383  -------------------------RX Gearbox Attributes---------------------------
384  RXGEARBOX_EN => ("TRUE"),
385  GEARBOX_MODE => ("001"),
386 
387  -------------------------PRBS Detection Attribute-----------------------
388  RXPRBS_ERR_LOOPBACK => ('0'),
389 
390  -------------Power-Down Attributes----------
391  PD_TRANS_TIME_FROM_P2 => (x"03c"),
392  PD_TRANS_TIME_NONE_P2 => (x"19"),
393  PD_TRANS_TIME_TO_P2 => (x"64"),
394 
395  -------------RX OOB Signaling Attributes----------
396  SAS_MAX_COM => (64),
397  SAS_MIN_COM => (36),
398  SATA_BURST_SEQ_LEN => ("1111"),
399  SATA_BURST_VAL => ("100"),
400  SATA_EIDLE_VAL => ("100"),
401  SATA_MAX_BURST => (8),
402  SATA_MAX_INIT => (21),
403  SATA_MAX_WAKE => (7),
404  SATA_MIN_BURST => (4),
405  SATA_MIN_INIT => (12),
406  SATA_MIN_WAKE => (4),
407 
408  -------------RX Fabric Clock Output Control Attributes----------
409  TRANS_TIME_RATE => (x"0E"),
410 
411  --------------TX Buffer Attributes----------------
412  TXBUF_EN => ("TRUE"),
413  TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
414  TXDLY_CFG => (x"001F"),
415  TXDLY_LCFG => (x"030"),
416  TXDLY_TAP_CFG => (x"0000"),
417  TXPH_CFG => (x"0780"),
418  TXPHDLY_CFG => (x"084020"),
419  TXPH_MONITOR_SEL => ("00000"),
420  TX_XCLK_SEL => ("TXOUT"),
421 
422  -------------------------FPGA TX Interface Attributes-------------------------
423  TX_DATA_WIDTH => (32),
424 
425  -------------------------TX Configurable Driver Attributes-------------------------
426  TX_DEEMPH0 => ("00000"),
427  TX_DEEMPH1 => ("00000"),
428  TX_EIDLE_ASSERT_DELAY => ("110"),
429  TX_EIDLE_DEASSERT_DELAY => ("100"),
430  TX_LOOPBACK_DRIVE_HIZ => ("FALSE"),
431  TX_MAINCURSOR_SEL => ('0'),
432  TX_DRIVE_MODE => ("DIRECT"),
433  TX_MARGIN_FULL_0 => ("1001110"),
434  TX_MARGIN_FULL_1 => ("1001001"),
435  TX_MARGIN_FULL_2 => ("1000101"),
436  TX_MARGIN_FULL_3 => ("1000010"),
437  TX_MARGIN_FULL_4 => ("1000000"),
438  TX_MARGIN_LOW_0 => ("1000110"),
439  TX_MARGIN_LOW_1 => ("1000100"),
440  TX_MARGIN_LOW_2 => ("1000010"),
441  TX_MARGIN_LOW_3 => ("1000000"),
442  TX_MARGIN_LOW_4 => ("1000000"),
443 
444  -------------------------TX Gearbox Attributes--------------------------
445  TXGEARBOX_EN => ("TRUE"),
446 
447  -------------------------TX Initialization and Reset Attributes--------------------------
448  TXPCSRESET_TIME => ("00001"),
449  TXPMARESET_TIME => ("00001"),
450 
451  -------------------------TX Receiver Detection Attributes--------------------------
452  TX_RXDETECT_CFG => (x"1832"),
453  TX_RXDETECT_REF => ("100"),
454 
455  ----------------------------CPLL Attributes----------------------------
456  CPLL_CFG => (x"BC07DC"),
457  CPLL_FBDIV => (4),
458  CPLL_FBDIV_45 => (5),
459  CPLL_INIT_CFG => (x"00001E"),
460  CPLL_LOCK_CFG => (x"01E8"),
461  CPLL_REFCLK_DIV => (1),
462  RXOUT_DIV => (1),
463  TXOUT_DIV => (1),
464  SATA_CPLL_CFG => ("VCO_3000MHZ"),
465 
466  --------------RX Initialization and Reset Attributes-------------
467  RXDFELPMRESET_TIME => ("0001111"),
468 
469  --------------RX Equalizer Attributes-------------
470  RXLPM_HF_CFG => ("00000011110000"),
471  RXLPM_LF_CFG => ("00000011110000"),
472  RX_DFE_GAIN_CFG => (x"020FEA"),
473  RX_DFE_H2_CFG => ("000000000000"),
474  RX_DFE_H3_CFG => ("000001000000"),
475  RX_DFE_H4_CFG => ("00011110000"),
476  RX_DFE_H5_CFG => ("00011100000"),
477  RX_DFE_KL_CFG => ("0000011111110"),
478  RX_DFE_LPM_CFG => (x"0954"),
479  RX_DFE_LPM_HOLD_DURING_EIDLE => ('0'),
480  RX_DFE_UT_CFG => ("10001111000000000"),
481  RX_DFE_VP_CFG => ("00011111100000011"),
482 
483  -------------------------Power-Down Attributes-------------------------
484  RX_CLKMUX_PD => ('1'),
485  TX_CLKMUX_PD => ('1'),
486 
487  -------------------------FPGA RX Interface Attribute-------------------------
488  RX_INT_DATAWIDTH => (1),
489 
490  -------------------------FPGA TX Interface Attribute-------------------------
491  TX_INT_DATAWIDTH => (1),
492 
493  ------------------TX Configurable Driver Attributes---------------
494  TX_QPI_STATUS_EN => ('0'),
495 
496  -------------------------RX Equalizer Attributes--------------------------
497  RX_DFE_KL_CFG2 => (RX_DFE_KL_CFG2_IN),
498  RX_DFE_XYD_CFG => ("0000000000000"),
499 
500  -------------------------TX Configurable Driver Attributes--------------------------
501  TX_PREDRIVER_MODE => ('0')
502 
503 
504  )
505  port map
506  (
507  --------------------------------- CPLL Ports -------------------------------
508  CPLLFBCLKLOST => open,
509  CPLLLOCK => open,
510  CPLLLOCKDETCLK => tied_to_ground_i,
511  CPLLLOCKEN => tied_to_vcc_i,
512  CPLLPD => tied_to_vcc_i,
513  CPLLREFCLKLOST => open,
514  CPLLREFCLKSEL => "001",
515  CPLLRESET => tied_to_ground_i,
516  GTRSVD => "0000000000000000",
517  PCSRSVDIN => "0000000000000000" ,
518  PCSRSVDIN2 => "00000",
519  PMARSVDIN => "00000",
520  PMARSVDIN2 => "00000",
521  TSTIN => "11111111111111111111" ,
522  TSTOUT => open,
523  ---------------------------------- Channel ---------------------------------
524  CLKRSVD => "0000",
525  -------------------------- Channel - Clocking Ports ------------------------
526  GTGREFCLK => tied_to_ground_i,
527  GTNORTHREFCLK0 => tied_to_ground_i,
528  GTNORTHREFCLK1 => tied_to_ground_i,
529  GTREFCLK0 => tied_to_ground_i,
530  GTREFCLK1 => tied_to_ground_i,
531  GTSOUTHREFCLK0 => tied_to_ground_i,
532  GTSOUTHREFCLK1 => tied_to_ground_i,
533  ---------------------------- Channel - DRP Ports --------------------------
534  DRPADDR => DRPADDR_IN,
535  DRPCLK => DRPCLK_IN ,
536  DRPDI => DRPDI_IN,
537  DRPDO => DRPDO_OUT ,
538  DRPEN => DRPEN_IN,
539  DRPRDY => DRPRDY_OUT,
540  DRPWE => DRPWE_IN,
541  ------------------------------- Clocking Ports -----------------------------
542  GTREFCLKMONITOR => open,
543  QPLLCLK => QPLLCLK_IN,
544  QPLLREFCLK => QPLLREFCLK_IN,
545  RXSYSCLKSEL => "11",
546  TXSYSCLKSEL => "11",
547  --------------------------- Digital Monitor Ports --------------------------
548  DMONITOROUT => open,
549  ----------------- FPGA TX Interface Datapath Configuration ----------------
550  TX8B10BEN => tied_to_ground_i,
551  ------------------------------- Loopback Ports -----------------------------
552  LOOPBACK => LOOPBACK_IN,
553  ----------------------------- PCI Express Ports ----------------------------
554  PHYSTATUS => open,
555  RXRATE => tied_to_ground_vec_i (2 downto 0),
556  RXVALID => open,
557  ------------------------------ Power-Down Ports ----------------------------
558  RXPD => RXPD_IN,
559  TXPD => TXPD_IN,
560  -------------------------- RX 8B/10B Decoder Ports -------------------------
561  SETERRSTATUS => tied_to_ground_i,
562  --------------------- RX Initialization and Reset Ports --------------------
563  EYESCANRESET => tied_to_ground_i,
564  RXUSERRDY => RXUSERRDY_IN,
565  -------------------------- RX Margin Analysis Ports ------------------------
566  EYESCANDATAERROR => EYESCANDATAERROR_OUT ,
567  EYESCANMODE => tied_to_ground_i,
568  EYESCANTRIGGER => tied_to_ground_i,
569  ------------------------- Receive Ports - CDR Ports ------------------------
570  RXCDRFREQRESET => tied_to_ground_i,
571  RXCDRHOLD => tied_to_ground_i,
572  RXCDRLOCK => RXCDRLOCK_OUT,
573  RXCDROVRDEN => tied_to_ground_i,
574  RXCDRRESET => tied_to_ground_i,
575  RXCDRRESETRSV => tied_to_ground_i,
576  ------------------- Receive Ports - Clock Correction Ports -----------------
577  RXCLKCORCNT => open,
578  ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
579  RX8B10BEN => tied_to_ground_i,
580  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
581  RXUSRCLK => RXUSRCLK_IN,
582  RXUSRCLK2 => RXUSRCLK2_IN,
583  ------------------ Receive Ports - FPGA RX interface Ports -----------------
584  RXDATA => rxdata_i,
585  ------------------- Receive Ports - Pattern Checker Ports ------------------
586  RXPRBSERR => RXPRBSERR_OUT,
587  RXPRBSSEL => RXPRBSSEL_IN,
588  ------------------- Receive Ports - Pattern Checker ports ------------------
589  RXPRBSCNTRESET => RXPRBSCNTRESET_IN,
590  -------------------- Receive Ports - RX Equalizer Ports -------------------
591  RXDFEXYDEN => tied_to_vcc_i,
592  RXDFEXYDHOLD => tied_to_ground_i,
593  RXDFEXYDOVRDEN => tied_to_ground_i,
594  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
595  RXDISPERR => open,
596  RXNOTINTABLE => open,
597  --------------------------- Receive Ports - RX AFE -------------------------
598  GTXRXP => GTXRXP_IN ,
599  ------------------------ Receive Ports - RX AFE Ports ----------------------
600  GTXRXN => GTXRXN_IN ,
601  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
602  RXBUFRESET => RXBUFRESET_IN,
603  RXBUFSTATUS => RXBUFSTATUS_OUT,
604  RXDDIEN => tied_to_ground_i,
605  RXDLYBYPASS => tied_to_vcc_i,
606  RXDLYEN => tied_to_ground_i,
607  RXDLYOVRDEN => tied_to_ground_i,
608  RXDLYSRESET => tied_to_ground_i,
609  RXDLYSRESETDONE => open,
610  RXPHALIGN => tied_to_ground_i,
611  RXPHALIGNDONE => open,
612  RXPHALIGNEN => tied_to_ground_i,
613  RXPHDLYPD => tied_to_ground_i,
614  RXPHDLYRESET => tied_to_ground_i,
615  RXPHMONITOR => open,
616  RXPHOVRDEN => tied_to_ground_i,
617  RXPHSLIPMONITOR => open,
618  RXSTATUS => open,
619  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
620  RXBYTEISALIGNED => open,
621  RXBYTEREALIGN => open,
622  RXCOMMADET => open,
623  RXCOMMADETEN => tied_to_ground_i,
624  RXMCOMMAALIGNEN => tied_to_ground_i,
625  RXPCOMMAALIGNEN => tied_to_ground_i,
626  ------------------ Receive Ports - RX Channel Bonding Ports ----------------
627  RXCHANBONDSEQ => open,
628  RXCHBONDEN => tied_to_ground_i,
629  RXCHBONDLEVEL => tied_to_ground_vec_i (2 downto 0),
630  RXCHBONDMASTER => tied_to_ground_i,
631  RXCHBONDO => open,
632  RXCHBONDSLAVE => tied_to_ground_i,
633  ----------------- Receive Ports - RX Channel Bonding Ports ----------------
634  RXCHANISALIGNED => open,
635  RXCHANREALIGN => open,
636  -------------------- Receive Ports - RX Equailizer Ports -------------------
637  RXLPMHFHOLD => tied_to_ground_i,
638  RXLPMHFOVRDEN => tied_to_ground_i,
639  RXLPMLFHOLD => tied_to_ground_i,
640  --------------------- Receive Ports - RX Equalizer Ports -------------------
641  RXDFEAGCHOLD => RXDFEAGCHOLD_IN,
642  RXDFEAGCOVRDEN => tied_to_ground_i,
643  RXDFECM1EN => tied_to_ground_i,
644  RXDFELFHOLD => RXDFELFHOLD_IN,
645  RXDFELFOVRDEN => tied_to_vcc_i,
646  RXDFELPMRESET => tied_to_ground_i,
647  RXDFETAP2HOLD => tied_to_ground_i,
648  RXDFETAP2OVRDEN => tied_to_ground_i,
649  RXDFETAP3HOLD => tied_to_ground_i,
650  RXDFETAP3OVRDEN => tied_to_ground_i,
651  RXDFETAP4HOLD => tied_to_ground_i,
652  RXDFETAP4OVRDEN => tied_to_ground_i,
653  RXDFETAP5HOLD => tied_to_ground_i,
654  RXDFETAP5OVRDEN => tied_to_ground_i,
655  RXDFEUTHOLD => tied_to_ground_i,
656  RXDFEUTOVRDEN => tied_to_ground_i,
657  RXDFEVPHOLD => tied_to_ground_i,
658  RXDFEVPOVRDEN => tied_to_ground_i,
659  RXDFEVSEN => tied_to_ground_i,
660  RXLPMLFKLOVRDEN => tied_to_ground_i,
661  RXMONITOROUT => open,
662  RXMONITORSEL => "00",
663  RXOSHOLD => tied_to_ground_i,
664  RXOSOVRDEN => tied_to_ground_i,
665  ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
666  RXRATEDONE => open,
667  --------------- Receive Ports - RX Fabric Output Control Ports -------------
668  RXOUTCLK => RXOUTCLK_OUT,
669  RXOUTCLKFABRIC => open,
670  RXOUTCLKPCS => open,
671  RXOUTCLKSEL => "010",
672  ---------------------- Receive Ports - RX Gearbox Ports --------------------
673  RXDATAVALID => RXDATAVALID_OUT,
674  RXHEADER(2) => rxheader_float_i ,
675  RXHEADER(1 downto 0) => RXHEADER_OUT,
676  RXHEADERVALID => RXHEADERVALID_OUT,
677  RXSTARTOFSEQ => open,
678  --------------------- Receive Ports - RX Gearbox Ports --------------------
679  RXGEARBOXSLIP => RXGEARBOXSLIP_IN,
680  ------------- Receive Ports - RX Initialization and Reset Ports ------------
681  GTRXRESET => GTRXRESET_IN,
682  RXOOBRESET => tied_to_ground_i,
683  RXPCSRESET => RXPCSRESET_IN,
684  RXPMARESET => RXPMARESET_IN,
685  ------------------ Receive Ports - RX Margin Analysis ports ----------------
686  RXLPMEN => RXLPMEN_IN,
687  ------------------- Receive Ports - RX OOB Signaling ports -----------------
688  RXCOMSASDET => open,
689  RXCOMWAKEDET => open,
690  ------------------ Receive Ports - RX OOB Signaling ports -----------------
691  RXCOMINITDET => open,
692  ------------------ Receive Ports - RX OOB signalling Ports -----------------
693  RXELECIDLE => open,
694  RXELECIDLEMODE => "11",
695  ----------------- Receive Ports - RX Polarity Control Ports ----------------
696  RXPOLARITY => tied_to_ground_i,
697  ---------------------- Receive Ports - RX gearbox ports --------------------
698  RXSLIDE => tied_to_ground_i,
699  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
700  RXCHARISCOMMA => open,
701  RXCHARISK => open,
702  ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
703  RXCHBONDI => "00000",
704  -------------- Receive Ports -RX Initialization and Reset Ports ------------
705  RXRESETDONE => RXRESETDONE_OUT,
706  -------------------------------- Rx AFE Ports ------------------------------
707  RXQPIEN => tied_to_ground_i,
708  RXQPISENN => open,
709  RXQPISENP => open,
710  --------------------------- TX Buffer Bypass Ports -------------------------
711  TXPHDLYTSTCLK => tied_to_ground_i,
712  ------------------------ TX Configurable Driver Ports ----------------------
713  TXPOSTCURSOR => "00000",
714  TXPOSTCURSORINV => tied_to_ground_i,
715  TXPRECURSOR => tied_to_ground_vec_i (4 downto 0),
716  TXPRECURSORINV => tied_to_ground_i,
717  TXQPIBIASEN => tied_to_ground_i,
718  TXQPISTRONGPDOWN => tied_to_ground_i,
719  TXQPIWEAKPUP => tied_to_ground_i,
720  --------------------- TX Initialization and Reset Ports --------------------
721  CFGRESET => tied_to_ground_i,
722  GTTXRESET => GTTXRESET_IN,
723  PCSRSVDOUT => open,
724  TXUSERRDY => TXUSERRDY_IN,
725  ---------------------- Transceiver Reset Mode Operation --------------------
726  GTRESETSEL => tied_to_ground_i,
727  RESETOVRD => tied_to_ground_i,
728  ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
729  TXCHARDISPMODE => tied_to_ground_vec_i (7 downto 0),
730  TXCHARDISPVAL => tied_to_ground_vec_i (7 downto 0),
731  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
732  TXUSRCLK => TXUSRCLK_IN,
733  TXUSRCLK2 => TXUSRCLK2_IN,
734  --------------------- Transmit Ports - PCI Express Ports -------------------
735  TXELECIDLE => tied_to_ground_i,
736  TXMARGIN => tied_to_ground_vec_i (2 downto 0),
737  TXRATE => tied_to_ground_vec_i (2 downto 0),
738  TXSWING => tied_to_ground_i,
739  ------------------ Transmit Ports - Pattern Generator Ports ----------------
740  TXPRBSFORCEERR => tied_to_ground_i,
741  ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
742  TXDLYBYPASS => tied_to_vcc_i,
743  TXDLYEN => tied_to_ground_i,
744  TXDLYHOLD => tied_to_ground_i,
745  TXDLYOVRDEN => tied_to_ground_i,
746  TXDLYSRESET => tied_to_ground_i,
747  TXDLYSRESETDONE => open,
748  TXDLYUPDOWN => tied_to_ground_i,
749  TXPHALIGN => tied_to_ground_i,
750  TXPHALIGNDONE => open,
751  TXPHALIGNEN => tied_to_ground_i,
752  TXPHDLYPD => tied_to_ground_i,
753  TXPHDLYRESET => tied_to_ground_i,
754  TXPHINIT => tied_to_ground_i,
755  TXPHINITDONE => open,
756  TXPHOVRDEN => tied_to_ground_i,
757  ---------------------- Transmit Ports - TX Buffer Ports --------------------
758  TXBUFSTATUS => open,
759  --------------- Transmit Ports - TX Configurable Driver Ports --------------
760  TXBUFDIFFCTRL => "100",
761  TXDEEMPH => tied_to_ground_i,
762  TXDIFFCTRL => TXDIFFCTRL_IN,
763  TXDIFFPD => tied_to_ground_i,
764  TXINHIBIT => TXINHIBIT_IN,
765  TXMAINCURSOR => TXMAINCURSOR_IN,
766  TXPISOPD => tied_to_ground_i,
767  ------------------ Transmit Ports - TX Data Path interface -----------------
768  TXDATA => txdata_i,
769  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
770  GTXTXN => GTXTXN_OUT,
771  GTXTXP => GTXTXP_OUT,
772  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
773  TXOUTCLK => TXOUTCLK_OUT,
774  TXOUTCLKFABRIC => TXOUTCLKFABRIC_OUT ,
775  TXOUTCLKPCS => TXOUTCLKPCS_OUT,
776  TXOUTCLKSEL => "010",
777  TXRATEDONE => open,
778  --------------------- Transmit Ports - TX Gearbox Ports --------------------
779  TXCHARISK => tied_to_ground_vec_i (7 downto 0),
780  TXGEARBOXREADY => open,
781  TXHEADER(2) => tied_to_ground_i,
782  TXHEADER(1 downto 0) => TXHEADER_IN,
783  TXSEQUENCE => TXSEQUENCE_IN,
784  TXSTARTSEQ => tied_to_ground_i,
785  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
786  TXPCSRESET => TXPCSRESET_IN,
787  TXPMARESET => tied_to_ground_i,
788  TXRESETDONE => TXRESETDONE_OUT,
789  ------------------ Transmit Ports - TX OOB signalling Ports ----------------
790  TXCOMFINISH => open,
791  TXCOMINIT => tied_to_ground_i,
792  TXCOMSAS => tied_to_ground_i,
793  TXCOMWAKE => tied_to_ground_i,
794  TXPDELECIDLEMODE => tied_to_ground_i,
795  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
796  TXPOLARITY => tied_to_ground_i,
797  --------------- Transmit Ports - TX Receiver Detection Ports --------------
798  TXDETECTRX => tied_to_ground_i,
799  ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
800  TX8B10BBYPASS => tied_to_ground_vec_i (7 downto 0),
801  ------------------ Transmit Ports - pattern Generator Ports ----------------
802  TXPRBSSEL => TXPRBSSEL_IN,
803  ----------------------- Tx Configurable Driver Ports ----------------------
804  TXQPISENN => open,
805  TXQPISENP => open
806 
807  );
808 
809  end RTL;
810 
811 
812 
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