AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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serdes5gpdprod_sync_block.vhd
1 --////////////////////////////////////////////////////////////////////////////////
2 --// ____ ____
3 --// / /\/ /
4 --// /___/ \ / Vendor: Xilinx
5 --// \ \ \/ Version : 2.7
6 --// \ \ Application : 7 Series FPGAs Transceivers Wizard
7 --// / / Filename :serdes5gpdprod_sync_block.vhd
8 --// /___/ /\
9 --// \ \ / \
10 --// \___\/\___\
11 --//
12 --//
13 --
14 -- Description: Used on signals crossing from one clock domain to
15 -- another, this is a flip-flop pair, with both flops
16 -- placed together with RLOCs into the same slice. Thus
17 -- the routing delay between the two is minimum to safe-
18 -- guard against metastability issues.
19 --
20 --
21 -- Module serdes5GpdProd_sync_block
22 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
23 --
24 --
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70 
71 
72 
73 
74 
75 library ieee;
76 use ieee.std_logic_1164.all;
77 
78 library unisim;
79 use unisim.vcomponents.all;
80 
82  generic (
83  INITIALISE : bit_vector(1 downto 0) := "00"
84  );
85  port (
86  clk : in std_logic; -- clock to be sync'ed to
87  data_in : in std_logic; -- Data to be 'synced'
88  data_out : out std_logic -- synced data
89  );
90 
91 end serdes5gpdprod_sync_block;
92 
93 
94 architecture structural of serdes5gpdprod_sync_block is
95 
96 
97  -- Internal Signals
98  signal data_sync1 : std_logic;
99 
100  -- These attributes will stop Vivado translating the desired flip-flops into an
101  -- SRL based shift register.
102  attribute ASYNC_REG : string;
103  attribute ASYNC_REG of data_sync : label is "TRUE";
104  attribute ASYNC_REG of data_sync_reg : label is "TRUE";
105 
106  -- These attributes will stop timing errors being reported on the target flip-flop during back annotated SDF simulation.
107  attribute MSGON : string;
108  attribute MSGON of data_sync : label is "FALSE";
109  attribute MSGON of data_sync_reg : label is "FALSE";
110 
111  -- These attributes will stop XST translating the desired flip-flops into an
112  -- SRL based shift register.
113  attribute shreg_extract : string;
114  attribute shreg_extract of data_sync : label is "no";
115  attribute shreg_extract of data_sync_reg : label is "no";
116 
117 
118 begin
119 
120  data_sync : FD
121  generic map (
122  INIT => INITIALISE(0)
123  )
124  port map (
125  C => clk,
126  D => data_in,
127  Q => data_sync1
128  );
129 
130 
131  data_sync_reg : FD
132  generic map (
133  INIT => INITIALISE(1)
134  )
135  port map (
136  C => clk,
137  D => data_sync1,
138  Q => data_out
139  );
140 
141 
142 end structural;
143 
144