AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
serdes5gpdprod_rx_startup_fsm.vhd
1 --////////////////////////////////////////////////////////////////////////////////
2 --// ____ ____
3 --// / /\/ /
4 --// /___/ \ / Vendor: Xilinx
5 --// \ \ \/ Version : 2.7
6 --// \ \ Application : 7 Series FPGAs Transceivers Wizard
7 --// / / Filename : serdes5gpdprod_rx_startup_fsm.vhd
8 --// /___/ /\
9 --// \ \ / \
10 --// \___\/\___\
11 --//
12 --//
13 -- Description : This module performs RX reset and initialization.
14 --
15 --
16 --
17 -- Module serdes5GpdProd_rx_startup_fsm
18 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
19 --
20 --
21 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
22 --
23 -- This file contains confidential and proprietary information
24 -- of Xilinx, Inc. and is protected under U.S. and
25 -- international copyright and other intellectual property
26 -- laws.
27 --
28 -- DISCLAIMER
29 -- This disclaimer is not a license and does not grant any
30 -- rights to the materials distributed herewith. Except as
31 -- otherwise provided in a valid license issued to you by
32 -- Xilinx, and to the maximum extent permitted by applicable
33 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
34 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
35 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
36 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
37 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
38 -- (2) Xilinx shall not be liable (whether in contract or tort,
39 -- including negligence, or under any other theory of
40 -- liability) for any loss or damage of any kind or nature
41 -- related to, arising under or in connection with these
42 -- materials, including for any direct, or any indirect,
43 -- special, incidental, or consequential loss or damage
44 -- (including loss of data, profits, goodwill, or any type of
45 -- loss or damage suffered as a result of any action brought
46 -- by a third party) even if such damage or loss was
47 -- reasonably foreseeable or Xilinx had been advised of the
48 -- possibility of the same.
49 --
50 -- CRITICAL APPLICATIONS
51 -- Xilinx products are not designed or intended to be fail-
52 -- safe, or for use in any application requiring fail-safe
53 -- performance, such as life-support or safety devices or
54 -- systems, Class III medical devices, nuclear facilities,
55 -- applications related to the deployment of airbags, or any
56 -- other applications that could lead to death, personal
57 -- injury, or severe property or environmental damage
58 -- (individually and collectively, "Critical
59 -- Applications"). Customer assumes the sole risk and
60 -- liability of any use of Xilinx products in Critical
61 -- Applications, subject only to applicable laws and
62 -- regulations governing limitations on product liability.
63 --
64 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
65 -- PART OF THIS FILE AT ALL TIMES.
66 
67 
68 --*****************************************************************************
69 
70 library IEEE;
71 use IEEE.STD_LOGIC_1164.ALL;
72 use IEEE.NUMERIC_STD.ALL;
73 
75  Generic( EXAMPLE_SIMULATION : integer := 0;
76  GT_TYPE : string := "GTX";
77  EQ_MODE : string := "DFE"; --RX Equalisation Mode; set to DFE or LPM
78  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
79  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
80  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
81  RX_QPLL_USED : boolean := False; -- share these two generic values
82  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
83  -- is enough. For single-lane applications the automatic alignment is
84  -- sufficient
85  );
86  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
87  --or reference-clock present at startup.
88  RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
89  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
90  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
91  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
92  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
93  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
94  RXRESETDONE : in STD_LOGIC;
95  MMCM_LOCK : in STD_LOGIC;
96  RECCLK_STABLE : in STD_LOGIC;
97  RECCLK_MONITOR_RESTART : in STD_LOGIC:='0';
98  DATA_VALID : in STD_LOGIC;
99  TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
100  DONT_RESET_ON_DATA_ERROR : in STD_LOGIC; --Used to control the Auto-Reset of FSM when Data Error is detected
101  GTRXRESET : out STD_LOGIC:='0';
102  MMCM_RESET : out STD_LOGIC:='1';
103  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
104  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
105  RX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished.
106  RXUSERRDY : out STD_LOGIC:='0';
107  RUN_PHALIGNMENT : out STD_LOGIC;
108  PHALIGNMENT_DONE : in STD_LOGIC;
109  RESET_PHALIGNMENT : out STD_LOGIC:='0';
110  RXDFEAGCHOLD : out STD_LOGIC;
111  RXDFELFHOLD : out STD_LOGIC;
112  RXLPMLFHOLD : out STD_LOGIC;
113  RXLPMHFHOLD : out STD_LOGIC;
114  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
115  -- Retries it took to get the transceiver up and running
116  );
117 end serdes5GpdProd_RX_STARTUP_FSM;
118 
119 --Interdependencies:
120 -- * Timing depends on the frequency of the stable clock. Hence counters-sizes
121 -- are calculated at design-time based on the Generics
122 --
123 -- * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX
124 -- => signal which PLL has been reset
125 -- *
126 
127 
128 
129 architecture RTL of serdes5GpdProd_RX_STARTUP_FSM is
130 
131  component serdes5GpdProd_sync_block
132  generic (
133  INITIALISE : bit_vector(1 downto 0) := "00"
134  );
135  port (
136  clk : in std_logic;
137  data_in : in std_logic;
138  data_out : out std_logic
139  );
140  end component;
141 
142 
143  type rx_rst_fsm_type is(
144  INIT, ASSERT_ALL_RESETS, RELEASE_PLL_RESET, VERIFY_RECCLK_STABLE,
145  RELEASE_MMCM_RESET, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
146  MONITOR_DATA_VALID, FSM_DONE);
147 
148  signal rx_state : rx_rst_fsm_type := INIT;
149 
150  constant MMCM_LOCK_CNT_MAX : integer := 1024;
151  constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
152  constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
153  constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
154  constant WAIT_TIMEOUT_2ms : integer := 2000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out
155  constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out
156  constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--500 us time-out
157  constant WAIT_TIMEOUT_1us : integer := 1000 / STABLE_CLOCK_PERIOD; --1 us time-out
158  constant WAIT_TIMEOUT_100us : integer := 100000 / STABLE_CLOCK_PERIOD; --100 us time-out
159  constant WAIT_TIME_ADAPT : integer := (37000000 /integer(5))/STABLE_CLOCK_PERIOD;
160 
161  signal init_wait_count : integer range 0 to WAIT_MAX:=0;
162  signal init_wait_done : std_logic := '0';
163  signal pll_reset_asserted : std_logic := '0';
164  signal rx_fsm_reset_done_int : std_logic := '0';
165  signal rx_fsm_reset_done_int_s2 : std_logic := '0';
166  signal rx_fsm_reset_done_int_s3 : std_logic := '0';
167 
168  signal rxresetdone_s2 : std_logic := '0';
169  signal rxresetdone_s3 : std_logic := '0';
170 
171  constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1;
172  signal retry_counter_int : integer range 0 to MAX_RETRIES := 0;
173  signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0;
174  signal recclk_mon_restart_count : integer range 0 to 3:= 0;
175  signal recclk_mon_count_reset : std_logic := '0';
176 
177  signal reset_time_out : std_logic := '0';
178  signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points
179  signal time_tlock_max : std_logic := '0';--|have been reached.
180  signal time_out_500us : std_logic := '0';--|
181  signal time_out_1us : std_logic := '0';--/
182  signal time_out_100us : std_logic := '0';--/
183  signal check_tlock_max : std_logic := '0';
184 
185  signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
186  signal mmcm_lock_int : std_logic := '0';
187  signal mmcm_lock_i : std_logic := '0';
188  signal mmcm_lock_reclocked : std_logic := '0';
189 
190  signal run_phase_alignment_int: std_logic := '0';
191  signal run_phase_alignment_int_s2 : std_logic := '0';
192  signal run_phase_alignment_int_s3 : std_logic := '0';
193 
194  constant MAX_WAIT_BYPASS : integer := 5000;--5000 RXUSRCLK cycles is the max time for Multi lanes designs
195  signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1;
196  signal time_out_wait_bypass : std_logic := '0';
197  signal time_out_wait_bypass_s2 : std_logic := '0';
198  signal time_out_wait_bypass_s3 : std_logic := '0';
199 
200  signal refclk_lost : std_logic;
201 
202  signal time_out_adapt : std_logic := '0';
203  signal adapt_count_reset : std_logic := '0';
204  signal adapt_count : integer range 0 to WAIT_TIME_ADAPT-1;
205 
206  signal data_valid_sync: std_logic := '0';
207 
208  signal cplllock_sync: std_logic := '0';
209  signal qplllock_sync: std_logic := '0';
210  signal cplllock_prev: std_logic := '0';
211  signal qplllock_prev: std_logic := '0';
212  signal cplllock_ris_edge: std_logic := '0';
213  signal qplllock_ris_edge: std_logic := '0';
214 
215 begin
216  --Alias section, signals used within this module mapped to output ports:
217  RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
218  RUN_PHALIGNMENT <= run_phase_alignment_int;
219  RX_FSM_RESET_DONE <= rx_fsm_reset_done_int;
220 
221  process(STABLE_CLOCK)
222  begin
223  if rising_edge(STABLE_CLOCK) then
224  -- The counter starts running when configuration has finished and
225  -- the clock is stable. When its maximum count-value has been reached,
226  -- the 500 ns from Answer Record 43482 have been passed.
227  if init_wait_count = WAIT_MAX then
228  init_wait_done <= '1';
229  else
230  init_wait_count <= init_wait_count + 1;
231  end if;
232  end if;
233  end process;
234 
235 
236  adapt_wait_sim:if(EXAMPLE_SIMULATION = 1) generate
237  time_out_adapt <= '1';
238  end generate;
239 
240  adapt_wait_hw:if(EXAMPLE_SIMULATION = 0) generate
241  process(STABLE_CLOCK)
242  begin
243  if rising_edge(STABLE_CLOCK) then
244  if(adapt_count_reset = '1') then
245  adapt_count <= 0;
246  time_out_adapt <= '0';
247  elsif(adapt_count = WAIT_TIME_ADAPT -1) then
248  time_out_adapt <= '1';
249  else
250  adapt_count <= adapt_count + 1;
251  end if;
252  end if;
253  end process;
254  end generate;
255 
256  retries_recclk_monitor:process(STABLE_CLOCK)
257  begin
258  --This counter monitors, how many retries the RECCLK monitor
259  --runs. If during startup too many retries are necessary, the whole
260  --initialisation-process of the transceivers gets restarted.
261  if rising_edge(STABLE_CLOCK) then
262  if recclk_mon_count_reset = '1' then
263  recclk_mon_restart_count <= 0;
264  elsif RECCLK_MONITOR_RESTART = '1' then
265  if recclk_mon_restart_count = 3 then
266  recclk_mon_restart_count <= 0;
267  else
268  recclk_mon_restart_count <= recclk_mon_restart_count + 1;
269  end if;
270  end if;
271  end if;
272  end process;
273 
274  timeouts:process(STABLE_CLOCK)
275  begin
276  if rising_edge(STABLE_CLOCK) then
277  -- One common large counter for generating three time-out signals.
278  -- Intermediate time-outs are derived from calculated values, based
279  -- on the period of the provided clock.
280  if reset_time_out = '1' then
281  time_out_counter <= 0;
282  time_out_2ms <= '0';
283  time_tlock_max <= '0';
284  time_out_500us <= '0';
285  time_out_1us <= '0';
286  time_out_100us <= '0';
287  else
288  if time_out_counter = WAIT_TIMEOUT_2ms then
289  time_out_2ms <= '1';
290  else
291  time_out_counter <= time_out_counter + 1;
292  end if;
293 
294  if (time_out_counter > WAIT_TLOCK_MAX) and (check_tlock_max='1') then
295  time_tlock_max <= '1';
296  end if;
297 
298  if time_out_counter = WAIT_TIMEOUT_500us then
299  time_out_500us <= '1';
300  end if;
301 
302  if time_out_counter = WAIT_TIMEOUT_1us then
303  time_out_1us <= '1';
304  end if;
305 
306  if time_out_counter = WAIT_TIMEOUT_100us then
307  time_out_100us <= '1';
308  end if;
309 
310  end if;
311  end if;
312  end process;
313 
314 
315  mmcm_lock_wait:process(STABLE_CLOCK)
316  begin
317  --The lock-signal from the MMCM is not immediately used but
318  --enabling a counter. Only when the counter hits its maximum,
319  --the MMCM is considered as "really" locked.
320  --The counter avoids that the FSM already starts on only a
321  --coarse lock of the MMCM (=toggling of the LOCK-signal).
322  if rising_edge(STABLE_CLOCK) then
323  if mmcm_lock_i = '0' then
324  mmcm_lock_count <= 0;
325  mmcm_lock_reclocked <= '0';
326  else
327  if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
328  mmcm_lock_count <= mmcm_lock_count + 1;
329  else
330  mmcm_lock_reclocked <= '1';
331  end if;
332  end if;
333  end if;
334  end process;
335 
336 
337  -- Clock Domain Crossing
338 
339  sync_run_phase_alignment_int : serdes5GpdProd_sync_block
340  port map
341  (
342  clk => RXUSERCLK,
343  data_in => run_phase_alignment_int ,
344  data_out => run_phase_alignment_int_s2
345  );
346 
347  sync_rx_fsm_reset_done_int : serdes5GpdProd_sync_block
348  port map
349  (
350  clk => RXUSERCLK,
351  data_in => rx_fsm_reset_done_int,
352  data_out => rx_fsm_reset_done_int_s2
353  );
354 
355  process(RXUSERCLK)
356  begin
357  if rising_edge(RXUSERCLK) then
358  run_phase_alignment_int_s3 <= run_phase_alignment_int_s2;
359 
360  rx_fsm_reset_done_int_s3 <= rx_fsm_reset_done_int_s2;
361  end if;
362  end process;
363 
364  sync_RXRESETDONE : serdes5GpdProd_sync_block
365  port map
366  (
367  clk => STABLE_CLOCK,
368  data_in => RXRESETDONE,
369  data_out => rxresetdone_s2
370  );
371 
372  sync_time_out_wait_bypass : serdes5GpdProd_sync_block
373  port map
374  (
375  clk => STABLE_CLOCK,
376  data_in => time_out_wait_bypass,
377  data_out => time_out_wait_bypass_s2
378  );
379 
380  sync_mmcm_lock_reclocked : serdes5GpdProd_sync_block
381  port map
382  (
383  clk => STABLE_CLOCK,
384  data_in => MMCM_LOCK,
385  data_out => mmcm_lock_i
386  );
387 
388  sync_data_valid : serdes5GpdProd_sync_block
389  port map
390  (
391  clk => STABLE_CLOCK,
392  data_in => DATA_VALID,
393  data_out => data_valid_sync
394  );
395 
396 
397  process(STABLE_CLOCK)
398  begin
399  if rising_edge(STABLE_CLOCK) then
400  rxresetdone_s3 <= rxresetdone_s2;
401 
402  time_out_wait_bypass_s3 <= time_out_wait_bypass_s2;
403  cplllock_prev <= cplllock_sync;
404  qplllock_prev <= qplllock_sync;
405  end if;
406  end process;
407 
408  sync_CPLLLOCK : serdes5GpdProd_sync_block
409  port map
410  (
411  clk => STABLE_CLOCK,
412  data_in => CPLLLOCK,
413  data_out => cplllock_sync
414  );
415 
416  sync_QPLLLOCK : serdes5GpdProd_sync_block
417  port map
418  (
419  clk => STABLE_CLOCK,
420  data_in => QPLLLOCK,
421  data_out => qplllock_sync
422  );
423 
424 
425  process (STABLE_CLOCK)
426  begin
427  if rising_edge(STABLE_CLOCK) then
428  if(SOFT_RESET = '1' ) then
429  cplllock_ris_edge <= '0';
430  elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
431  cplllock_ris_edge <= '1';
432  elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
433  cplllock_ris_edge <= cplllock_ris_edge;
434  else
435  cplllock_ris_edge <= '0';
436  end if;
437  end if;
438  end process;
439 
440  process (STABLE_CLOCK)
441  begin
442  if rising_edge(STABLE_CLOCK) then
443  if(SOFT_RESET = '1' ) then
444  qplllock_ris_edge <= '0';
445  elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
446  qplllock_ris_edge <= '1';
447  elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
448  qplllock_ris_edge <= qplllock_ris_edge;
449  else
450  qplllock_ris_edge <= '0';
451  end if;
452  end if;
453  end process;
454 
455 
456 
457  timeout_buffer_bypass:process(RXUSERCLK)
458  begin
459  if rising_edge(RXUSERCLK) then
460  if run_phase_alignment_int_s3 = '0' then
461  wait_bypass_count <= 0;
462  time_out_wait_bypass <= '0';
463  elsif (run_phase_alignment_int_s3 = '1') and (rx_fsm_reset_done_int_s3 = '0') then
464  if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
465  time_out_wait_bypass <= '1';
466  else
467  wait_bypass_count <= wait_bypass_count + 1;
468  end if;
469  end if;
470  end if;
471  end process;
472 
473  refclk_lost <= '1' when ((RX_QPLL_USED and QPLLREFCLKLOST='1') or (not RX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
474 
475 
476 
477  --FSM for resetting the GTX/GTH/GTP in the 7-series.
478  --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
479  --
480  -- Following steps are performed:
481  -- 1) After configuration wait for approximately 500 ns as specified in
482  -- answer-record 43482
483  -- 2) Assert all resets on the GT and on an MMCM potentially connected.
484  -- After that wait until a reference-clock has been detected.
485  -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
486  -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
487  -- Also get info from the TX-side which PLL has been reset.
488  -- 5) Wait for the RESET_DONE-signal from the GT.
489  -- 6) Signal to start the phase-alignment procedure and wait for it to
490  -- finish.
491  -- 7) Reset-sequence has successfully run through. Signal this to the
492  -- rest of the design by asserting RX_FSM_RESET_DONE.
493 
494  reset_fsm:process(STABLE_CLOCK)
495  begin
496  if rising_edge(STABLE_CLOCK) then
497  if (SOFT_RESET = '1' or (not(rx_state = INIT) and not(rx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
498  rx_state <= INIT;
499  RXUSERRDY <= '0';
500  GTRXRESET <= '0';
501  MMCM_RESET <= '1';
502  rx_fsm_reset_done_int <= '0';
503  QPLL_RESET <= '0';
504  CPLL_RESET <= '0';
505  pll_reset_asserted <= '0';
506  reset_time_out <= '1';
507  retry_counter_int <= 0;
508  run_phase_alignment_int <= '0';
509  check_tlock_max <= '0';
510  RESET_PHALIGNMENT <= '1';
511  recclk_mon_count_reset <= '1';
512  adapt_count_reset <= '1';
513  RXDFEAGCHOLD <= '0';
514  RXDFELFHOLD <= '0';
515  RXLPMLFHOLD <= '0';
516  RXLPMHFHOLD <= '0';
517 
518  else
519 
520  case rx_state is
521  when INIT =>
522  --Initial state after configuration. This state will be left after
523  --approx. 500 ns and not be re-entered.
524  if init_wait_done = '1' then
525  rx_state <= ASSERT_ALL_RESETS;
526  end if;
527 
528  when ASSERT_ALL_RESETS =>
529  --This is the state into which the FSM will always jump back if any
530  --time-outs will occur.
531  --The number of retries is reported on the output RETRY_COUNTER. In
532  --case the transceiver never comes up for some reason, this machine
533  --will still continue its best and rerun until the FPGA is turned off
534  --or the transceivers come up correctly.
535  if RX_QPLL_USED and not TX_QPLL_USED then
536  if pll_reset_asserted = '0' then
537  QPLL_RESET <= '1';
538  pll_reset_asserted <= '1';
539  else
540  QPLL_RESET <= '0';
541  end if;
542  elsif not RX_QPLL_USED and TX_QPLL_USED then
543  if pll_reset_asserted = '0' then
544  CPLL_RESET <= '1';
545  pll_reset_asserted <= '1';
546  else
547  CPLL_RESET <= '0';
548  end if;
549  end if;
550 
551  RXUSERRDY <= '0';
552  GTRXRESET <= '1';
553  MMCM_RESET <= '1';
554  run_phase_alignment_int <= '0';
555  RESET_PHALIGNMENT <= '1';
556  check_tlock_max <= '0';
557  recclk_mon_count_reset <= '1';
558  adapt_count_reset <= '1';
559 
560 
561  if (RX_QPLL_USED and not TX_QPLL_USED and (QPLLREFCLKLOST = '0') and pll_reset_asserted = '1') or
562  (not RX_QPLL_USED and TX_QPLL_USED and (CPLLREFCLKLOST = '0') and pll_reset_asserted = '1') or
563  (not RX_QPLL_USED and not TX_QPLL_USED and (CPLLREFCLKLOST = '0') ) or
564  (RX_QPLL_USED and TX_QPLL_USED and (QPLLREFCLKLOST = '0') ) then
565  rx_state <= RELEASE_PLL_RESET;
566  reset_time_out <= '1';
567  end if;
568 
569  when RELEASE_PLL_RESET =>
570  --PLL-Reset of the GTX gets released and the time-out counter
571  --starts running.
572  pll_reset_asserted <= '0';
573  reset_time_out <= '0';
574 
575 
576  if (RX_QPLL_USED and not TX_QPLL_USED and (qplllock_ris_edge = '1')) or
577  (not RX_QPLL_USED and TX_QPLL_USED and (cplllock_ris_edge = '1')) then
578  rx_state <= VERIFY_RECCLK_STABLE;
579  reset_time_out <= '1';
580  recclk_mon_count_reset <= '0';
581  adapt_count_reset <= '0';
582 
583  elsif (RX_QPLL_USED and (qplllock_sync = '1')) or
584  (not RX_QPLL_USED and (cplllock_sync = '1')) then
585  rx_state <= VERIFY_RECCLK_STABLE;
586  reset_time_out <= '1';
587  recclk_mon_count_reset <= '0';
588  adapt_count_reset <= '0';
589  end if;
590 
591  if time_out_2ms = '1' then
592  if retry_counter_int = MAX_RETRIES then
593  -- If too many retries are performed compared to what is specified in
594  -- the generic, the counter simply wraps around.
595  retry_counter_int <= 0;
596  else
597  retry_counter_int <= retry_counter_int + 1;
598  end if;
599  rx_state <= ASSERT_ALL_RESETS;
600  end if;
601 
602  when VERIFY_RECCLK_STABLE =>
603  --reset_time_out <= '0';
604  --Time-out counter is not released in this state as here the FSM
605  --does not wait for a certain period of time but checks on the number
606  --of retries in the RECCLK monitor
607  GTRXRESET <= '0';
608  if RECCLK_STABLE = '1' then
609  rx_state <= RELEASE_MMCM_RESET;
610  reset_time_out <= '1';
611 
612  end if;
613 
614  if recclk_mon_restart_count = 2 then
615  --If two retries are performed in the RECCLK monitor
616  --the whole initialisation-sequence gets restarted.
617  if retry_counter_int = MAX_RETRIES then
618  -- If too many retries are performed compared to what is specified in
619  -- the generic, the counter simply wraps around.
620  retry_counter_int <= 0;
621  else
622  retry_counter_int <= retry_counter_int + 1;
623  end if;
624  rx_state <= ASSERT_ALL_RESETS;
625  end if;
626 
627  when RELEASE_MMCM_RESET =>
628  --Release of the MMCM-reset. Waiting for the MMCM to lock.
629  reset_time_out <= '0';
630  check_tlock_max <= '1';
631 
632  MMCM_RESET <= '0';
633  if mmcm_lock_reclocked = '1' then
634  rx_state <= WAIT_RESET_DONE;
635  reset_time_out <= '1';
636  end if;
637 
638  if time_tlock_max = '1' and reset_time_out = '0' then
639  if retry_counter_int = MAX_RETRIES then
640  -- If too many retries are performed compared to what is specified in
641  -- the generic, the counter simply wraps around.
642  retry_counter_int <= 0;
643  else
644  retry_counter_int <= retry_counter_int + 1;
645  end if;
646  rx_state <= ASSERT_ALL_RESETS;
647  end if;
648 
649  when WAIT_RESET_DONE =>
650  --When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY
651  --If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1'
652  if TXUSERRDY = '1' then
653  RXUSERRDY <= '1';
654  end if;
655  reset_time_out <= '0';
656  if rxresetdone_s3 = '1' then
657  rx_state <= DO_PHASE_ALIGNMENT;
658  reset_time_out <= '1';
659  end if;
660 
661  if time_out_2ms = '1' and reset_time_out = '0' then
662  if retry_counter_int = MAX_RETRIES then
663  -- If too many retries are performed compared to what is specified in
664  -- the generic, the counter simply wraps around.
665  retry_counter_int <= 0;
666  else
667  retry_counter_int <= retry_counter_int + 1;
668  end if;
669  rx_state <= ASSERT_ALL_RESETS;
670  end if;
671 
672  when DO_PHASE_ALIGNMENT =>
673  --The direct handling of the signals for the Phase Alignment is done outside
674  --this state-machine.
675  RESET_PHALIGNMENT <= '0';
676  run_phase_alignment_int <= '1';
677  reset_time_out <= '0';
678 
679  if PHALIGNMENT_DONE = '1' then
680  rx_state <= MONITOR_DATA_VALID;
681  reset_time_out <= '1';
682  end if;
683 
684  if time_out_wait_bypass_s3 = '1' then
685  if retry_counter_int = MAX_RETRIES then
686  -- If too many retries are performed compared to what is specified in
687  -- the generic, the counter simply wraps around.
688  retry_counter_int <= 0;
689  else
690  retry_counter_int <= retry_counter_int + 1;
691  end if;
692  rx_state <= ASSERT_ALL_RESETS;
693  end if;
694 
695  when MONITOR_DATA_VALID =>
696  reset_time_out <= '0';
697 
698  if(time_out_100us = '1' and data_valid_sync ='0' and DONT_RESET_ON_DATA_ERROR = '0' and reset_time_out = '0') then
699  rx_state <= ASSERT_ALL_RESETS;
700  rx_fsm_reset_done_int <= '0';
701  elsif (data_valid_sync = '1') then
702  rx_state <= FSM_DONE;
703  rx_fsm_reset_done_int <= '0';
704  reset_time_out <= '1';
705  end if;
706 
707  when FSM_DONE =>
708  reset_time_out <= '0';
709  if data_valid_sync = '0' then
710  rx_fsm_reset_done_int <= '0';
711  reset_time_out <= '1';
712  rx_state <= MONITOR_DATA_VALID;
713  elsif(time_out_1us = '1' and reset_time_out = '0') then
714  rx_fsm_reset_done_int <= '1';
715  end if;
716 
717  if(time_out_adapt = '1') then
718  if((GT_TYPE = "GTX" ) and EQ_MODE = "DFE") then
719  RXDFEAGCHOLD <= '1';
720  RXDFELFHOLD <= '1';
721  else
722  RXDFEAGCHOLD <= '0';
723  RXDFELFHOLD <= '0';
724  RXLPMHFHOLD <= '0';
725  RXLPMLFHOLD <= '0';
726  end if;
727  end if;
728 
729  when OTHERS =>
730  rx_state <= INIT;
731  end case;
732  end if;
733  end if;
734  end process;
735 
736 end RTL;
737 
738