AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
serdes5gpdprod_init.vhd
1 ------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : serdes5gpdprod_init.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 -- Description : This module instantiates the modules required for
13 -- reset and initialisation of the Transceiver
14 --
15 -- Module serdes5GpdProd_init
16 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
17 --
18 --
19 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
20 --
21 -- This file contains confidential and proprietary information
22 -- of Xilinx, Inc. and is protected under U.S. and
23 -- international copyright and other intellectual property
24 -- laws.
25 --
26 -- DISCLAIMER
27 -- This disclaimer is not a license and does not grant any
28 -- rights to the materials distributed herewith. Except as
29 -- otherwise provided in a valid license issued to you by
30 -- Xilinx, and to the maximum extent permitted by applicable
31 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
32 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
33 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
34 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
35 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
36 -- (2) Xilinx shall not be liable (whether in contract or tort,
37 -- including negligence, or under any other theory of
38 -- liability) for any loss or damage of any kind or nature
39 -- related to, arising under or in connection with these
40 -- materials, including for any direct, or any indirect,
41 -- special, incidental, or consequential loss or damage
42 -- (including loss of data, profits, goodwill, or any type of
43 -- loss or damage suffered as a result of any action brought
44 -- by a third party) even if such damage or loss was
45 -- reasonably foreseeable or Xilinx had been advised of the
46 -- possibility of the same.
47 --
48 -- CRITICAL APPLICATIONS
49 -- Xilinx products are not designed or intended to be fail-
50 -- safe, or for use in any application requiring fail-safe
51 -- performance, such as life-support or safety devices or
52 -- systems, Class III medical devices, nuclear facilities,
53 -- applications related to the deployment of airbags, or any
54 -- other applications that could lead to death, personal
55 -- injury, or severe property or environmental damage
56 -- (individually and collectively, "Critical
57 -- Applications"). Customer assumes the sole risk and
58 -- liability of any use of Xilinx products in Critical
59 -- Applications, subject only to applicable laws and
60 -- regulations governing limitations on product liability.
61 --
62 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
63 -- PART OF THIS FILE AT ALL TIMES.
64 
65 
66 library ieee;
67 use ieee.std_logic_1164.all;
68 use ieee.numeric_std.all;
69 use ieee.std_logic_unsigned.all;
70 library UNISIM;
71 use UNISIM.VCOMPONENTS.ALL;
72 
73 --***********************************Entity Declaration************************
74 
75 entity serdes5GpdProd_init is
76 generic
77 (
78  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
79  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
80  STABLE_CLOCK_PERIOD : integer := 20; --Period of the stable clock driving this state-machine, unit is [ns]
81  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
82 
83 );
84 port
85 (
86  SYSCLK_IN : in std_logic;
87  SOFT_RESET_IN : in std_logic;
88  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
89  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
90  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
91  GT0_DATA_VALID_IN : in std_logic;
92  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
93  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
94  GT1_DATA_VALID_IN : in std_logic;
95  GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
96  GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
97  GT2_DATA_VALID_IN : in std_logic;
98 
99  --_________________________________________________________________________
100  --GT0 (X1Y12)
101  --____________________________CHANNEL PORTS________________________________
102  ---------------------------- Channel - DRP Ports --------------------------
103  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
104  GT0_DRPCLK_IN : in std_logic;
105  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
106  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
107  GT0_DRPEN_IN : in std_logic;
108  GT0_DRPRDY_OUT : out std_logic;
109  GT0_DRPWE_IN : in std_logic;
110  ------------------------------ Power-Down Ports ----------------------------
111  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
112  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
113  --------------------- RX Initialization and Reset Ports --------------------
114  GT0_RXUSERRDY_IN : in std_logic;
115  -------------------------- RX Margin Analysis Ports ------------------------
116  GT0_EYESCANDATAERROR_OUT : out std_logic;
117  ------------------------- Receive Ports - CDR Ports ------------------------
118  GT0_RXCDRLOCK_OUT : out std_logic;
119  ------------------- Receive Ports - Clock Correction Ports -----------------
120  GT0_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
121  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
122  GT0_RXUSRCLK_IN : in std_logic;
123  GT0_RXUSRCLK2_IN : in std_logic;
124  ------------------ Receive Ports - FPGA RX interface Ports -----------------
125  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
126  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
127  GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
128  GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
129  --------------------------- Receive Ports - RX AFE -------------------------
130  GT0_GTXRXP_IN : in std_logic;
131  ------------------------ Receive Ports - RX AFE Ports ----------------------
132  GT0_GTXRXN_IN : in std_logic;
133  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
134  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
135  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
136  GT0_RXBYTEISALIGNED_OUT : out std_logic;
137  GT0_RXBYTEREALIGN_OUT : out std_logic;
138  GT0_RXCOMMADET_OUT : out std_logic;
139  GT0_RXMCOMMAALIGNEN_IN : in std_logic;
140  GT0_RXPCOMMAALIGNEN_IN : in std_logic;
141  ------------- Receive Ports - RX Initialization and Reset Ports ------------
142  GT0_GTRXRESET_IN : in std_logic;
143  GT0_RXPMARESET_IN : in std_logic;
144  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
145  GT0_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
146  GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
147  -------------- Receive Ports -RX Initialization and Reset Ports ------------
148  GT0_RXRESETDONE_OUT : out std_logic;
149  --------------------- TX Initialization and Reset Ports --------------------
150  GT0_GTTXRESET_IN : in std_logic;
151  GT0_TXUSERRDY_IN : in std_logic;
152  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
153  GT0_TXUSRCLK_IN : in std_logic;
154  GT0_TXUSRCLK2_IN : in std_logic;
155  ------------------ Transmit Ports - TX Data Path interface -----------------
156  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
157  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
158  GT0_GTXTXN_OUT : out std_logic;
159  GT0_GTXTXP_OUT : out std_logic;
160  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
161  GT0_TXOUTCLK_OUT : out std_logic;
162  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
163  GT0_TXOUTCLKPCS_OUT : out std_logic;
164  --------------------- Transmit Ports - TX Gearbox Ports --------------------
165  GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
166  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
167  GT0_TXRESETDONE_OUT : out std_logic;
168 
169  --GT1 (X1Y13)
170  --____________________________CHANNEL PORTS________________________________
171  ---------------------------- Channel - DRP Ports --------------------------
172  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
173  GT1_DRPCLK_IN : in std_logic;
174  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
175  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
176  GT1_DRPEN_IN : in std_logic;
177  GT1_DRPRDY_OUT : out std_logic;
178  GT1_DRPWE_IN : in std_logic;
179  ------------------------------ Power-Down Ports ----------------------------
180  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
181  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
182  --------------------- RX Initialization and Reset Ports --------------------
183  GT1_RXUSERRDY_IN : in std_logic;
184  -------------------------- RX Margin Analysis Ports ------------------------
185  GT1_EYESCANDATAERROR_OUT : out std_logic;
186  ------------------------- Receive Ports - CDR Ports ------------------------
187  GT1_RXCDRLOCK_OUT : out std_logic;
188  ------------------- Receive Ports - Clock Correction Ports -----------------
189  GT1_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
190  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
191  GT1_RXUSRCLK_IN : in std_logic;
192  GT1_RXUSRCLK2_IN : in std_logic;
193  ------------------ Receive Ports - FPGA RX interface Ports -----------------
194  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
195  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
196  GT1_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
197  GT1_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
198  --------------------------- Receive Ports - RX AFE -------------------------
199  GT1_GTXRXP_IN : in std_logic;
200  ------------------------ Receive Ports - RX AFE Ports ----------------------
201  GT1_GTXRXN_IN : in std_logic;
202  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
203  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
204  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
205  GT1_RXBYTEISALIGNED_OUT : out std_logic;
206  GT1_RXBYTEREALIGN_OUT : out std_logic;
207  GT1_RXCOMMADET_OUT : out std_logic;
208  GT1_RXMCOMMAALIGNEN_IN : in std_logic;
209  GT1_RXPCOMMAALIGNEN_IN : in std_logic;
210  ------------- Receive Ports - RX Initialization and Reset Ports ------------
211  GT1_GTRXRESET_IN : in std_logic;
212  GT1_RXPMARESET_IN : in std_logic;
213  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
214  GT1_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
215  GT1_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
216  -------------- Receive Ports -RX Initialization and Reset Ports ------------
217  GT1_RXRESETDONE_OUT : out std_logic;
218  --------------------- TX Initialization and Reset Ports --------------------
219  GT1_GTTXRESET_IN : in std_logic;
220  GT1_TXUSERRDY_IN : in std_logic;
221  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
222  GT1_TXUSRCLK_IN : in std_logic;
223  GT1_TXUSRCLK2_IN : in std_logic;
224  ------------------ Transmit Ports - TX Data Path interface -----------------
225  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
226  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
227  GT1_GTXTXN_OUT : out std_logic;
228  GT1_GTXTXP_OUT : out std_logic;
229  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
230  GT1_TXOUTCLK_OUT : out std_logic;
231  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
232  GT1_TXOUTCLKPCS_OUT : out std_logic;
233  --------------------- Transmit Ports - TX Gearbox Ports --------------------
234  GT1_TXCHARISK_IN : in std_logic_vector(3 downto 0);
235  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
236  GT1_TXRESETDONE_OUT : out std_logic;
237 
238  --GT2 (X1Y14)
239  --____________________________CHANNEL PORTS________________________________
240  ---------------------------- Channel - DRP Ports --------------------------
241  GT2_DRPADDR_IN : in std_logic_vector(8 downto 0);
242  GT2_DRPCLK_IN : in std_logic;
243  GT2_DRPDI_IN : in std_logic_vector(15 downto 0);
244  GT2_DRPDO_OUT : out std_logic_vector(15 downto 0);
245  GT2_DRPEN_IN : in std_logic;
246  GT2_DRPRDY_OUT : out std_logic;
247  GT2_DRPWE_IN : in std_logic;
248  ------------------------------ Power-Down Ports ----------------------------
249  GT2_RXPD_IN : in std_logic_vector(1 downto 0);
250  GT2_TXPD_IN : in std_logic_vector(1 downto 0);
251  --------------------- RX Initialization and Reset Ports --------------------
252  GT2_RXUSERRDY_IN : in std_logic;
253  -------------------------- RX Margin Analysis Ports ------------------------
254  GT2_EYESCANDATAERROR_OUT : out std_logic;
255  ------------------------- Receive Ports - CDR Ports ------------------------
256  GT2_RXCDRLOCK_OUT : out std_logic;
257  ------------------- Receive Ports - Clock Correction Ports -----------------
258  GT2_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
259  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
260  GT2_RXUSRCLK_IN : in std_logic;
261  GT2_RXUSRCLK2_IN : in std_logic;
262  ------------------ Receive Ports - FPGA RX interface Ports -----------------
263  GT2_RXDATA_OUT : out std_logic_vector(31 downto 0);
264  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
265  GT2_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
266  GT2_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
267  --------------------------- Receive Ports - RX AFE -------------------------
268  GT2_GTXRXP_IN : in std_logic;
269  ------------------------ Receive Ports - RX AFE Ports ----------------------
270  GT2_GTXRXN_IN : in std_logic;
271  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
272  GT2_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
273  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
274  GT2_RXBYTEISALIGNED_OUT : out std_logic;
275  GT2_RXBYTEREALIGN_OUT : out std_logic;
276  GT2_RXCOMMADET_OUT : out std_logic;
277  GT2_RXMCOMMAALIGNEN_IN : in std_logic;
278  GT2_RXPCOMMAALIGNEN_IN : in std_logic;
279  ------------- Receive Ports - RX Initialization and Reset Ports ------------
280  GT2_GTRXRESET_IN : in std_logic;
281  GT2_RXPMARESET_IN : in std_logic;
282  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
283  GT2_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
284  GT2_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
285  -------------- Receive Ports -RX Initialization and Reset Ports ------------
286  GT2_RXRESETDONE_OUT : out std_logic;
287  --------------------- TX Initialization and Reset Ports --------------------
288  GT2_GTTXRESET_IN : in std_logic;
289  GT2_TXUSERRDY_IN : in std_logic;
290  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
291  GT2_TXUSRCLK_IN : in std_logic;
292  GT2_TXUSRCLK2_IN : in std_logic;
293  ------------------ Transmit Ports - TX Data Path interface -----------------
294  GT2_TXDATA_IN : in std_logic_vector(31 downto 0);
295  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
296  GT2_GTXTXN_OUT : out std_logic;
297  GT2_GTXTXP_OUT : out std_logic;
298  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
299  GT2_TXOUTCLK_OUT : out std_logic;
300  GT2_TXOUTCLKFABRIC_OUT : out std_logic;
301  GT2_TXOUTCLKPCS_OUT : out std_logic;
302  --------------------- Transmit Ports - TX Gearbox Ports --------------------
303  GT2_TXCHARISK_IN : in std_logic_vector(3 downto 0);
304  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
305  GT2_TXRESETDONE_OUT : out std_logic;
306 
307 
308  --____________________________COMMON PORTS________________________________
309  ---------------------- Common Block - Ref Clock Ports ---------------------
310  GT0_GTREFCLK0_COMMON_IN : in std_logic;
311  ------------------------- Common Block - QPLL Ports ------------------------
312  GT0_QPLLLOCK_OUT : out std_logic;
313  GT0_QPLLLOCKDETCLK_IN : in std_logic;
314  GT0_QPLLRESET_IN : in std_logic
315 
316 
317 );
318 
319 end serdes5GpdProd_init;
320 
321 architecture RTL of serdes5GpdProd_init is
322 
323 --**************************Component Declarations*****************************
324 
325 
326 component serdes5GpdProd
327 generic
328 (
329  -- Simulation attributes
330  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to 1 to speed up sim reset
331 
332 );
333 port
334 (
335 
336  --_________________________________________________________________________
337  --_________________________________________________________________________
338  --GT0 (X1Y12)
339  --____________________________CHANNEL PORTS________________________________
340  ---------------------------- Channel - DRP Ports --------------------------
341  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
342  GT0_DRPCLK_IN : in std_logic;
343  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
344  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
345  GT0_DRPEN_IN : in std_logic;
346  GT0_DRPRDY_OUT : out std_logic;
347  GT0_DRPWE_IN : in std_logic;
348  ------------------------------ Power-Down Ports ----------------------------
349  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
350  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
351  --------------------- RX Initialization and Reset Ports --------------------
352  GT0_RXUSERRDY_IN : in std_logic;
353  -------------------------- RX Margin Analysis Ports ------------------------
354  GT0_EYESCANDATAERROR_OUT : out std_logic;
355  ------------------------- Receive Ports - CDR Ports ------------------------
356  GT0_RXCDRLOCK_OUT : out std_logic;
357  ------------------- Receive Ports - Clock Correction Ports -----------------
358  GT0_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
359  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
360  GT0_RXUSRCLK_IN : in std_logic;
361  GT0_RXUSRCLK2_IN : in std_logic;
362  ------------------ Receive Ports - FPGA RX interface Ports -----------------
363  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
364  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
365  GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
366  GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
367  --------------------------- Receive Ports - RX AFE -------------------------
368  GT0_GTXRXP_IN : in std_logic;
369  ------------------------ Receive Ports - RX AFE Ports ----------------------
370  GT0_GTXRXN_IN : in std_logic;
371  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
372  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
373  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
374  GT0_RXBYTEISALIGNED_OUT : out std_logic;
375  GT0_RXBYTEREALIGN_OUT : out std_logic;
376  GT0_RXCOMMADET_OUT : out std_logic;
377  GT0_RXMCOMMAALIGNEN_IN : in std_logic;
378  GT0_RXPCOMMAALIGNEN_IN : in std_logic;
379  --------------------- Receive Ports - RX Equalizer Ports -------------------
380  GT0_RXDFEAGCHOLD_IN : in std_logic;
381  GT0_RXDFELFHOLD_IN : in std_logic;
382  --------------- Receive Ports - RX Fabric Output Control Ports -------------
383  GT0_RXOUTCLK_OUT : out std_logic;
384  ------------- Receive Ports - RX Initialization and Reset Ports ------------
385  GT0_GTRXRESET_IN : in std_logic;
386  GT0_RXPMARESET_IN : in std_logic;
387  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
388  GT0_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
389  GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
390  -------------- Receive Ports -RX Initialization and Reset Ports ------------
391  GT0_RXRESETDONE_OUT : out std_logic;
392  --------------------- TX Initialization and Reset Ports --------------------
393  GT0_GTTXRESET_IN : in std_logic;
394  GT0_TXUSERRDY_IN : in std_logic;
395  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
396  GT0_TXUSRCLK_IN : in std_logic;
397  GT0_TXUSRCLK2_IN : in std_logic;
398  ------------------ Transmit Ports - TX Data Path interface -----------------
399  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
400  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
401  GT0_GTXTXN_OUT : out std_logic;
402  GT0_GTXTXP_OUT : out std_logic;
403  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
404  GT0_TXOUTCLK_OUT : out std_logic;
405  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
406  GT0_TXOUTCLKPCS_OUT : out std_logic;
407  --------------------- Transmit Ports - TX Gearbox Ports --------------------
408  GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
409  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
410  GT0_TXRESETDONE_OUT : out std_logic;
411 
412  --_________________________________________________________________________
413  --_________________________________________________________________________
414  --GT1 (X1Y13)
415  --____________________________CHANNEL PORTS________________________________
416  ---------------------------- Channel - DRP Ports --------------------------
417  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
418  GT1_DRPCLK_IN : in std_logic;
419  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
420  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
421  GT1_DRPEN_IN : in std_logic;
422  GT1_DRPRDY_OUT : out std_logic;
423  GT1_DRPWE_IN : in std_logic;
424  ------------------------------ Power-Down Ports ----------------------------
425  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
426  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
427  --------------------- RX Initialization and Reset Ports --------------------
428  GT1_RXUSERRDY_IN : in std_logic;
429  -------------------------- RX Margin Analysis Ports ------------------------
430  GT1_EYESCANDATAERROR_OUT : out std_logic;
431  ------------------------- Receive Ports - CDR Ports ------------------------
432  GT1_RXCDRLOCK_OUT : out std_logic;
433  ------------------- Receive Ports - Clock Correction Ports -----------------
434  GT1_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
435  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
436  GT1_RXUSRCLK_IN : in std_logic;
437  GT1_RXUSRCLK2_IN : in std_logic;
438  ------------------ Receive Ports - FPGA RX interface Ports -----------------
439  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
440  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
441  GT1_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
442  GT1_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
443  --------------------------- Receive Ports - RX AFE -------------------------
444  GT1_GTXRXP_IN : in std_logic;
445  ------------------------ Receive Ports - RX AFE Ports ----------------------
446  GT1_GTXRXN_IN : in std_logic;
447  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
448  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
449  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
450  GT1_RXBYTEISALIGNED_OUT : out std_logic;
451  GT1_RXBYTEREALIGN_OUT : out std_logic;
452  GT1_RXCOMMADET_OUT : out std_logic;
453  GT1_RXMCOMMAALIGNEN_IN : in std_logic;
454  GT1_RXPCOMMAALIGNEN_IN : in std_logic;
455  --------------------- Receive Ports - RX Equalizer Ports -------------------
456  GT1_RXDFEAGCHOLD_IN : in std_logic;
457  GT1_RXDFELFHOLD_IN : in std_logic;
458  --------------- Receive Ports - RX Fabric Output Control Ports -------------
459  GT1_RXOUTCLK_OUT : out std_logic;
460  ------------- Receive Ports - RX Initialization and Reset Ports ------------
461  GT1_GTRXRESET_IN : in std_logic;
462  GT1_RXPMARESET_IN : in std_logic;
463  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
464  GT1_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
465  GT1_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
466  -------------- Receive Ports -RX Initialization and Reset Ports ------------
467  GT1_RXRESETDONE_OUT : out std_logic;
468  --------------------- TX Initialization and Reset Ports --------------------
469  GT1_GTTXRESET_IN : in std_logic;
470  GT1_TXUSERRDY_IN : in std_logic;
471  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
472  GT1_TXUSRCLK_IN : in std_logic;
473  GT1_TXUSRCLK2_IN : in std_logic;
474  ------------------ Transmit Ports - TX Data Path interface -----------------
475  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
476  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
477  GT1_GTXTXN_OUT : out std_logic;
478  GT1_GTXTXP_OUT : out std_logic;
479  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
480  GT1_TXOUTCLK_OUT : out std_logic;
481  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
482  GT1_TXOUTCLKPCS_OUT : out std_logic;
483  --------------------- Transmit Ports - TX Gearbox Ports --------------------
484  GT1_TXCHARISK_IN : in std_logic_vector(3 downto 0);
485  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
486  GT1_TXRESETDONE_OUT : out std_logic;
487 
488  --_________________________________________________________________________
489  --_________________________________________________________________________
490  --GT2 (X1Y14)
491  --____________________________CHANNEL PORTS________________________________
492  ---------------------------- Channel - DRP Ports --------------------------
493  GT2_DRPADDR_IN : in std_logic_vector(8 downto 0);
494  GT2_DRPCLK_IN : in std_logic;
495  GT2_DRPDI_IN : in std_logic_vector(15 downto 0);
496  GT2_DRPDO_OUT : out std_logic_vector(15 downto 0);
497  GT2_DRPEN_IN : in std_logic;
498  GT2_DRPRDY_OUT : out std_logic;
499  GT2_DRPWE_IN : in std_logic;
500  ------------------------------ Power-Down Ports ----------------------------
501  GT2_RXPD_IN : in std_logic_vector(1 downto 0);
502  GT2_TXPD_IN : in std_logic_vector(1 downto 0);
503  --------------------- RX Initialization and Reset Ports --------------------
504  GT2_RXUSERRDY_IN : in std_logic;
505  -------------------------- RX Margin Analysis Ports ------------------------
506  GT2_EYESCANDATAERROR_OUT : out std_logic;
507  ------------------------- Receive Ports - CDR Ports ------------------------
508  GT2_RXCDRLOCK_OUT : out std_logic;
509  ------------------- Receive Ports - Clock Correction Ports -----------------
510  GT2_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
511  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
512  GT2_RXUSRCLK_IN : in std_logic;
513  GT2_RXUSRCLK2_IN : in std_logic;
514  ------------------ Receive Ports - FPGA RX interface Ports -----------------
515  GT2_RXDATA_OUT : out std_logic_vector(31 downto 0);
516  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
517  GT2_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
518  GT2_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
519  --------------------------- Receive Ports - RX AFE -------------------------
520  GT2_GTXRXP_IN : in std_logic;
521  ------------------------ Receive Ports - RX AFE Ports ----------------------
522  GT2_GTXRXN_IN : in std_logic;
523  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
524  GT2_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
525  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
526  GT2_RXBYTEISALIGNED_OUT : out std_logic;
527  GT2_RXBYTEREALIGN_OUT : out std_logic;
528  GT2_RXCOMMADET_OUT : out std_logic;
529  GT2_RXMCOMMAALIGNEN_IN : in std_logic;
530  GT2_RXPCOMMAALIGNEN_IN : in std_logic;
531  --------------------- Receive Ports - RX Equalizer Ports -------------------
532  GT2_RXDFEAGCHOLD_IN : in std_logic;
533  GT2_RXDFELFHOLD_IN : in std_logic;
534  --------------- Receive Ports - RX Fabric Output Control Ports -------------
535  GT2_RXOUTCLK_OUT : out std_logic;
536  ------------- Receive Ports - RX Initialization and Reset Ports ------------
537  GT2_GTRXRESET_IN : in std_logic;
538  GT2_RXPMARESET_IN : in std_logic;
539  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
540  GT2_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
541  GT2_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
542  -------------- Receive Ports -RX Initialization and Reset Ports ------------
543  GT2_RXRESETDONE_OUT : out std_logic;
544  --------------------- TX Initialization and Reset Ports --------------------
545  GT2_GTTXRESET_IN : in std_logic;
546  GT2_TXUSERRDY_IN : in std_logic;
547  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
548  GT2_TXUSRCLK_IN : in std_logic;
549  GT2_TXUSRCLK2_IN : in std_logic;
550  ------------------ Transmit Ports - TX Data Path interface -----------------
551  GT2_TXDATA_IN : in std_logic_vector(31 downto 0);
552  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
553  GT2_GTXTXN_OUT : out std_logic;
554  GT2_GTXTXP_OUT : out std_logic;
555  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
556  GT2_TXOUTCLK_OUT : out std_logic;
557  GT2_TXOUTCLKFABRIC_OUT : out std_logic;
558  GT2_TXOUTCLKPCS_OUT : out std_logic;
559  --------------------- Transmit Ports - TX Gearbox Ports --------------------
560  GT2_TXCHARISK_IN : in std_logic_vector(3 downto 0);
561  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
562  GT2_TXRESETDONE_OUT : out std_logic;
563 
564 
565  --____________________________COMMON PORTS________________________________
566  ---------------------- Common Block - Ref Clock Ports ---------------------
567  GT0_GTREFCLK0_COMMON_IN : in std_logic;
568  ------------------------- Common Block - QPLL Ports ------------------------
569  GT0_QPLLLOCK_OUT : out std_logic;
570  GT0_QPLLLOCKDETCLK_IN : in std_logic;
571  GT0_QPLLREFCLKLOST_OUT : out std_logic;
572  GT0_QPLLRESET_IN : in std_logic
573 
574 
575 );
576 end component;
577 
578 component serdes5GpdProd_TX_STARTUP_FSM
579  Generic(
580  GT_TYPE : string := "GTX";
581  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
582  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
583  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
584  RX_QPLL_USED : boolean := False; -- share these two generic values
585  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
586  -- is enough. For single-lane applications the automatic alignment is
587  -- sufficient
588  );
589  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
590  --or reference-clock present at startup.
591  TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
592  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
593  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
594  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
595  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
596  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
597  TXRESETDONE : in STD_LOGIC;
598  MMCM_LOCK : in STD_LOGIC;
599  GTTXRESET : out STD_LOGIC:='0';
600  MMCM_RESET : out STD_LOGIC:='0';
601  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
602  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
603  TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
604  TXUSERRDY : out STD_LOGIC:='0';
605  RUN_PHALIGNMENT : out STD_LOGIC:='0';
606  RESET_PHALIGNMENT : out STD_LOGIC:='0';
607  PHALIGNMENT_DONE : in STD_LOGIC;
608 
609  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
610  -- Retries it took to get the transceiver up and running
611  );
612 end component;
613 
614 component serdes5GpdProd_RX_STARTUP_FSM
615  Generic(
616  EXAMPLE_SIMULATION : integer := 0;
617  EQ_MODE : string := "DFE";
618  GT_TYPE : string := "GTX";
619  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
620  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
621  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
622  RX_QPLL_USED : boolean := False; -- share these two generic values
623  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
624  -- is enough. For single-lane applications the automatic alignment is
625  -- sufficient
626  );
627  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
628  --or reference-clock present at startup.
629  RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
630  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
631  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
632  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
633  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
634  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
635  RXRESETDONE : in STD_LOGIC;
636  MMCM_LOCK : in STD_LOGIC;
637  RECCLK_STABLE : in STD_LOGIC;
638  RECCLK_MONITOR_RESTART : in STD_LOGIC;
639  DATA_VALID : in STD_LOGIC;
640  TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
641  DONT_RESET_ON_DATA_ERROR : in STD_LOGIC;
642  GTRXRESET : out STD_LOGIC:='0';
643  MMCM_RESET : out STD_LOGIC:='0';
644  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
645  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
646  RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
647  RXUSERRDY : out STD_LOGIC:='0';
648  RUN_PHALIGNMENT : out STD_LOGIC;
649  PHALIGNMENT_DONE : in STD_LOGIC;
650  RESET_PHALIGNMENT : out STD_LOGIC:='0';
651  RXDFEAGCHOLD : out STD_LOGIC;
652  RXDFELFHOLD : out STD_LOGIC;
653  RXLPMLFHOLD : out STD_LOGIC;
654  RXLPMHFHOLD : out STD_LOGIC;
655  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
656  -- Retries it took to get the transceiver up and running
657  );
658 end component;
659 
660 
661 
662 
663 
664 
665  function get_cdrlock_time(is_sim : in integer) return integer is
666  variable lock_time: integer;
667  begin
668  if (is_sim = 1) then
669  lock_time := 1000;
670  else
671  lock_time := 50000 / integer(5); --Typical CDR lock time is 50,000UI as per DS183
672  end if;
673  return lock_time;
674  end function;
675 
676 
677 --***********************************Parameter Declarations********************
678 
679  constant DLY : time := 1 ns;
680  constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us
681  constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out
682 
683  -------------------------- GT Wrapper Wires ------------------------------
684  signal gt0_txresetdone_i : std_logic;
685  signal gt0_rxresetdone_i : std_logic;
686  signal gt0_gttxreset_i : std_logic;
687  signal gt0_gttxreset_t : std_logic;
688  signal gt0_gtrxreset_i : std_logic;
689  signal gt0_gtrxreset_t : std_logic;
690  signal gt0_rxdfelpmreset_i : std_logic;
691  signal gt0_txuserrdy_i : std_logic;
692  signal gt0_txuserrdy_t : std_logic;
693  signal gt0_rxuserrdy_i : std_logic;
694  signal gt0_rxuserrdy_t : std_logic;
695 
696  signal gt0_rxdfeagchold_i : std_logic;
697  signal gt0_rxdfelfhold_i : std_logic;
698  signal gt0_rxlpmlfhold_i : std_logic;
699  signal gt0_rxlpmhfhold_i : std_logic;
700 
701 
702  signal gt1_txresetdone_i : std_logic;
703  signal gt1_rxresetdone_i : std_logic;
704  signal gt1_gttxreset_i : std_logic;
705  signal gt1_gttxreset_t : std_logic;
706  signal gt1_gtrxreset_i : std_logic;
707  signal gt1_gtrxreset_t : std_logic;
708  signal gt1_rxdfelpmreset_i : std_logic;
709  signal gt1_txuserrdy_i : std_logic;
710  signal gt1_txuserrdy_t : std_logic;
711  signal gt1_rxuserrdy_i : std_logic;
712  signal gt1_rxuserrdy_t : std_logic;
713 
714  signal gt1_rxdfeagchold_i : std_logic;
715  signal gt1_rxdfelfhold_i : std_logic;
716  signal gt1_rxlpmlfhold_i : std_logic;
717  signal gt1_rxlpmhfhold_i : std_logic;
718 
719 
720  signal gt2_txresetdone_i : std_logic;
721  signal gt2_rxresetdone_i : std_logic;
722  signal gt2_gttxreset_i : std_logic;
723  signal gt2_gttxreset_t : std_logic;
724  signal gt2_gtrxreset_i : std_logic;
725  signal gt2_gtrxreset_t : std_logic;
726  signal gt2_rxdfelpmreset_i : std_logic;
727  signal gt2_txuserrdy_i : std_logic;
728  signal gt2_txuserrdy_t : std_logic;
729  signal gt2_rxuserrdy_i : std_logic;
730  signal gt2_rxuserrdy_t : std_logic;
731 
732  signal gt2_rxdfeagchold_i : std_logic;
733  signal gt2_rxdfelfhold_i : std_logic;
734  signal gt2_rxlpmlfhold_i : std_logic;
735  signal gt2_rxlpmhfhold_i : std_logic;
736 
737 
738 
739  signal gt0_qpllreset_i : std_logic;
740  signal gt0_qpllreset_t : std_logic;
741  signal gt0_qpllrefclklost_i : std_logic;
742  signal gt0_qplllock_i : std_logic;
743 
744 
745  ------------------------------- Global Signals -----------------------------
746  signal tied_to_ground_i : std_logic;
747  signal tied_to_vcc_i : std_logic;
748 
749  signal gt0_rxoutclk_i : std_logic;
750  signal gt0_recclk_stable_i : std_logic;
751 
752  signal gt1_rxoutclk_i : std_logic;
753  signal gt1_recclk_stable_i : std_logic;
754 
755  signal gt2_rxoutclk_i : std_logic;
756  signal gt2_recclk_stable_i : std_logic;
757 
758 
759 
760 
761 
762 
763  signal rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
764  signal rx_cdrlocked : std_logic;
765 
766 
767 
768 
769 
770 --**************************** Main Body of Code *******************************
771 begin
772  -- Static signal Assigments
773  tied_to_ground_i <= '0';
774  tied_to_vcc_i <= '1';
775 
776  ----------------------------- The GT Wrapper -----------------------------
777 
778  -- Use the instantiation template in the example directory to add the GT wrapper to your design.
779  -- In this example, the wrapper is wired up for basic operation with a frame generator and frame
780  -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
781  -- enabled, bonding should occur after alignment.
782 
783 
784  serdes5GpdProd_i : serdes5GpdProd
785  generic map
786  (
787  WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP
788  )
789  port map
790  (
791 
792  --_____________________________________________________________________
793  --_____________________________________________________________________
794  --GT0 (X1Y12)
795 
796  ---------------------------- Channel - DRP Ports --------------------------
797  GT0_DRPADDR_IN => GT0_DRPADDR_IN,
798  GT0_DRPCLK_IN => GT0_DRPCLK_IN,
799  GT0_DRPDI_IN => GT0_DRPDI_IN,
800  GT0_DRPDO_OUT => GT0_DRPDO_OUT,
801  GT0_DRPEN_IN => GT0_DRPEN_IN,
802  GT0_DRPRDY_OUT => GT0_DRPRDY_OUT,
803  GT0_DRPWE_IN => GT0_DRPWE_IN,
804  ------------------------------ Power-Down Ports ----------------------------
805  GT0_RXPD_IN => GT0_RXPD_IN,
806  GT0_TXPD_IN => GT0_TXPD_IN,
807  --------------------- RX Initialization and Reset Ports --------------------
808  GT0_RXUSERRDY_IN => gt0_rxuserrdy_i,
809  -------------------------- RX Margin Analysis Ports ------------------------
810  GT0_EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
811  ------------------------- Receive Ports - CDR Ports ------------------------
812  GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
813  ------------------- Receive Ports - Clock Correction Ports -----------------
814  GT0_RXCLKCORCNT_OUT => GT0_RXCLKCORCNT_OUT ,
815  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
816  GT0_RXUSRCLK_IN => GT0_RXUSRCLK_IN,
817  GT0_RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
818  ------------------ Receive Ports - FPGA RX interface Ports -----------------
819  GT0_RXDATA_OUT => GT0_RXDATA_OUT,
820  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
821  GT0_RXDISPERR_OUT => GT0_RXDISPERR_OUT,
822  GT0_RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT ,
823  --------------------------- Receive Ports - RX AFE -------------------------
824  GT0_GTXRXP_IN => GT0_GTXRXP_IN,
825  ------------------------ Receive Ports - RX AFE Ports ----------------------
826  GT0_GTXRXN_IN => GT0_GTXRXN_IN,
827  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
828  GT0_RXBUFSTATUS_OUT => GT0_RXBUFSTATUS_OUT ,
829  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
830  GT0_RXBYTEISALIGNED_OUT => GT0_RXBYTEISALIGNED_OUT ,
831  GT0_RXBYTEREALIGN_OUT => GT0_RXBYTEREALIGN_OUT ,
832  GT0_RXCOMMADET_OUT => GT0_RXCOMMADET_OUT,
833  GT0_RXMCOMMAALIGNEN_IN => GT0_RXMCOMMAALIGNEN_IN ,
834  GT0_RXPCOMMAALIGNEN_IN => GT0_RXPCOMMAALIGNEN_IN ,
835  --------------------- Receive Ports - RX Equalizer Ports -------------------
836  GT0_RXDFEAGCHOLD_IN => gt0_rxdfeagchold_i,
837  GT0_RXDFELFHOLD_IN => gt0_rxdfelfhold_i,
838  --------------- Receive Ports - RX Fabric Output Control Ports -------------
839  GT0_RXOUTCLK_OUT => gt0_rxoutclk_i,
840  ------------- Receive Ports - RX Initialization and Reset Ports ------------
841  GT0_GTRXRESET_IN => gt0_gtrxreset_i,
842  GT0_RXPMARESET_IN => GT0_RXPMARESET_IN,
843  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
844  GT0_RXCHARISCOMMA_OUT => GT0_RXCHARISCOMMA_OUT ,
845  GT0_RXCHARISK_OUT => GT0_RXCHARISK_OUT,
846  -------------- Receive Ports -RX Initialization and Reset Ports ------------
847  GT0_RXRESETDONE_OUT => gt0_rxresetdone_i,
848  --------------------- TX Initialization and Reset Ports --------------------
849  GT0_GTTXRESET_IN => gt0_gttxreset_i,
850  GT0_TXUSERRDY_IN => gt0_txuserrdy_i,
851  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
852  GT0_TXUSRCLK_IN => GT0_TXUSRCLK_IN,
853  GT0_TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
854  ------------------ Transmit Ports - TX Data Path interface -----------------
855  GT0_TXDATA_IN => GT0_TXDATA_IN,
856  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
857  GT0_GTXTXN_OUT => GT0_GTXTXN_OUT,
858  GT0_GTXTXP_OUT => GT0_GTXTXP_OUT,
859  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
860  GT0_TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
861  GT0_TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT ,
862  GT0_TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT ,
863  --------------------- Transmit Ports - TX Gearbox Ports --------------------
864  GT0_TXCHARISK_IN => GT0_TXCHARISK_IN,
865  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
866  GT0_TXRESETDONE_OUT => gt0_txresetdone_i,
867 
868 
869 
870  --_____________________________________________________________________
871  --_____________________________________________________________________
872  --GT1 (X1Y13)
873 
874  ---------------------------- Channel - DRP Ports --------------------------
875  GT1_DRPADDR_IN => GT1_DRPADDR_IN,
876  GT1_DRPCLK_IN => GT1_DRPCLK_IN,
877  GT1_DRPDI_IN => GT1_DRPDI_IN,
878  GT1_DRPDO_OUT => GT1_DRPDO_OUT,
879  GT1_DRPEN_IN => GT1_DRPEN_IN,
880  GT1_DRPRDY_OUT => GT1_DRPRDY_OUT,
881  GT1_DRPWE_IN => GT1_DRPWE_IN,
882  ------------------------------ Power-Down Ports ----------------------------
883  GT1_RXPD_IN => GT1_RXPD_IN,
884  GT1_TXPD_IN => GT1_TXPD_IN,
885  --------------------- RX Initialization and Reset Ports --------------------
886  GT1_RXUSERRDY_IN => gt1_rxuserrdy_i,
887  -------------------------- RX Margin Analysis Ports ------------------------
888  GT1_EYESCANDATAERROR_OUT => GT1_EYESCANDATAERROR_OUT,
889  ------------------------- Receive Ports - CDR Ports ------------------------
890  GT1_RXCDRLOCK_OUT => GT1_RXCDRLOCK_OUT,
891  ------------------- Receive Ports - Clock Correction Ports -----------------
892  GT1_RXCLKCORCNT_OUT => GT1_RXCLKCORCNT_OUT ,
893  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
894  GT1_RXUSRCLK_IN => GT1_RXUSRCLK_IN,
895  GT1_RXUSRCLK2_IN => GT1_RXUSRCLK2_IN,
896  ------------------ Receive Ports - FPGA RX interface Ports -----------------
897  GT1_RXDATA_OUT => GT1_RXDATA_OUT,
898  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
899  GT1_RXDISPERR_OUT => GT1_RXDISPERR_OUT,
900  GT1_RXNOTINTABLE_OUT => GT1_RXNOTINTABLE_OUT ,
901  --------------------------- Receive Ports - RX AFE -------------------------
902  GT1_GTXRXP_IN => GT1_GTXRXP_IN,
903  ------------------------ Receive Ports - RX AFE Ports ----------------------
904  GT1_GTXRXN_IN => GT1_GTXRXN_IN,
905  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
906  GT1_RXBUFSTATUS_OUT => GT1_RXBUFSTATUS_OUT ,
907  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
908  GT1_RXBYTEISALIGNED_OUT => GT1_RXBYTEISALIGNED_OUT ,
909  GT1_RXBYTEREALIGN_OUT => GT1_RXBYTEREALIGN_OUT ,
910  GT1_RXCOMMADET_OUT => GT1_RXCOMMADET_OUT,
911  GT1_RXMCOMMAALIGNEN_IN => GT1_RXMCOMMAALIGNEN_IN ,
912  GT1_RXPCOMMAALIGNEN_IN => GT1_RXPCOMMAALIGNEN_IN ,
913  --------------------- Receive Ports - RX Equalizer Ports -------------------
914  GT1_RXDFEAGCHOLD_IN => gt1_rxdfeagchold_i,
915  GT1_RXDFELFHOLD_IN => gt1_rxdfelfhold_i,
916  --------------- Receive Ports - RX Fabric Output Control Ports -------------
917  GT1_RXOUTCLK_OUT => gt1_rxoutclk_i,
918  ------------- Receive Ports - RX Initialization and Reset Ports ------------
919  GT1_GTRXRESET_IN => gt1_gtrxreset_i,
920  GT1_RXPMARESET_IN => GT1_RXPMARESET_IN,
921  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
922  GT1_RXCHARISCOMMA_OUT => GT1_RXCHARISCOMMA_OUT ,
923  GT1_RXCHARISK_OUT => GT1_RXCHARISK_OUT,
924  -------------- Receive Ports -RX Initialization and Reset Ports ------------
925  GT1_RXRESETDONE_OUT => gt1_rxresetdone_i,
926  --------------------- TX Initialization and Reset Ports --------------------
927  GT1_GTTXRESET_IN => gt1_gttxreset_i,
928  GT1_TXUSERRDY_IN => gt1_txuserrdy_i,
929  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
930  GT1_TXUSRCLK_IN => GT1_TXUSRCLK_IN,
931  GT1_TXUSRCLK2_IN => GT1_TXUSRCLK2_IN,
932  ------------------ Transmit Ports - TX Data Path interface -----------------
933  GT1_TXDATA_IN => GT1_TXDATA_IN,
934  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
935  GT1_GTXTXN_OUT => GT1_GTXTXN_OUT,
936  GT1_GTXTXP_OUT => GT1_GTXTXP_OUT,
937  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
938  GT1_TXOUTCLK_OUT => GT1_TXOUTCLK_OUT,
939  GT1_TXOUTCLKFABRIC_OUT => GT1_TXOUTCLKFABRIC_OUT ,
940  GT1_TXOUTCLKPCS_OUT => GT1_TXOUTCLKPCS_OUT ,
941  --------------------- Transmit Ports - TX Gearbox Ports --------------------
942  GT1_TXCHARISK_IN => GT1_TXCHARISK_IN,
943  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
944  GT1_TXRESETDONE_OUT => gt1_txresetdone_i,
945 
946 
947 
948  --_____________________________________________________________________
949  --_____________________________________________________________________
950  --GT2 (X1Y14)
951 
952  ---------------------------- Channel - DRP Ports --------------------------
953  GT2_DRPADDR_IN => GT2_DRPADDR_IN,
954  GT2_DRPCLK_IN => GT2_DRPCLK_IN,
955  GT2_DRPDI_IN => GT2_DRPDI_IN,
956  GT2_DRPDO_OUT => GT2_DRPDO_OUT,
957  GT2_DRPEN_IN => GT2_DRPEN_IN,
958  GT2_DRPRDY_OUT => GT2_DRPRDY_OUT,
959  GT2_DRPWE_IN => GT2_DRPWE_IN,
960  ------------------------------ Power-Down Ports ----------------------------
961  GT2_RXPD_IN => GT2_RXPD_IN,
962  GT2_TXPD_IN => GT2_TXPD_IN,
963  --------------------- RX Initialization and Reset Ports --------------------
964  GT2_RXUSERRDY_IN => gt2_rxuserrdy_i,
965  -------------------------- RX Margin Analysis Ports ------------------------
966  GT2_EYESCANDATAERROR_OUT => GT2_EYESCANDATAERROR_OUT,
967  ------------------------- Receive Ports - CDR Ports ------------------------
968  GT2_RXCDRLOCK_OUT => GT2_RXCDRLOCK_OUT,
969  ------------------- Receive Ports - Clock Correction Ports -----------------
970  GT2_RXCLKCORCNT_OUT => GT2_RXCLKCORCNT_OUT ,
971  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
972  GT2_RXUSRCLK_IN => GT2_RXUSRCLK_IN,
973  GT2_RXUSRCLK2_IN => GT2_RXUSRCLK2_IN,
974  ------------------ Receive Ports - FPGA RX interface Ports -----------------
975  GT2_RXDATA_OUT => GT2_RXDATA_OUT,
976  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
977  GT2_RXDISPERR_OUT => GT2_RXDISPERR_OUT,
978  GT2_RXNOTINTABLE_OUT => GT2_RXNOTINTABLE_OUT ,
979  --------------------------- Receive Ports - RX AFE -------------------------
980  GT2_GTXRXP_IN => GT2_GTXRXP_IN,
981  ------------------------ Receive Ports - RX AFE Ports ----------------------
982  GT2_GTXRXN_IN => GT2_GTXRXN_IN,
983  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
984  GT2_RXBUFSTATUS_OUT => GT2_RXBUFSTATUS_OUT ,
985  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
986  GT2_RXBYTEISALIGNED_OUT => GT2_RXBYTEISALIGNED_OUT ,
987  GT2_RXBYTEREALIGN_OUT => GT2_RXBYTEREALIGN_OUT ,
988  GT2_RXCOMMADET_OUT => GT2_RXCOMMADET_OUT,
989  GT2_RXMCOMMAALIGNEN_IN => GT2_RXMCOMMAALIGNEN_IN ,
990  GT2_RXPCOMMAALIGNEN_IN => GT2_RXPCOMMAALIGNEN_IN ,
991  --------------------- Receive Ports - RX Equalizer Ports -------------------
992  GT2_RXDFEAGCHOLD_IN => gt2_rxdfeagchold_i,
993  GT2_RXDFELFHOLD_IN => gt2_rxdfelfhold_i,
994  --------------- Receive Ports - RX Fabric Output Control Ports -------------
995  GT2_RXOUTCLK_OUT => gt2_rxoutclk_i,
996  ------------- Receive Ports - RX Initialization and Reset Ports ------------
997  GT2_GTRXRESET_IN => gt2_gtrxreset_i,
998  GT2_RXPMARESET_IN => GT2_RXPMARESET_IN,
999  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1000  GT2_RXCHARISCOMMA_OUT => GT2_RXCHARISCOMMA_OUT ,
1001  GT2_RXCHARISK_OUT => GT2_RXCHARISK_OUT,
1002  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1003  GT2_RXRESETDONE_OUT => gt2_rxresetdone_i,
1004  --------------------- TX Initialization and Reset Ports --------------------
1005  GT2_GTTXRESET_IN => gt2_gttxreset_i,
1006  GT2_TXUSERRDY_IN => gt2_txuserrdy_i,
1007  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1008  GT2_TXUSRCLK_IN => GT2_TXUSRCLK_IN,
1009  GT2_TXUSRCLK2_IN => GT2_TXUSRCLK2_IN,
1010  ------------------ Transmit Ports - TX Data Path interface -----------------
1011  GT2_TXDATA_IN => GT2_TXDATA_IN,
1012  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1013  GT2_GTXTXN_OUT => GT2_GTXTXN_OUT,
1014  GT2_GTXTXP_OUT => GT2_GTXTXP_OUT,
1015  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1016  GT2_TXOUTCLK_OUT => GT2_TXOUTCLK_OUT,
1017  GT2_TXOUTCLKFABRIC_OUT => GT2_TXOUTCLKFABRIC_OUT ,
1018  GT2_TXOUTCLKPCS_OUT => GT2_TXOUTCLKPCS_OUT ,
1019  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1020  GT2_TXCHARISK_IN => GT2_TXCHARISK_IN,
1021  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1022  GT2_TXRESETDONE_OUT => gt2_txresetdone_i,
1023 
1024 
1025 
1026 
1027  --____________________________COMMON PORTS________________________________
1028  ---------------------- Common Block - Ref Clock Ports ---------------------
1029  GT0_GTREFCLK0_COMMON_IN => GT0_GTREFCLK0_COMMON_IN ,
1030  ------------------------- Common Block - QPLL Ports ------------------------
1031  GT0_QPLLLOCK_OUT => gt0_qplllock_i,
1032  GT0_QPLLLOCKDETCLK_IN => GT0_QPLLLOCKDETCLK_IN ,
1033  GT0_QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i ,
1034  GT0_QPLLRESET_IN => gt0_qpllreset_i
1035 
1036  );
1037 
1038 
1039  gt0_rxdfelpmreset_i <= tied_to_ground_i;
1040  gt1_rxdfelpmreset_i <= tied_to_ground_i;
1041  gt2_rxdfelpmreset_i <= tied_to_ground_i;
1042 
1043 
1044 
1045 
1046  GT0_TXRESETDONE_OUT <= gt0_txresetdone_i;
1047  GT0_RXRESETDONE_OUT <= gt0_rxresetdone_i;
1048  GT1_TXRESETDONE_OUT <= gt1_txresetdone_i;
1049  GT1_RXRESETDONE_OUT <= gt1_rxresetdone_i;
1050  GT2_TXRESETDONE_OUT <= gt2_txresetdone_i;
1051  GT2_RXRESETDONE_OUT <= gt2_rxresetdone_i;
1052  GT0_QPLLLOCK_OUT <= gt0_qplllock_i;
1053 
1054 chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
1055  gt0_gttxreset_i <= GT0_GTTXRESET_IN or gt0_gttxreset_t;
1056  gt0_gtrxreset_i <= GT0_GTRXRESET_IN or gt0_gtrxreset_t;
1057  gt0_txuserrdy_i <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t;
1058  gt0_rxuserrdy_i <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t;
1059  gt1_gttxreset_i <= GT1_GTTXRESET_IN or gt1_gttxreset_t;
1060  gt1_gtrxreset_i <= GT1_GTRXRESET_IN or gt1_gtrxreset_t;
1061  gt1_txuserrdy_i <= GT1_TXUSERRDY_IN or gt1_txuserrdy_t;
1062  gt1_rxuserrdy_i <= GT1_RXUSERRDY_IN or gt1_rxuserrdy_t;
1063  gt2_gttxreset_i <= GT2_GTTXRESET_IN or gt2_gttxreset_t;
1064  gt2_gtrxreset_i <= GT2_GTRXRESET_IN or gt2_gtrxreset_t;
1065  gt2_txuserrdy_i <= GT2_TXUSERRDY_IN or gt2_txuserrdy_t;
1066  gt2_rxuserrdy_i <= GT2_RXUSERRDY_IN or gt2_rxuserrdy_t;
1067  gt0_qpllreset_i <= GT0_QPLLRESET_IN or gt0_qpllreset_t;
1068 end generate chipscope;
1069 
1070 no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
1071  gt0_gttxreset_i <= gt0_gttxreset_t;
1072  gt0_gtrxreset_i <= gt0_gtrxreset_t;
1073  gt0_txuserrdy_i <= gt0_txuserrdy_t;
1074  gt0_rxuserrdy_i <= gt0_rxuserrdy_t;
1075  gt1_gttxreset_i <= gt1_gttxreset_t;
1076  gt1_gtrxreset_i <= gt1_gtrxreset_t;
1077  gt1_txuserrdy_i <= gt1_txuserrdy_t;
1078  gt1_rxuserrdy_i <= gt1_rxuserrdy_t;
1079  gt2_gttxreset_i <= gt2_gttxreset_t;
1080  gt2_gtrxreset_i <= gt2_gtrxreset_t;
1081  gt2_txuserrdy_i <= gt2_txuserrdy_t;
1082  gt2_rxuserrdy_i <= gt2_rxuserrdy_t;
1083  gt0_qpllreset_i <= gt0_qpllreset_t;
1084 end generate no_chipscope;
1085 
1086 
1087 gt0_txresetfsm_i: serdes5GpdProd_TX_STARTUP_FSM
1088 
1089  generic map(
1090  GT_TYPE => "GTX", --GTX or GTH or GTP
1091  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
1092  RETRY_COUNTER_BITWIDTH => 8,
1093  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
1094  RX_QPLL_USED => TRUE, -- share these two generic values
1095  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
1096  -- is enough. For single-lane applications the automatic alignment is
1097  -- sufficient
1098  )
1099  port map (
1100  STABLE_CLOCK => SYSCLK_IN,
1101  TXUSERCLK => GT0_TXUSRCLK_IN,
1102  SOFT_RESET => SOFT_RESET_IN,
1103  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
1104  CPLLREFCLKLOST => tied_to_ground_i,
1105  QPLLLOCK => gt0_qplllock_i,
1106  CPLLLOCK => tied_to_vcc_i,
1107  TXRESETDONE => gt0_txresetdone_i,
1108  MMCM_LOCK => tied_to_vcc_i,
1109  GTTXRESET => gt0_gttxreset_t,
1110  MMCM_RESET => open,
1111  QPLL_RESET => gt0_qpllreset_t,
1112  CPLL_RESET => open,
1113  TX_FSM_RESET_DONE => GT0_TX_FSM_RESET_DONE_OUT,
1114  TXUSERRDY => gt0_txuserrdy_t,
1115  RUN_PHALIGNMENT => open,
1116  RESET_PHALIGNMENT => open,
1117  PHALIGNMENT_DONE => tied_to_vcc_i,
1118  RETRY_COUNTER => open
1119  );
1120 
1121 
1122 gt1_txresetfsm_i: serdes5GpdProd_TX_STARTUP_FSM
1123 
1124  generic map(
1125  GT_TYPE => "GTX", --GTX or GTH or GTP
1126  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
1127  RETRY_COUNTER_BITWIDTH => 8,
1128  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
1129  RX_QPLL_USED => TRUE, -- share these two generic values
1130  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
1131  -- is enough. For single-lane applications the automatic alignment is
1132  -- sufficient
1133  )
1134  port map (
1135  STABLE_CLOCK => SYSCLK_IN,
1136  TXUSERCLK => GT1_TXUSRCLK_IN,
1137  SOFT_RESET => SOFT_RESET_IN,
1138  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
1139  CPLLREFCLKLOST => tied_to_ground_i,
1140  QPLLLOCK => gt0_qplllock_i,
1141  CPLLLOCK => tied_to_vcc_i,
1142  TXRESETDONE => gt1_txresetdone_i,
1143  MMCM_LOCK => tied_to_vcc_i,
1144  GTTXRESET => gt1_gttxreset_t,
1145  MMCM_RESET => open,
1146  QPLL_RESET => open,
1147  CPLL_RESET => open,
1148  TX_FSM_RESET_DONE => GT1_TX_FSM_RESET_DONE_OUT,
1149  TXUSERRDY => gt1_txuserrdy_t,
1150  RUN_PHALIGNMENT => open,
1151  RESET_PHALIGNMENT => open,
1152  PHALIGNMENT_DONE => tied_to_vcc_i,
1153  RETRY_COUNTER => open
1154  );
1155 
1156 
1157 gt2_txresetfsm_i: serdes5GpdProd_TX_STARTUP_FSM
1158 
1159  generic map(
1160  GT_TYPE => "GTX", --GTX or GTH or GTP
1161  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
1162  RETRY_COUNTER_BITWIDTH => 8,
1163  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
1164  RX_QPLL_USED => TRUE, -- share these two generic values
1165  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
1166  -- is enough. For single-lane applications the automatic alignment is
1167  -- sufficient
1168  )
1169  port map (
1170  STABLE_CLOCK => SYSCLK_IN,
1171  TXUSERCLK => GT2_TXUSRCLK_IN,
1172  SOFT_RESET => SOFT_RESET_IN,
1173  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
1174  CPLLREFCLKLOST => tied_to_ground_i,
1175  QPLLLOCK => gt0_qplllock_i,
1176  CPLLLOCK => tied_to_vcc_i,
1177  TXRESETDONE => gt2_txresetdone_i,
1178  MMCM_LOCK => tied_to_vcc_i,
1179  GTTXRESET => gt2_gttxreset_t,
1180  MMCM_RESET => open,
1181  QPLL_RESET => open,
1182  CPLL_RESET => open,
1183  TX_FSM_RESET_DONE => GT2_TX_FSM_RESET_DONE_OUT,
1184  TXUSERRDY => gt2_txuserrdy_t,
1185  RUN_PHALIGNMENT => open,
1186  RESET_PHALIGNMENT => open,
1187  PHALIGNMENT_DONE => tied_to_vcc_i,
1188  RETRY_COUNTER => open
1189  );
1190 
1191 
1192 
1193 
1194 
1195 
1196 gt0_rxresetfsm_i: serdes5GpdProd_RX_STARTUP_FSM
1197 
1198  generic map(
1199  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
1200  GT_TYPE => "GTX", --GTX or GTH or GTP
1201  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
1202  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
1203  RETRY_COUNTER_BITWIDTH => 8,
1204  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
1205  RX_QPLL_USED => TRUE, -- share these two generic values
1206  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
1207  -- is enough. For single-lane applications the automatic alignment is
1208  -- sufficient
1209  )
1210  port map (
1211  STABLE_CLOCK => SYSCLK_IN,
1212  RXUSERCLK => GT0_RXUSRCLK_IN,
1213  SOFT_RESET => SOFT_RESET_IN,
1214  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
1215  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
1216  CPLLREFCLKLOST => tied_to_ground_i,
1217  QPLLLOCK => gt0_qplllock_i,
1218  CPLLLOCK => tied_to_vcc_i,
1219  RXRESETDONE => gt0_rxresetdone_i,
1220  MMCM_LOCK => tied_to_vcc_i,
1221  RECCLK_STABLE => gt0_recclk_stable_i ,
1222  RECCLK_MONITOR_RESTART => tied_to_ground_i,
1223  DATA_VALID => GT0_DATA_VALID_IN,
1224  TXUSERRDY => gt0_txuserrdy_i,
1225  GTRXRESET => gt0_gtrxreset_t,
1226  MMCM_RESET => open,
1227  QPLL_RESET => open,
1228  CPLL_RESET => open,
1229  RX_FSM_RESET_DONE => GT0_RX_FSM_RESET_DONE_OUT ,
1230  RXUSERRDY => gt0_rxuserrdy_t,
1231  RUN_PHALIGNMENT => open,
1232  RESET_PHALIGNMENT => open,
1233  PHALIGNMENT_DONE => tied_to_vcc_i,
1234  RXDFEAGCHOLD => gt0_rxdfeagchold_i ,
1235  RXDFELFHOLD => gt0_rxdfelfhold_i,
1236  RXLPMLFHOLD => gt0_rxlpmlfhold_i,
1237  RXLPMHFHOLD => gt0_rxlpmhfhold_i,
1238  RETRY_COUNTER => open
1239  );
1240 
1241 gt1_rxresetfsm_i: serdes5GpdProd_RX_STARTUP_FSM
1242 
1243  generic map(
1244  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
1245  GT_TYPE => "GTX", --GTX or GTH or GTP
1246  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
1247  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
1248  RETRY_COUNTER_BITWIDTH => 8,
1249  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
1250  RX_QPLL_USED => TRUE, -- share these two generic values
1251  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
1252  -- is enough. For single-lane applications the automatic alignment is
1253  -- sufficient
1254  )
1255  port map (
1256  STABLE_CLOCK => SYSCLK_IN,
1257  RXUSERCLK => GT1_RXUSRCLK_IN,
1258  SOFT_RESET => SOFT_RESET_IN,
1259  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
1260  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
1261  CPLLREFCLKLOST => tied_to_ground_i,
1262  QPLLLOCK => gt0_qplllock_i,
1263  CPLLLOCK => tied_to_vcc_i,
1264  RXRESETDONE => gt1_rxresetdone_i,
1265  MMCM_LOCK => tied_to_vcc_i,
1266  RECCLK_STABLE => gt1_recclk_stable_i ,
1267  RECCLK_MONITOR_RESTART => tied_to_ground_i,
1268  DATA_VALID => GT1_DATA_VALID_IN,
1269  TXUSERRDY => gt1_txuserrdy_i,
1270  GTRXRESET => gt1_gtrxreset_t,
1271  MMCM_RESET => open,
1272  QPLL_RESET => open,
1273  CPLL_RESET => open,
1274  RX_FSM_RESET_DONE => GT1_RX_FSM_RESET_DONE_OUT ,
1275  RXUSERRDY => gt1_rxuserrdy_t,
1276  RUN_PHALIGNMENT => open,
1277  RESET_PHALIGNMENT => open,
1278  PHALIGNMENT_DONE => tied_to_vcc_i,
1279  RXDFEAGCHOLD => gt1_rxdfeagchold_i ,
1280  RXDFELFHOLD => gt1_rxdfelfhold_i,
1281  RXLPMLFHOLD => gt1_rxlpmlfhold_i,
1282  RXLPMHFHOLD => gt1_rxlpmhfhold_i,
1283  RETRY_COUNTER => open
1284  );
1285 
1286 gt2_rxresetfsm_i: serdes5GpdProd_RX_STARTUP_FSM
1287 
1288  generic map(
1289  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
1290  GT_TYPE => "GTX", --GTX or GTH or GTP
1291  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
1292  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
1293  RETRY_COUNTER_BITWIDTH => 8,
1294  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
1295  RX_QPLL_USED => TRUE, -- share these two generic values
1296  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
1297  -- is enough. For single-lane applications the automatic alignment is
1298  -- sufficient
1299  )
1300  port map (
1301  STABLE_CLOCK => SYSCLK_IN,
1302  RXUSERCLK => GT2_RXUSRCLK_IN,
1303  SOFT_RESET => SOFT_RESET_IN,
1304  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
1305  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
1306  CPLLREFCLKLOST => tied_to_ground_i,
1307  QPLLLOCK => gt0_qplllock_i,
1308  CPLLLOCK => tied_to_vcc_i,
1309  RXRESETDONE => gt2_rxresetdone_i,
1310  MMCM_LOCK => tied_to_vcc_i,
1311  RECCLK_STABLE => gt2_recclk_stable_i ,
1312  RECCLK_MONITOR_RESTART => tied_to_ground_i,
1313  DATA_VALID => GT2_DATA_VALID_IN,
1314  TXUSERRDY => gt2_txuserrdy_i,
1315  GTRXRESET => gt2_gtrxreset_t,
1316  MMCM_RESET => open,
1317  QPLL_RESET => open,
1318  CPLL_RESET => open,
1319  RX_FSM_RESET_DONE => GT2_RX_FSM_RESET_DONE_OUT ,
1320  RXUSERRDY => gt2_rxuserrdy_t,
1321  RUN_PHALIGNMENT => open,
1322  RESET_PHALIGNMENT => open,
1323  PHALIGNMENT_DONE => tied_to_vcc_i,
1324  RXDFEAGCHOLD => gt2_rxdfeagchold_i ,
1325  RXDFELFHOLD => gt2_rxdfelfhold_i,
1326  RXLPMLFHOLD => gt2_rxlpmlfhold_i,
1327  RXLPMHFHOLD => gt2_rxlpmhfhold_i,
1328  RETRY_COUNTER => open
1329  );
1330 
1331 
1332 
1333  cdrlock_timeout:process(SYSCLK_IN)
1334  begin
1335  if rising_edge(SYSCLK_IN) then
1336  if(gt0_gtrxreset_i = '1') then
1337  rx_cdrlocked <= '0';
1338  rx_cdrlock_counter <= 0 after DLY;
1339  elsif (rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
1340  rx_cdrlocked <= '1';
1341  rx_cdrlock_counter <= rx_cdrlock_counter after DLY;
1342  else
1343  rx_cdrlock_counter <= rx_cdrlock_counter + 1 after DLY;
1344  end if;
1345  end if;
1346  end process;
1347 
1348 gt0_recclk_stable_i <= rx_cdrlocked;
1349 gt1_recclk_stable_i <= rx_cdrlocked;
1350 gt2_recclk_stable_i <= rx_cdrlocked;
1351 
1352 
1353 
1354 
1355 
1356 
1357 
1358 end RTL;
1359 
1360 
Generated on Wed Apr 18 2018 10:55:26 for AMC13 by   doxygen 1.8.1