AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
s6link_gt.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.5
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : s6link_gt.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module S6Link_GT (a GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 library UNISIM;
68 use UNISIM.VCOMPONENTS.ALL;
69 
70 --***************************** Entity Declaration ****************************
71 
72 entity S6Link_GT is
73 generic
74 (
75  -- Simulation attributes
76  GT_SIM_GTRESET_SPEEDUP : string := "false"; -- Set to "true" to speed up sim reset
77  RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
78  PMA_RSV_IN : bit_vector := x"00018480";
79  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000";
80  SIM_VERSION : string := "4.0"
81 );
82 port
83 (
84  --------------------------------- CPLL Ports -------------------------------
85  CPLLFBCLKLOST_OUT : out std_logic;
86  CPLLLOCK_OUT : out std_logic;
87  CPLLLOCKDETCLK_IN : in std_logic;
88  CPLLREFCLKLOST_OUT : out std_logic;
89  CPLLRESET_IN : in std_logic;
90  -------------------------- Channel - Clocking Ports ------------------------
91  GTREFCLK0_IN : in std_logic;
92  ---------------------------- Channel - DRP Ports --------------------------
93  DRPADDR_IN : in std_logic_vector(8 downto 0);
94  DRPCLK_IN : in std_logic;
95  DRPDI_IN : in std_logic_vector(15 downto 0);
96  DRPDO_OUT : out std_logic_vector(15 downto 0);
97  DRPEN_IN : in std_logic;
98  DRPRDY_OUT : out std_logic;
99  DRPWE_IN : in std_logic;
100  ------------------------------- Clocking Ports -----------------------------
101  QPLLCLK_IN : in std_logic;
102  QPLLREFCLK_IN : in std_logic;
103  --------------------- RX Initialization and Reset Ports --------------------
104  RXUSERRDY_IN : in std_logic;
105  -------------------------- RX Margin Analysis Ports ------------------------
106  EYESCANDATAERROR_OUT : out std_logic;
107  ------------------------- Receive Ports - CDR Ports ------------------------
108  RXCDRLOCK_OUT : out std_logic;
109  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
110  RXUSRCLK_IN : in std_logic;
111  RXUSRCLK2_IN : in std_logic;
112  ------------------ Receive Ports - FPGA RX interface Ports -----------------
113  RXDATA_OUT : out std_logic_vector(15 downto 0);
114  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
115  RXDISPERR_OUT : out std_logic_vector(1 downto 0);
116  RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
117  --------------------------- Receive Ports - RX AFE -------------------------
118  GTXRXP_IN : in std_logic;
119  ------------------------ Receive Ports - RX AFE Ports ----------------------
120  GTXRXN_IN : in std_logic;
121  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
122  RXMCOMMAALIGNEN_IN : in std_logic;
123  RXPCOMMAALIGNEN_IN : in std_logic;
124  --------------------- Receive Ports - RX Equalizer Ports -------------------
125  RXDFELPMRESET_IN : in std_logic;
126  --------------------- Receive Ports - RX Equilizer Ports -------------------
127  RXLPMHFHOLD_IN : in std_logic;
128  RXLPMLFHOLD_IN : in std_logic;
129  --------------- Receive Ports - RX Fabric Output Control Ports -------------
130  RXOUTCLK_OUT : out std_logic;
131  ------------- Receive Ports - RX Initialization and Reset Ports ------------
132  GTRXRESET_IN : in std_logic;
133  RXPMARESET_IN : in std_logic;
134  ----------------- Receive Ports - RX Polarity Control Ports ----------------
135  RXPOLARITY_IN : in std_logic;
136  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
137  RXCHARISK_OUT : out std_logic_vector(1 downto 0);
138  -------------- Receive Ports -RX Initialization and Reset Ports ------------
139  RXRESETDONE_OUT : out std_logic;
140  --------------------- TX Initialization and Reset Ports --------------------
141  GTTXRESET_IN : in std_logic;
142  TXUSERRDY_IN : in std_logic;
143  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
144  TXUSRCLK_IN : in std_logic;
145  TXUSRCLK2_IN : in std_logic;
146  ------------------ Transmit Ports - TX Data Path interface -----------------
147  TXDATA_IN : in std_logic_vector(15 downto 0);
148  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
149  GTXTXN_OUT : out std_logic;
150  GTXTXP_OUT : out std_logic;
151  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
152  TXOUTCLK_OUT : out std_logic;
153  TXOUTCLKFABRIC_OUT : out std_logic;
154  TXOUTCLKPCS_OUT : out std_logic;
155  --------------------- Transmit Ports - TX Gearbox Ports --------------------
156  TXCHARISK_IN : in std_logic_vector(1 downto 0);
157  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
158  TXRESETDONE_OUT : out std_logic;
159  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
160  TXPOLARITY_IN : in std_logic
161 
162 
163 );
164 
165 
166 end S6Link_GT;
167 
168 architecture RTL of S6Link_GT is
169 
170 --**************************** Signal Declarations ****************************
171 
172  -- ground and tied_to_vcc_i signals
173  signal tied_to_ground_i : std_logic;
174  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
175  signal tied_to_vcc_i : std_logic;
176 
177 
178 
179  -- RX Datapath signals
180  signal rxdata_i : std_logic_vector(63 downto 0);
181  signal rxchariscomma_float_i : std_logic_vector(5 downto 0);
182  signal rxcharisk_float_i : std_logic_vector(5 downto 0);
183  signal rxdisperr_float_i : std_logic_vector(5 downto 0);
184  signal rxnotintable_float_i : std_logic_vector(5 downto 0);
185  signal rxrundisp_float_i : std_logic_vector(5 downto 0);
186 
187 
188 
189  -- TX Datapath signals
190  signal txdata_i : std_logic_vector(63 downto 0);
191  signal txkerr_float_i : std_logic_vector(5 downto 0);
192  signal txrundisp_float_i : std_logic_vector(5 downto 0);
193 
194 
195 --******************************** Main Body of Code***************************
196 
197 begin
198 
199  --------------------------- Static signal Assignments ---------------------
200 
201  tied_to_ground_i <= '0';
202  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
203  tied_to_vcc_i <= '1';
204 
205  ------------------- GT Datapath byte mapping -----------------
206 
207  RXDATA_OUT <= rxdata_i(15 downto 0);
208 
209  txdata_i <= (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN);
210 
211 
212 
213  ----------------------------- GTXE2 Instance --------------------------
214 
215  gtxe2_i :GTXE2_CHANNEL
216  generic map
217  (
218 
219  --_______________________ Simulation-Only Attributes ___________________
220 
221  SIM_RECEIVER_DETECT_PASS => ("TRUE"),
222  SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP),
223  SIM_TX_EIDLE_DRIVE_LEVEL => ("X"),
224  SIM_CPLLREFCLK_SEL => ("001"),
225  SIM_VERSION => (SIM_VERSION),
226 
227 
228  ------------------RX Byte and Word Alignment Attributes---------------
229  ALIGN_COMMA_DOUBLE => ("FALSE"),
230  ALIGN_COMMA_ENABLE => ("1111111111"),
231  ALIGN_COMMA_WORD => (2),
232  ALIGN_MCOMMA_DET => ("TRUE"),
233  ALIGN_MCOMMA_VALUE => ("1010000011"),
234  ALIGN_PCOMMA_DET => ("TRUE"),
235  ALIGN_PCOMMA_VALUE => ("0101111100"),
236  SHOW_REALIGN_COMMA => ("TRUE"),
237  RXSLIDE_AUTO_WAIT => (7),
238  RXSLIDE_MODE => ("OFF"),
239  RX_SIG_VALID_DLY => (10),
240 
241  ------------------RX 8B/10B Decoder Attributes---------------
242  RX_DISPERR_SEQ_MATCH => ("TRUE"),
243  DEC_MCOMMA_DETECT => ("TRUE"),
244  DEC_PCOMMA_DETECT => ("TRUE"),
245  DEC_VALID_COMMA_ONLY => ("FALSE"),
246 
247  ------------------------RX Clock Correction Attributes----------------------
248  CBCC_DATA_SOURCE_SEL => ("DECODED"),
249  CLK_COR_SEQ_2_USE => ("FALSE"),
250  CLK_COR_KEEP_IDLE => ("FALSE"),
251  CLK_COR_MAX_LAT => (10),
252  CLK_COR_MIN_LAT => (8),
253  CLK_COR_PRECEDENCE => ("TRUE"),
254  CLK_COR_REPEAT_WAIT => (0),
255  CLK_COR_SEQ_LEN => (1),
256  CLK_COR_SEQ_1_ENABLE => ("1111"),
257  CLK_COR_SEQ_1_1 => ("0000000000"),
258  CLK_COR_SEQ_1_2 => ("0000000000"),
259  CLK_COR_SEQ_1_3 => ("0000000000"),
260  CLK_COR_SEQ_1_4 => ("0000000000"),
261  CLK_CORRECT_USE => ("FALSE"),
262  CLK_COR_SEQ_2_ENABLE => ("1111"),
263  CLK_COR_SEQ_2_1 => ("0000000000"),
264  CLK_COR_SEQ_2_2 => ("0000000000"),
265  CLK_COR_SEQ_2_3 => ("0000000000"),
266  CLK_COR_SEQ_2_4 => ("0000000000"),
267 
268  ------------------------RX Channel Bonding Attributes----------------------
269  CHAN_BOND_KEEP_ALIGN => ("FALSE"),
270  CHAN_BOND_MAX_SKEW => (1),
271  CHAN_BOND_SEQ_LEN => (1),
272  CHAN_BOND_SEQ_1_1 => ("0000000000"),
273  CHAN_BOND_SEQ_1_2 => ("0000000000"),
274  CHAN_BOND_SEQ_1_3 => ("0000000000"),
275  CHAN_BOND_SEQ_1_4 => ("0000000000"),
276  CHAN_BOND_SEQ_1_ENABLE => ("1111"),
277  CHAN_BOND_SEQ_2_1 => ("0000000000"),
278  CHAN_BOND_SEQ_2_2 => ("0000000000"),
279  CHAN_BOND_SEQ_2_3 => ("0000000000"),
280  CHAN_BOND_SEQ_2_4 => ("0000000000"),
281  CHAN_BOND_SEQ_2_ENABLE => ("1111"),
282  CHAN_BOND_SEQ_2_USE => ("FALSE"),
283  FTS_DESKEW_SEQ_ENABLE => ("1111"),
284  FTS_LANE_DESKEW_CFG => ("1111"),
285  FTS_LANE_DESKEW_EN => ("FALSE"),
286 
287  ---------------------------RX Margin Analysis Attributes----------------------------
288  ES_CONTROL => ("000000"),
289  ES_ERRDET_EN => ("FALSE"),
290  ES_EYE_SCAN_EN => ("TRUE"),
291  ES_HORZ_OFFSET => (x"000"),
292  ES_PMA_CFG => ("0000000000"),
293  ES_PRESCALE => ("00000"),
294  ES_QUALIFIER => (x"00000000000000000000"),
295  ES_QUAL_MASK => (x"00000000000000000000"),
296  ES_SDATA_MASK => (x"00000000000000000000"),
297  ES_VERT_OFFSET => ("000000000"),
298 
299  -------------------------FPGA RX Interface Attributes-------------------------
300  RX_DATA_WIDTH => (20),
301 
302  ---------------------------PMA Attributes----------------------------
303  OUTREFCLK_SEL_INV => ("11"),
304  PMA_RSV => (PMA_RSV_IN),
305  PMA_RSV2 => (x"2040"),
306  PMA_RSV3 => ("00"),
307  PMA_RSV4 => (x"00000000"),
308  RX_BIAS_CFG => ("000000000100"),
309  DMONITOR_CFG => (x"000A00"),
310  RX_CM_SEL => ("00"),
311  RX_CM_TRIM => ("000"),
312  RX_DEBUG_CFG => ("000000000000"),
313  RX_OS_CFG => ("0000010000000"),
314  TERM_RCAL_CFG => ("10000"),
315  TERM_RCAL_OVRD => ('0'),
316  TST_RSV => (x"00000000"),
317  RX_CLK25_DIV => (5),
318  TX_CLK25_DIV => (5),
319  UCODEER_CLR => ('0'),
320 
321  ---------------------------PCI Express Attributes----------------------------
322  PCS_PCIE_EN => ("FALSE"),
323 
324  ---------------------------PCS Attributes----------------------------
325  PCS_RSVD_ATTR => (PCS_RSVD_ATTR_IN),
326 
327  -------------RX Buffer Attributes------------
328  RXBUF_ADDR_MODE => ("FAST"),
329  RXBUF_EIDLE_HI_CNT => ("1000"),
330  RXBUF_EIDLE_LO_CNT => ("0000"),
331  RXBUF_EN => ("TRUE"),
332  RX_BUFFER_CFG => ("000000"),
333  RXBUF_RESET_ON_CB_CHANGE => ("TRUE"),
334  RXBUF_RESET_ON_COMMAALIGN => ("FALSE"),
335  RXBUF_RESET_ON_EIDLE => ("FALSE"),
336  RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
337  RXBUFRESET_TIME => ("00001"),
338  RXBUF_THRESH_OVFLW => (61),
339  RXBUF_THRESH_OVRD => ("FALSE"),
340  RXBUF_THRESH_UNDFLW => (4),
341  RXDLY_CFG => (x"001F"),
342  RXDLY_LCFG => (x"030"),
343  RXDLY_TAP_CFG => (x"0000"),
344  RXPH_CFG => (x"000000"),
345  RXPHDLY_CFG => (x"084020"),
346  RXPH_MONITOR_SEL => ("00000"),
347  RX_XCLK_SEL => ("RXREC"),
348  RX_DDI_SEL => ("000000"),
349  RX_DEFER_RESET_BUF_EN => ("TRUE"),
350 
351  -----------------------CDR Attributes-------------------------
352 
353  --For GTX only: Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200002
354 
355  --For GTX only: Display Port, HBR2 - set RXCDR_CFG=72'h03000023ff10200020
356  RXCDR_CFG => (x"03000023ff10200020"),
357  RXCDR_FR_RESET_ON_EIDLE => ('0'),
358  RXCDR_HOLD_DURING_EIDLE => ('0'),
359  RXCDR_PH_RESET_ON_EIDLE => ('0'),
360  RXCDR_LOCK_CFG => ("010101"),
361 
362  -------------------RX Initialization and Reset Attributes-------------------
363  RXCDRFREQRESET_TIME => ("00001"),
364  RXCDRPHRESET_TIME => ("00001"),
365  RXISCANRESET_TIME => ("00001"),
366  RXPCSRESET_TIME => ("00001"),
367  RXPMARESET_TIME => ("00011"),
368 
369  -------------------RX OOB Signaling Attributes-------------------
370  RXOOB_CFG => ("0000110"),
371 
372  -------------------------RX Gearbox Attributes---------------------------
373  RXGEARBOX_EN => ("FALSE"),
374  GEARBOX_MODE => ("000"),
375 
376  -------------------------PRBS Detection Attribute-----------------------
377  RXPRBS_ERR_LOOPBACK => ('0'),
378 
379  -------------Power-Down Attributes----------
380  PD_TRANS_TIME_FROM_P2 => (x"03c"),
381  PD_TRANS_TIME_NONE_P2 => (x"3c"),
382  PD_TRANS_TIME_TO_P2 => (x"64"),
383 
384  -------------RX OOB Signaling Attributes----------
385  SAS_MAX_COM => (64),
386  SAS_MIN_COM => (36),
387  SATA_BURST_SEQ_LEN => ("1111"),
388  SATA_BURST_VAL => ("100"),
389  SATA_EIDLE_VAL => ("100"),
390  SATA_MAX_BURST => (8),
391  SATA_MAX_INIT => (21),
392  SATA_MAX_WAKE => (7),
393  SATA_MIN_BURST => (4),
394  SATA_MIN_INIT => (12),
395  SATA_MIN_WAKE => (4),
396 
397  -------------RX Fabric Clock Output Control Attributes----------
398  TRANS_TIME_RATE => (x"0E"),
399 
400  --------------TX Buffer Attributes----------------
401  TXBUF_EN => ("TRUE"),
402  TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
403  TXDLY_CFG => (x"001F"),
404  TXDLY_LCFG => (x"030"),
405  TXDLY_TAP_CFG => (x"0000"),
406  TXPH_CFG => (x"0780"),
407  TXPHDLY_CFG => (x"084020"),
408  TXPH_MONITOR_SEL => ("00000"),
409  TX_XCLK_SEL => ("TXOUT"),
410 
411  -------------------------FPGA TX Interface Attributes-------------------------
412  TX_DATA_WIDTH => (20),
413 
414  -------------------------TX Configurable Driver Attributes-------------------------
415  TX_DEEMPH0 => ("00000"),
416  TX_DEEMPH1 => ("00000"),
417  TX_EIDLE_ASSERT_DELAY => ("110"),
418  TX_EIDLE_DEASSERT_DELAY => ("100"),
419  TX_LOOPBACK_DRIVE_HIZ => ("FALSE"),
420  TX_MAINCURSOR_SEL => ('0'),
421  TX_DRIVE_MODE => ("DIRECT"),
422  TX_MARGIN_FULL_0 => ("1001110"),
423  TX_MARGIN_FULL_1 => ("1001001"),
424  TX_MARGIN_FULL_2 => ("1000101"),
425  TX_MARGIN_FULL_3 => ("1000010"),
426  TX_MARGIN_FULL_4 => ("1000000"),
427  TX_MARGIN_LOW_0 => ("1000110"),
428  TX_MARGIN_LOW_1 => ("1000100"),
429  TX_MARGIN_LOW_2 => ("1000010"),
430  TX_MARGIN_LOW_3 => ("1000000"),
431  TX_MARGIN_LOW_4 => ("1000000"),
432 
433  -------------------------TX Gearbox Attributes--------------------------
434  TXGEARBOX_EN => ("FALSE"),
435 
436  -------------------------TX Initialization and Reset Attributes--------------------------
437  TXPCSRESET_TIME => ("00001"),
438  TXPMARESET_TIME => ("00001"),
439 
440  -------------------------TX Receiver Detection Attributes--------------------------
441  TX_RXDETECT_CFG => (x"1832"),
442  TX_RXDETECT_REF => ("100"),
443 
444  ----------------------------CPLL Attributes----------------------------
445  CPLL_CFG => (x"BC07DC"),
446  CPLL_FBDIV => (4),
447  CPLL_FBDIV_45 => (5),
448  CPLL_INIT_CFG => (x"00001E"),
449  CPLL_LOCK_CFG => (x"01E8"),
450  CPLL_REFCLK_DIV => (1),
451  RXOUT_DIV => (2),
452  TXOUT_DIV => (2),
453  SATA_CPLL_CFG => ("VCO_3000MHZ"),
454 
455  --------------RX Initialization and Reset Attributes-------------
456  RXDFELPMRESET_TIME => ("0001111"),
457 
458  --------------RX Equalizer Attributes-------------
459  RXLPM_HF_CFG => ("00000011110000"),
460  RXLPM_LF_CFG => ("00000011110000"),
461  RX_DFE_GAIN_CFG => (x"020FEA"),
462  RX_DFE_H2_CFG => ("000000000000"),
463  RX_DFE_H3_CFG => ("000001000000"),
464  RX_DFE_H4_CFG => ("00011110000"),
465  RX_DFE_H5_CFG => ("00011100000"),
466  RX_DFE_KL_CFG => ("0000011111110"),
467  RX_DFE_LPM_CFG => (x"0904"),
468  RX_DFE_LPM_HOLD_DURING_EIDLE => ('0'),
469  RX_DFE_UT_CFG => ("10001111000000000"),
470  RX_DFE_VP_CFG => ("00011111100000011"),
471 
472  -------------------------Power-Down Attributes-------------------------
473  RX_CLKMUX_PD => ('1'),
474  TX_CLKMUX_PD => ('1'),
475 
476  -------------------------FPGA RX Interface Attribute-------------------------
477  RX_INT_DATAWIDTH => (0),
478 
479  -------------------------FPGA TX Interface Attribute-------------------------
480  TX_INT_DATAWIDTH => (0),
481 
482  ------------------TX Configurable Driver Attributes---------------
483  TX_QPI_STATUS_EN => ('0'),
484 
485  -------------------------RX Equalizer Attributes--------------------------
486  RX_DFE_KL_CFG2 => (RX_DFE_KL_CFG2_IN),
487  RX_DFE_XYD_CFG => ("0000000000000"),
488 
489  -------------------------TX Configurable Driver Attributes--------------------------
490  TX_PREDRIVER_MODE => ('0')
491 
492 
493  )
494  port map
495  (
496  --------------------------------- CPLL Ports -------------------------------
497  CPLLFBCLKLOST => CPLLFBCLKLOST_OUT,
498  CPLLLOCK => CPLLLOCK_OUT,
499  CPLLLOCKDETCLK => CPLLLOCKDETCLK_IN,
500  CPLLLOCKEN => tied_to_vcc_i,
501  CPLLPD => tied_to_ground_i,
502  CPLLREFCLKLOST => CPLLREFCLKLOST_OUT,
503  CPLLREFCLKSEL => "001",
504  CPLLRESET => CPLLRESET_IN,
505  GTRSVD => "0000000000000000",
506  PCSRSVDIN => "0000000000000000",
507  PCSRSVDIN2 => "00000",
508  PMARSVDIN => "00000",
509  PMARSVDIN2 => "00000",
510  TSTIN => "11111111111111111111" ,
511  TSTOUT => open,
512  ---------------------------------- Channel ---------------------------------
513  CLKRSVD => "0000",
514  -------------------------- Channel - Clocking Ports ------------------------
515  GTGREFCLK => tied_to_ground_i,
516  GTNORTHREFCLK0 => tied_to_ground_i,
517  GTNORTHREFCLK1 => tied_to_ground_i,
518  GTREFCLK0 => GTREFCLK0_IN,
519  GTREFCLK1 => tied_to_ground_i,
520  GTSOUTHREFCLK0 => tied_to_ground_i,
521  GTSOUTHREFCLK1 => tied_to_ground_i,
522  ---------------------------- Channel - DRP Ports --------------------------
523  DRPADDR => DRPADDR_IN,
524  DRPCLK => DRPCLK_IN ,
525  DRPDI => DRPDI_IN,
526  DRPDO => DRPDO_OUT ,
527  DRPEN => DRPEN_IN,
528  DRPRDY => DRPRDY_OUT,
529  DRPWE => DRPWE_IN,
530  ------------------------------- Clocking Ports -----------------------------
531  GTREFCLKMONITOR => open,
532  QPLLCLK => QPLLCLK_IN,
533  QPLLREFCLK => QPLLREFCLK_IN,
534  RXSYSCLKSEL => "00",
535  TXSYSCLKSEL => "00",
536  --------------------------- Digital Monitor Ports --------------------------
537  DMONITOROUT => open,
538  ----------------- FPGA TX Interface Datapath Configuration ----------------
539  TX8B10BEN => tied_to_vcc_i,
540  ------------------------------- Loopback Ports -----------------------------
541  LOOPBACK => tied_to_ground_vec_i (2 downto 0),
542  ----------------------------- PCI Express Ports ----------------------------
543  PHYSTATUS => open,
544  RXRATE => tied_to_ground_vec_i (2 downto 0),
545  RXVALID => open,
546  ------------------------------ Power-Down Ports ----------------------------
547  RXPD => "00",
548  TXPD => "00",
549  -------------------------- RX 8B/10B Decoder Ports -------------------------
550  SETERRSTATUS => tied_to_ground_i,
551  --------------------- RX Initialization and Reset Ports --------------------
552  EYESCANRESET => tied_to_ground_i,
553  RXUSERRDY => RXUSERRDY_IN,
554  -------------------------- RX Margin Analysis Ports ------------------------
555  EYESCANDATAERROR => EYESCANDATAERROR_OUT ,
556  EYESCANMODE => tied_to_ground_i,
557  EYESCANTRIGGER => tied_to_ground_i,
558  ------------------------- Receive Ports - CDR Ports ------------------------
559  RXCDRFREQRESET => tied_to_ground_i,
560  RXCDRHOLD => tied_to_ground_i,
561  RXCDRLOCK => RXCDRLOCK_OUT,
562  RXCDROVRDEN => tied_to_ground_i,
563  RXCDRRESET => tied_to_ground_i,
564  RXCDRRESETRSV => tied_to_ground_i,
565  ------------------- Receive Ports - Clock Correction Ports -----------------
566  RXCLKCORCNT => open,
567  ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
568  RX8B10BEN => tied_to_vcc_i,
569  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
570  RXUSRCLK => RXUSRCLK_IN,
571  RXUSRCLK2 => RXUSRCLK2_IN,
572  ------------------ Receive Ports - FPGA RX interface Ports -----------------
573  RXDATA => rxdata_i,
574  ------------------- Receive Ports - Pattern Checker Ports ------------------
575  RXPRBSERR => open,
576  RXPRBSSEL => tied_to_ground_vec_i (2 downto 0),
577  ------------------- Receive Ports - Pattern Checker ports ------------------
578  RXPRBSCNTRESET => tied_to_ground_i,
579  -------------------- Receive Ports - RX Equalizer Ports -------------------
580  RXDFEXYDEN => tied_to_ground_i,
581  RXDFEXYDHOLD => tied_to_ground_i,
582  RXDFEXYDOVRDEN => tied_to_ground_i,
583  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
584  RXDISPERR(7 downto 2) => rxdisperr_float_i,
585  RXDISPERR(1 downto 0) => RXDISPERR_OUT,
586  RXNOTINTABLE(7 downto 2) => rxnotintable_float_i,
587  RXNOTINTABLE(1 downto 0) => RXNOTINTABLE_OUT,
588  --------------------------- Receive Ports - RX AFE -------------------------
589  GTXRXP => GTXRXP_IN ,
590  ------------------------ Receive Ports - RX AFE Ports ----------------------
591  GTXRXN => GTXRXN_IN ,
592  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
593  RXBUFRESET => tied_to_ground_i,
594  RXBUFSTATUS => open,
595  RXDDIEN => tied_to_ground_i,
596  RXDLYBYPASS => tied_to_vcc_i,
597  RXDLYEN => tied_to_ground_i,
598  RXDLYOVRDEN => tied_to_ground_i,
599  RXDLYSRESET => tied_to_ground_i,
600  RXDLYSRESETDONE => open,
601  RXPHALIGN => tied_to_ground_i,
602  RXPHALIGNDONE => open,
603  RXPHALIGNEN => tied_to_ground_i,
604  RXPHDLYPD => tied_to_ground_i,
605  RXPHDLYRESET => tied_to_ground_i,
606  RXPHMONITOR => open,
607  RXPHOVRDEN => tied_to_ground_i,
608  RXPHSLIPMONITOR => open,
609  RXSTATUS => open,
610  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
611  RXBYTEISALIGNED => open,
612  RXBYTEREALIGN => open,
613  RXCOMMADET => open,
614  RXCOMMADETEN => tied_to_vcc_i,
615  RXMCOMMAALIGNEN => RXMCOMMAALIGNEN_IN,
616  RXPCOMMAALIGNEN => RXPCOMMAALIGNEN_IN,
617  ------------------ Receive Ports - RX Channel Bonding Ports ----------------
618  RXCHANBONDSEQ => open,
619  RXCHBONDEN => tied_to_ground_i,
620  RXCHBONDLEVEL => tied_to_ground_vec_i (2 downto 0),
621  RXCHBONDMASTER => tied_to_ground_i,
622  RXCHBONDO => open,
623  RXCHBONDSLAVE => tied_to_ground_i,
624  ----------------- Receive Ports - RX Channel Bonding Ports ----------------
625  RXCHANISALIGNED => open,
626  RXCHANREALIGN => open,
627  --------------------- Receive Ports - RX Equalizer Ports -------------------
628  RXDFEAGCHOLD => tied_to_ground_i,
629  RXDFEAGCOVRDEN => tied_to_ground_i,
630  RXDFECM1EN => tied_to_ground_i,
631  RXDFELFHOLD => tied_to_ground_i,
632  RXDFELFOVRDEN => tied_to_ground_i,
633  RXDFELPMRESET => RXDFELPMRESET_IN,
634  RXDFETAP2HOLD => tied_to_ground_i,
635  RXDFETAP2OVRDEN => tied_to_ground_i,
636  RXDFETAP3HOLD => tied_to_ground_i,
637  RXDFETAP3OVRDEN => tied_to_ground_i,
638  RXDFETAP4HOLD => tied_to_ground_i,
639  RXDFETAP4OVRDEN => tied_to_ground_i,
640  RXDFETAP5HOLD => tied_to_ground_i,
641  RXDFETAP5OVRDEN => tied_to_ground_i,
642  RXDFEUTHOLD => tied_to_ground_i,
643  RXDFEUTOVRDEN => tied_to_ground_i,
644  RXDFEVPHOLD => tied_to_ground_i,
645  RXDFEVPOVRDEN => tied_to_ground_i,
646  RXDFEVSEN => tied_to_ground_i,
647  RXLPMLFKLOVRDEN => tied_to_ground_i,
648  RXMONITOROUT => open,
649  RXMONITORSEL => "00",
650  RXOSHOLD => tied_to_ground_i,
651  RXOSOVRDEN => tied_to_ground_i,
652  --------------------- Receive Ports - RX Equilizer Ports -------------------
653  RXLPMHFHOLD => RXLPMHFHOLD_IN,
654  RXLPMHFOVRDEN => tied_to_ground_i,
655  RXLPMLFHOLD => RXLPMLFHOLD_IN,
656  ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
657  RXRATEDONE => open,
658  --------------- Receive Ports - RX Fabric Output Control Ports -------------
659  RXOUTCLK => RXOUTCLK_OUT,
660  RXOUTCLKFABRIC => open,
661  RXOUTCLKPCS => open,
662  RXOUTCLKSEL => "010",
663  ---------------------- Receive Ports - RX Gearbox Ports --------------------
664  RXDATAVALID => open,
665  RXHEADER => open,
666  RXHEADERVALID => open,
667  RXSTARTOFSEQ => open,
668  --------------------- Receive Ports - RX Gearbox Ports --------------------
669  RXGEARBOXSLIP => tied_to_ground_i,
670  ------------- Receive Ports - RX Initialization and Reset Ports ------------
671  GTRXRESET => GTRXRESET_IN,
672  RXOOBRESET => tied_to_ground_i,
673  RXPCSRESET => tied_to_ground_i,
674  RXPMARESET => RXPMARESET_IN,
675  ------------------ Receive Ports - RX Margin Analysis ports ----------------
676  RXLPMEN => tied_to_vcc_i,
677  ------------------- Receive Ports - RX OOB Signaling ports -----------------
678  RXCOMSASDET => open,
679  RXCOMWAKEDET => open,
680  ------------------ Receive Ports - RX OOB Signaling ports -----------------
681  RXCOMINITDET => open,
682  ------------------ Receive Ports - RX OOB signalling Ports -----------------
683  RXELECIDLE => open,
684  RXELECIDLEMODE => "11",
685  ----------------- Receive Ports - RX Polarity Control Ports ----------------
686  RXPOLARITY => RXPOLARITY_IN,
687  ---------------------- Receive Ports - RX gearbox ports --------------------
688  RXSLIDE => tied_to_ground_i,
689  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
690  RXCHARISCOMMA => open,
691  RXCHARISK(7 downto 2) => rxcharisk_float_i,
692  RXCHARISK(1 downto 0) => RXCHARISK_OUT,
693  ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
694  RXCHBONDI => "00000",
695  -------------- Receive Ports -RX Initialization and Reset Ports ------------
696  RXRESETDONE => RXRESETDONE_OUT,
697  -------------------------------- Rx AFE Ports ------------------------------
698  RXQPIEN => tied_to_ground_i,
699  RXQPISENN => open,
700  RXQPISENP => open,
701  --------------------------- TX Buffer Bypass Ports -------------------------
702  TXPHDLYTSTCLK => tied_to_ground_i,
703  ------------------------ TX Configurable Driver Ports ----------------------
704  TXPOSTCURSOR => "00000",
705  TXPOSTCURSORINV => tied_to_ground_i,
706  TXPRECURSOR => tied_to_ground_vec_i (4 downto 0),
707  TXPRECURSORINV => tied_to_ground_i,
708  TXQPIBIASEN => tied_to_ground_i,
709  TXQPISTRONGPDOWN => tied_to_ground_i,
710  TXQPIWEAKPUP => tied_to_ground_i,
711  --------------------- TX Initialization and Reset Ports --------------------
712  CFGRESET => tied_to_ground_i,
713  GTTXRESET => GTTXRESET_IN,
714  PCSRSVDOUT => open,
715  TXUSERRDY => TXUSERRDY_IN,
716  ---------------------- Transceiver Reset Mode Operation --------------------
717  GTRESETSEL => tied_to_ground_i,
718  RESETOVRD => tied_to_ground_i,
719  ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
720  TXCHARDISPMODE => tied_to_ground_vec_i (7 downto 0),
721  TXCHARDISPVAL => tied_to_ground_vec_i (7 downto 0),
722  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
723  TXUSRCLK => TXUSRCLK_IN,
724  TXUSRCLK2 => TXUSRCLK2_IN,
725  --------------------- Transmit Ports - PCI Express Ports -------------------
726  TXELECIDLE => tied_to_ground_i,
727  TXMARGIN => tied_to_ground_vec_i (2 downto 0),
728  TXRATE => tied_to_ground_vec_i (2 downto 0),
729  TXSWING => tied_to_ground_i,
730  ------------------ Transmit Ports - Pattern Generator Ports ----------------
731  TXPRBSFORCEERR => tied_to_ground_i,
732  ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
733  TXDLYBYPASS => tied_to_vcc_i,
734  TXDLYEN => tied_to_ground_i,
735  TXDLYHOLD => tied_to_ground_i,
736  TXDLYOVRDEN => tied_to_ground_i,
737  TXDLYSRESET => tied_to_ground_i,
738  TXDLYSRESETDONE => open,
739  TXDLYUPDOWN => tied_to_ground_i,
740  TXPHALIGN => tied_to_ground_i,
741  TXPHALIGNDONE => open,
742  TXPHALIGNEN => tied_to_ground_i,
743  TXPHDLYPD => tied_to_ground_i,
744  TXPHDLYRESET => tied_to_ground_i,
745  TXPHINIT => tied_to_ground_i,
746  TXPHINITDONE => open,
747  TXPHOVRDEN => tied_to_ground_i,
748  ---------------------- Transmit Ports - TX Buffer Ports --------------------
749  TXBUFSTATUS => open,
750  --------------- Transmit Ports - TX Configurable Driver Ports --------------
751  TXBUFDIFFCTRL => "100",
752  TXDEEMPH => tied_to_ground_i,
753  TXDIFFCTRL => "1000",
754  TXDIFFPD => tied_to_ground_i,
755  TXINHIBIT => tied_to_ground_i,
756  TXMAINCURSOR => "0000000" ,
757  TXPISOPD => tied_to_ground_i,
758  ------------------ Transmit Ports - TX Data Path interface -----------------
759  TXDATA => txdata_i,
760  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
761  GTXTXN => GTXTXN_OUT,
762  GTXTXP => GTXTXP_OUT,
763  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
764  TXOUTCLK => TXOUTCLK_OUT,
765  TXOUTCLKFABRIC => TXOUTCLKFABRIC_OUT ,
766  TXOUTCLKPCS => TXOUTCLKPCS_OUT,
767  TXOUTCLKSEL => "010",
768  TXRATEDONE => open,
769  --------------------- Transmit Ports - TX Gearbox Ports --------------------
770  TXCHARISK(7 downto 2) => tied_to_ground_vec_i (5 downto 0),
771  TXCHARISK(1 downto 0) => TXCHARISK_IN,
772  TXGEARBOXREADY => open,
773  TXHEADER => tied_to_ground_vec_i (2 downto 0),
774  TXSEQUENCE => tied_to_ground_vec_i (6 downto 0),
775  TXSTARTSEQ => tied_to_ground_i,
776  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
777  TXPCSRESET => tied_to_ground_i,
778  TXPMARESET => tied_to_ground_i,
779  TXRESETDONE => TXRESETDONE_OUT,
780  ------------------ Transmit Ports - TX OOB signalling Ports ----------------
781  TXCOMFINISH => open,
782  TXCOMINIT => tied_to_ground_i,
783  TXCOMSAS => tied_to_ground_i,
784  TXCOMWAKE => tied_to_ground_i,
785  TXPDELECIDLEMODE => tied_to_ground_i,
786  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
787  TXPOLARITY => TXPOLARITY_IN,
788  --------------- Transmit Ports - TX Receiver Detection Ports --------------
789  TXDETECTRX => tied_to_ground_i,
790  ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
791  TX8B10BBYPASS => tied_to_ground_vec_i (7 downto 0),
792  ------------------ Transmit Ports - pattern Generator Ports ----------------
793  TXPRBSSEL => tied_to_ground_vec_i (2 downto 0),
794  ----------------------- Tx Configurable Driver Ports ----------------------
795  TXQPISENN => open,
796  TXQPISENP => open
797 
798  );
799 
800  end RTL;
801 
802 
803 
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