AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
s6link.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.5
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : s6link.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module S6Link (a GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 library UNISIM;
68 use UNISIM.VCOMPONENTS.ALL;
69 
70 
71 --***************************** Entity Declaration ****************************
72 
73 entity S6Link is
74 generic
75 (
76  QPLL_FBDIV_TOP : integer := 16;
77 
78  -- Simulation attributes
79  WRAPPER_SIM_GTRESET_SPEEDUP : string := "false"; -- Set to "true" to speed up sim reset
80  RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
81  PMA_RSV_IN : bit_vector := x"00018480";
82  SIM_VERSION : string := "4.0"
83 
84 );
85 port
86 (
87  --_________________________________________________________________________
88  --_________________________________________________________________________
89  --GT0 (X0Y15)
90  --____________________________CHANNEL PORTS________________________________
91  --------------------------------- CPLL Ports -------------------------------
92  GT0_CPLLFBCLKLOST_OUT : out std_logic;
93  GT0_CPLLLOCK_OUT : out std_logic;
94  GT0_CPLLLOCKDETCLK_IN : in std_logic;
95  GT0_CPLLREFCLKLOST_OUT : out std_logic;
96  GT0_CPLLRESET_IN : in std_logic;
97  -------------------------- Channel - Clocking Ports ------------------------
98  GT0_GTREFCLK0_IN : in std_logic;
99  ---------------------------- Channel - DRP Ports --------------------------
100  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
101  GT0_DRPCLK_IN : in std_logic;
102  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
103  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
104  GT0_DRPEN_IN : in std_logic;
105  GT0_DRPRDY_OUT : out std_logic;
106  GT0_DRPWE_IN : in std_logic;
107  --------------------- RX Initialization and Reset Ports --------------------
108  GT0_RXUSERRDY_IN : in std_logic;
109  -------------------------- RX Margin Analysis Ports ------------------------
110  GT0_EYESCANDATAERROR_OUT : out std_logic;
111  ------------------------- Receive Ports - CDR Ports ------------------------
112  GT0_RXCDRLOCK_OUT : out std_logic;
113  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
114  GT0_RXUSRCLK_IN : in std_logic;
115  GT0_RXUSRCLK2_IN : in std_logic;
116  ------------------ Receive Ports - FPGA RX interface Ports -----------------
117  GT0_RXDATA_OUT : out std_logic_vector(15 downto 0);
118  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
119  GT0_RXDISPERR_OUT : out std_logic_vector(1 downto 0);
120  GT0_RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
121  --------------------------- Receive Ports - RX AFE -------------------------
122  GT0_GTXRXP_IN : in std_logic;
123  ------------------------ Receive Ports - RX AFE Ports ----------------------
124  GT0_GTXRXN_IN : in std_logic;
125  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
126  GT0_RXMCOMMAALIGNEN_IN : in std_logic;
127  GT0_RXPCOMMAALIGNEN_IN : in std_logic;
128  --------------------- Receive Ports - RX Equalizer Ports -------------------
129  GT0_RXDFELPMRESET_IN : in std_logic;
130  --------------------- Receive Ports - RX Equilizer Ports -------------------
131  GT0_RXLPMHFHOLD_IN : in std_logic;
132  GT0_RXLPMLFHOLD_IN : in std_logic;
133  --------------- Receive Ports - RX Fabric Output Control Ports -------------
134  GT0_RXOUTCLK_OUT : out std_logic;
135  ------------- Receive Ports - RX Initialization and Reset Ports ------------
136  GT0_GTRXRESET_IN : in std_logic;
137  GT0_RXPMARESET_IN : in std_logic;
138  ----------------- Receive Ports - RX Polarity Control Ports ----------------
139  GT0_RXPOLARITY_IN : in std_logic;
140  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
141  GT0_RXCHARISK_OUT : out std_logic_vector(1 downto 0);
142  -------------- Receive Ports -RX Initialization and Reset Ports ------------
143  GT0_RXRESETDONE_OUT : out std_logic;
144  --------------------- TX Initialization and Reset Ports --------------------
145  GT0_GTTXRESET_IN : in std_logic;
146  GT0_TXUSERRDY_IN : in std_logic;
147  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
148  GT0_TXUSRCLK_IN : in std_logic;
149  GT0_TXUSRCLK2_IN : in std_logic;
150  ------------------ Transmit Ports - TX Data Path interface -----------------
151  GT0_TXDATA_IN : in std_logic_vector(15 downto 0);
152  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
153  GT0_GTXTXN_OUT : out std_logic;
154  GT0_GTXTXP_OUT : out std_logic;
155  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
156  GT0_TXOUTCLK_OUT : out std_logic;
157  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
158  GT0_TXOUTCLKPCS_OUT : out std_logic;
159  --------------------- Transmit Ports - TX Gearbox Ports --------------------
160  GT0_TXCHARISK_IN : in std_logic_vector(1 downto 0);
161  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
162  GT0_TXRESETDONE_OUT : out std_logic;
163  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
164  GT0_TXPOLARITY_IN : in std_logic;
165 
166 
167  --____________________________COMMON PORTS________________________________
168  ---------------------- Common Block - Ref Clock Ports ---------------------
169  GT0_GTREFCLK0_COMMON_IN : in std_logic;
170  ------------------------- Common Block - QPLL Ports ------------------------
171  GT0_QPLLLOCK_OUT : out std_logic;
172  GT0_QPLLLOCKDETCLK_IN : in std_logic;
173  GT0_QPLLREFCLKLOST_OUT : out std_logic;
174  GT0_QPLLRESET_IN : in std_logic
175 
176 
177 );
178 
179 
180 end S6Link;
181 
182 architecture RTL of S6Link is
183 
184  attribute CORE_GENERATION_INFO : string;
185  attribute CORE_GENERATION_INFO of RTL : architecture is "S6Link,gtwizard_v2_5,{protocol_file=Start_from_scratch}";
186 
187 
188 --***********************************Parameter Declarations********************
189 
190  constant DLY : time := 1 ns;
191 
192 --***************************** Signal Declarations *****************************
193 
194  -- ground and tied_to_vcc_i signals
195  signal tied_to_ground_i : std_logic;
196  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
197  signal tied_to_vcc_i : std_logic;
198  signal gt0_qplloutclk_i : std_logic;
199  signal gt0_qplloutrefclk_i : std_logic;
200 
201 
202  signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0);
203  signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0);
204 
205 
206  signal gt0_qpllclk_i : std_logic;
207  signal gt0_qpllrefclk_i : std_logic;
208 
209 
210 --*************************** Component Declarations **************************
211 component S6Link_GT
212 generic
213 (
214  -- Simulation attributes
215  GT_SIM_GTRESET_SPEEDUP : string := "false";
216  RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
217  PMA_RSV_IN : bit_vector := X"00000000";
218  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000";
219  SIM_VERSION : string := "4.0"
220 );
221 port
222 (
223  --------------------------------- CPLL Ports -------------------------------
224  CPLLFBCLKLOST_OUT : out std_logic;
225  CPLLLOCK_OUT : out std_logic;
226  CPLLLOCKDETCLK_IN : in std_logic;
227  CPLLREFCLKLOST_OUT : out std_logic;
228  CPLLRESET_IN : in std_logic;
229  -------------------------- Channel - Clocking Ports ------------------------
230  GTREFCLK0_IN : in std_logic;
231  ---------------------------- Channel - DRP Ports --------------------------
232  DRPADDR_IN : in std_logic_vector(8 downto 0);
233  DRPCLK_IN : in std_logic;
234  DRPDI_IN : in std_logic_vector(15 downto 0);
235  DRPDO_OUT : out std_logic_vector(15 downto 0);
236  DRPEN_IN : in std_logic;
237  DRPRDY_OUT : out std_logic;
238  DRPWE_IN : in std_logic;
239  ------------------------------- Clocking Ports -----------------------------
240  QPLLCLK_IN : in std_logic;
241  QPLLREFCLK_IN : in std_logic;
242  --------------------- RX Initialization and Reset Ports --------------------
243  RXUSERRDY_IN : in std_logic;
244  -------------------------- RX Margin Analysis Ports ------------------------
245  EYESCANDATAERROR_OUT : out std_logic;
246  ------------------------- Receive Ports - CDR Ports ------------------------
247  RXCDRLOCK_OUT : out std_logic;
248  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
249  RXUSRCLK_IN : in std_logic;
250  RXUSRCLK2_IN : in std_logic;
251  ------------------ Receive Ports - FPGA RX interface Ports -----------------
252  RXDATA_OUT : out std_logic_vector(15 downto 0);
253  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
254  RXDISPERR_OUT : out std_logic_vector(1 downto 0);
255  RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
256  --------------------------- Receive Ports - RX AFE -------------------------
257  GTXRXP_IN : in std_logic;
258  ------------------------ Receive Ports - RX AFE Ports ----------------------
259  GTXRXN_IN : in std_logic;
260  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
261  RXMCOMMAALIGNEN_IN : in std_logic;
262  RXPCOMMAALIGNEN_IN : in std_logic;
263  --------------------- Receive Ports - RX Equalizer Ports -------------------
264  RXDFELPMRESET_IN : in std_logic;
265  --------------------- Receive Ports - RX Equilizer Ports -------------------
266  RXLPMHFHOLD_IN : in std_logic;
267  RXLPMLFHOLD_IN : in std_logic;
268  --------------- Receive Ports - RX Fabric Output Control Ports -------------
269  RXOUTCLK_OUT : out std_logic;
270  ------------- Receive Ports - RX Initialization and Reset Ports ------------
271  GTRXRESET_IN : in std_logic;
272  RXPMARESET_IN : in std_logic;
273  ----------------- Receive Ports - RX Polarity Control Ports ----------------
274  RXPOLARITY_IN : in std_logic;
275  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
276  RXCHARISK_OUT : out std_logic_vector(1 downto 0);
277  -------------- Receive Ports -RX Initialization and Reset Ports ------------
278  RXRESETDONE_OUT : out std_logic;
279  --------------------- TX Initialization and Reset Ports --------------------
280  GTTXRESET_IN : in std_logic;
281  TXUSERRDY_IN : in std_logic;
282  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
283  TXUSRCLK_IN : in std_logic;
284  TXUSRCLK2_IN : in std_logic;
285  ------------------ Transmit Ports - TX Data Path interface -----------------
286  TXDATA_IN : in std_logic_vector(15 downto 0);
287  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
288  GTXTXN_OUT : out std_logic;
289  GTXTXP_OUT : out std_logic;
290  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
291  TXOUTCLK_OUT : out std_logic;
292  TXOUTCLKFABRIC_OUT : out std_logic;
293  TXOUTCLKPCS_OUT : out std_logic;
294  --------------------- Transmit Ports - TX Gearbox Ports --------------------
295  TXCHARISK_IN : in std_logic_vector(1 downto 0);
296  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
297  TXRESETDONE_OUT : out std_logic;
298  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
299  TXPOLARITY_IN : in std_logic
300 
301 
302 );
303 end component;
304 
305 
306 
307 --*************************Logic to set Attribute QPLL_FB_DIV*****************************
308  impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
309  begin
310  if (qpllfbdiv_top = 16) then
311  return "0000100000";
312  elsif (qpllfbdiv_top = 20) then
313  return "0000110000" ;
314  elsif (qpllfbdiv_top = 32) then
315  return "0001100000" ;
316  elsif (qpllfbdiv_top = 40) then
317  return "0010000000" ;
318  elsif (qpllfbdiv_top = 64) then
319  return "0011100000" ;
320  elsif (qpllfbdiv_top = 66) then
321  return "0101000000" ;
322  elsif (qpllfbdiv_top = 80) then
323  return "0100100000" ;
324  elsif (qpllfbdiv_top = 100) then
325  return "0101110000" ;
326  else
327  return "0000000000" ;
328  end if;
329  end function;
330 
331  impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
332  begin
333  if (qpllfbdiv_top = 16) then
334  return '1';
335  elsif (qpllfbdiv_top = 20) then
336  return '1' ;
337  elsif (qpllfbdiv_top = 32) then
338  return '1' ;
339  elsif (qpllfbdiv_top = 40) then
340  return '1' ;
341  elsif (qpllfbdiv_top = 64) then
342  return '1' ;
343  elsif (qpllfbdiv_top = 66) then
344  return '0' ;
345  elsif (qpllfbdiv_top = 80) then
346  return '1' ;
347  elsif (qpllfbdiv_top = 100) then
348  return '1' ;
349  else
350  return '1' ;
351  end if;
352  end function;
353 
354  constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
355  constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
356 
357 --********************************* Main Body of Code**************************
358 
359 begin
360 
361  tied_to_ground_i <= '0';
362  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
363  tied_to_vcc_i <= '1';
364 -- gt0_qpllclk_i <= gt0_qplloutclk_i;
365 -- gt0_qpllrefclk_i <= gt0_qplloutrefclk_i;
366  gt0_qpllclk_i <= '0';
367  gt0_qpllrefclk_i <= '0';
368 
369 
370 
371  --------------------------- GT Instances -------------------------------
372 
373  --_________________________________________________________________________
374  --_________________________________________________________________________
375  --GT0 (X0Y15)
376 
377  gt0_S6Link_i : S6Link_GT
378  generic map
379  (
380  -- Simulation attributes
381  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
382  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
383  PMA_RSV_IN => PMA_RSV_IN,
384  PCS_RSVD_ATTR_IN => X"000000000000",
385  SIM_VERSION => SIM_VERSION
386  )
387  port map
388  (
389  --------------------------------- CPLL Ports -------------------------------
390  CPLLFBCLKLOST_OUT => GT0_CPLLFBCLKLOST_OUT ,
391  CPLLLOCK_OUT => GT0_CPLLLOCK_OUT,
392  CPLLLOCKDETCLK_IN => GT0_CPLLLOCKDETCLK_IN ,
393  CPLLREFCLKLOST_OUT => GT0_CPLLREFCLKLOST_OUT ,
394  CPLLRESET_IN => GT0_CPLLRESET_IN,
395  -------------------------- Channel - Clocking Ports ------------------------
396  GTREFCLK0_IN => GT0_GTREFCLK0_IN,
397  ---------------------------- Channel - DRP Ports --------------------------
398  DRPADDR_IN => GT0_DRPADDR_IN,
399  DRPCLK_IN => GT0_DRPCLK_IN,
400  DRPDI_IN => GT0_DRPDI_IN,
401  DRPDO_OUT => GT0_DRPDO_OUT,
402  DRPEN_IN => GT0_DRPEN_IN,
403  DRPRDY_OUT => GT0_DRPRDY_OUT,
404  DRPWE_IN => GT0_DRPWE_IN,
405  ------------------------------- Clocking Ports -----------------------------
406  QPLLCLK_IN => gt0_qpllclk_i,
407  QPLLREFCLK_IN => gt0_qpllrefclk_i,
408  --------------------- RX Initialization and Reset Ports --------------------
409  RXUSERRDY_IN => GT0_RXUSERRDY_IN,
410  -------------------------- RX Margin Analysis Ports ------------------------
411  EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
412  ------------------------- Receive Ports - CDR Ports ------------------------
413  RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
414  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
415  RXUSRCLK_IN => GT0_RXUSRCLK_IN,
416  RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
417  ------------------ Receive Ports - FPGA RX interface Ports -----------------
418  RXDATA_OUT => GT0_RXDATA_OUT,
419  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
420  RXDISPERR_OUT => GT0_RXDISPERR_OUT,
421  RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT ,
422  --------------------------- Receive Ports - RX AFE -------------------------
423  GTXRXP_IN => GT0_GTXRXP_IN,
424  ------------------------ Receive Ports - RX AFE Ports ----------------------
425  GTXRXN_IN => GT0_GTXRXN_IN,
426  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
427  RXMCOMMAALIGNEN_IN => GT0_RXMCOMMAALIGNEN_IN ,
428  RXPCOMMAALIGNEN_IN => GT0_RXPCOMMAALIGNEN_IN ,
429  --------------------- Receive Ports - RX Equalizer Ports -------------------
430  RXDFELPMRESET_IN => GT0_RXDFELPMRESET_IN ,
431  --------------------- Receive Ports - RX Equilizer Ports -------------------
432  RXLPMHFHOLD_IN => GT0_RXLPMHFHOLD_IN,
433  RXLPMLFHOLD_IN => GT0_RXLPMLFHOLD_IN,
434  --------------- Receive Ports - RX Fabric Output Control Ports -------------
435  RXOUTCLK_OUT => GT0_RXOUTCLK_OUT,
436  ------------- Receive Ports - RX Initialization and Reset Ports ------------
437  GTRXRESET_IN => GT0_GTRXRESET_IN,
438  RXPMARESET_IN => GT0_RXPMARESET_IN,
439  ----------------- Receive Ports - RX Polarity Control Ports ----------------
440  RXPOLARITY_IN => GT0_RXPOLARITY_IN,
441  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
442  RXCHARISK_OUT => GT0_RXCHARISK_OUT,
443  -------------- Receive Ports -RX Initialization and Reset Ports ------------
444  RXRESETDONE_OUT => GT0_RXRESETDONE_OUT ,
445  --------------------- TX Initialization and Reset Ports --------------------
446  GTTXRESET_IN => GT0_GTTXRESET_IN,
447  TXUSERRDY_IN => GT0_TXUSERRDY_IN,
448  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
449  TXUSRCLK_IN => GT0_TXUSRCLK_IN,
450  TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
451  ------------------ Transmit Ports - TX Data Path interface -----------------
452  TXDATA_IN => GT0_TXDATA_IN,
453  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
454  GTXTXN_OUT => GT0_GTXTXN_OUT,
455  GTXTXP_OUT => GT0_GTXTXP_OUT,
456  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
457  TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
458  TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT ,
459  TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT ,
460  --------------------- Transmit Ports - TX Gearbox Ports --------------------
461  TXCHARISK_IN => GT0_TXCHARISK_IN,
462  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
463  TXRESETDONE_OUT => GT0_TXRESETDONE_OUT ,
464  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
465  TXPOLARITY_IN => GT0_TXPOLARITY_IN
466 
467  );
468 
469  --_________________________________________________________________________
470  --_________________________________________________________________________
471  --_________________________GTXE2_COMMON____________________________________
472 
473 -- gtxe2_common_0_i : GTXE2_COMMON
474 -- generic map
475 -- (
476 -- -- Simulation attributes
477 -- SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
478 -- SIM_QPLLREFCLK_SEL => ("001"),
479 -- SIM_VERSION => SIM_VERSION,
480 --
481 --
482 -- ------------------COMMON BLOCK Attributes---------------
483 -- BIAS_CFG => (x"0000040000001000"),
484 -- COMMON_CFG => (x"00000000"),
485 -- QPLL_CFG => (x"06801C1"),
486 -- QPLL_CLKOUT_CFG => ("0000"),
487 -- QPLL_COARSE_FREQ_OVRD => ("010000"),
488 -- QPLL_COARSE_FREQ_OVRD_EN => ('0'),
489 -- QPLL_CP => ("0000011111"),
490 -- QPLL_CP_MONITOR_EN => ('0'),
491 -- QPLL_DMONITOR_SEL => ('0'),
492 -- QPLL_FBDIV => (QPLL_FBDIV_IN),
493 -- QPLL_FBDIV_MONITOR_EN => ('0'),
494 -- QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
495 -- QPLL_INIT_CFG => (x"000006"),
496 -- QPLL_LOCK_CFG => (x"21E8"),
497 -- QPLL_LPF => ("1111"),
498 -- QPLL_REFCLK_DIV => (1)
499 --
500 --
501 -- )
502 -- port map
503 -- (
504 -- ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
505 -- DRPADDR => tied_to_ground_vec_i(7 downto 0),
506 -- DRPCLK => tied_to_ground_i,
507 -- DRPDI => tied_to_ground_vec_i(15 downto 0),
508 -- DRPDO => open,
509 -- DRPEN => tied_to_ground_i,
510 -- DRPRDY => open,
511 -- DRPWE => tied_to_ground_i,
512 -- ---------------------- Common Block - Ref Clock Ports ---------------------
513 -- GTGREFCLK => tied_to_ground_i,
514 -- GTNORTHREFCLK0 => tied_to_ground_i,
515 -- GTNORTHREFCLK1 => tied_to_ground_i,
516 -- GTREFCLK0 => GT0_GTREFCLK0_COMMON_IN,
517 -- GTREFCLK1 => tied_to_ground_i,
518 -- GTSOUTHREFCLK0 => tied_to_ground_i,
519 -- GTSOUTHREFCLK1 => tied_to_ground_i,
520 -- ------------------------- Common Block - QPLL Ports -----------------------
521 -- QPLLDMONITOR => open,
522 -- ----------------------- Common Block - Clocking Ports ----------------------
523 -- QPLLOUTCLK => gt0_qplloutclk_i,
524 -- QPLLOUTREFCLK => gt0_qplloutrefclk_i,
525 -- REFCLKOUTMONITOR => open,
526 -- ------------------------- Common Block - QPLL Ports ------------------------
527 -- QPLLFBCLKLOST => open,
528 -- QPLLLOCK => GT0_QPLLLOCK_OUT,
529 -- QPLLLOCKDETCLK => GT0_QPLLLOCKDETCLK_IN,
530 -- QPLLLOCKEN => tied_to_vcc_i,
531 -- QPLLOUTRESET => tied_to_ground_i,
532 -- QPLLPD => tied_to_ground_i,
533 -- QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_OUT,
534 -- QPLLREFCLKSEL => "001",
535 -- QPLLRESET => GT0_QPLLRESET_IN,
536 -- QPLLRSVD1 => "0000000000000000",
537 -- QPLLRSVD2 => "11111",
538 -- --------------------------------- QPLL Ports -------------------------------
539 -- BGBYPASSB => tied_to_vcc_i,
540 -- BGMONITORENB => tied_to_vcc_i,
541 -- BGPDB => tied_to_vcc_i,
542 -- BGRCALOVRD => "00000",
543 -- PMARSVD => "00000000",
544 -- RCALENB => tied_to_vcc_i
545 --
546 -- );
547 
548 
549 
550 end RTL;
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