AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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mig_7series_v1_9_ui_cmd.v
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49 // ____ ____
50 // / /\/ /
51 // /___/ \ / Vendor : Xilinx
52 // \ \ \/ Version : %version
53 // \ \ Application : MIG
54 // / / Filename : ui_cmd.v
55 // /___/ /\ Date Last Modified : $date$
56 // \ \ / \ Date Created : Tue Jun 30 2009
57 // \___\/\___\
58 //
59 //Device : 7-Series
60 //Design Name : DDR3 SDRAM
61 //Purpose :
62 //Reference :
63 //Revision History :
64 //*****************************************************************************
65 
66 `timescale 1 ps / 1 ps
67 
68 // User interface command port.
69 
70 module mig_7series_v1_9_ui_cmd #
71  (
72  parameter TCQ = 100,
73  parameter ADDR_WIDTH = 33,
74  parameter BANK_WIDTH = 3,
75  parameter COL_WIDTH = 12,
76  parameter DATA_BUF_ADDR_WIDTH = 5,
77  parameter RANK_WIDTH = 2,
78  parameter ROW_WIDTH = 16,
79  parameter RANKS = 4,
80  parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
81  )
82  (/*AUTOARG**/
83  // Outputs
84  app_rdy, use_addr, rank, bank, row, col, size, cmd, hi_priority,
85  rd_accepted, wr_accepted, data_buf_addr,
86  // Inputs
87  rst, clk, accept_ns, rd_buf_full, wr_req_16, app_addr, app_cmd,
88  app_sz, app_hi_pri, app_en, wr_data_buf_addr, rd_data_buf_addr_r
89  );
90 
91  input rst;
92  input clk;
93 
94  input accept_ns;
95  input rd_buf_full;
96  input wr_req_16;
97  wire app_rdy_ns = accept_ns && ~rd_buf_full && ~wr_req_16;
98  (* keep = "true", max_fanout = 10 *) reg app_rdy_r = 1'b0 /* synthesis syn_maxfan = 10 **/;
99  always @(posedge clk) app_rdy_r <= #TCQ app_rdy_ns;
100  output wire app_rdy;
101  assign app_rdy = app_rdy_r;
102 
103  input [ADDR_WIDTH-1:0] app_addr;
104  input [2:0] app_cmd;
105  input app_sz;
106  input app_hi_pri;
107  input app_en;
108 
109  reg [ADDR_WIDTH-1:0] app_addr_r1 = {ADDR_WIDTH{1'b0}};
110  reg [ADDR_WIDTH-1:0] app_addr_r2 = {ADDR_WIDTH{1'b0}};
111  reg [2:0] app_cmd_r1;
112  reg [2:0] app_cmd_r2;
113  reg app_sz_r1;
114  reg app_sz_r2;
115  reg app_hi_pri_r1;
116  reg app_hi_pri_r2;
117  reg app_en_r1;
118  reg app_en_r2;
119 
120  wire [ADDR_WIDTH-1:0] app_addr_ns1 = app_rdy_r && app_en ? app_addr : app_addr_r1;
121  wire [ADDR_WIDTH-1:0] app_addr_ns2 = app_rdy_r ? app_addr_r1 : app_addr_r2;
122  wire [2:0] app_cmd_ns1 = app_rdy_r ? app_cmd : app_cmd_r1;
123  wire [2:0] app_cmd_ns2 = app_rdy_r ? app_cmd_r1 : app_cmd_r2;
124  wire app_sz_ns1 = app_rdy_r ? app_sz : app_sz_r1;
125  wire app_sz_ns2 = app_rdy_r ? app_sz_r1 : app_sz_r2;
126  wire app_hi_pri_ns1 = app_rdy_r ? app_hi_pri : app_hi_pri_r1;
127  wire app_hi_pri_ns2 = app_rdy_r ? app_hi_pri_r1 : app_hi_pri_r2;
128  wire app_en_ns1 = ~rst && (app_rdy_r ? app_en : app_en_r1);
129  wire app_en_ns2 = ~rst && (app_rdy_r ? app_en_r1 : app_en_r2);
130 
131  always @(posedge clk) begin
132  if (rst) begin
133  app_addr_r1 <= #TCQ {ADDR_WIDTH{1'b0}};
134  app_addr_r2 <= #TCQ {ADDR_WIDTH{1'b0}};
135  end else begin
136  app_addr_r1 <= #TCQ app_addr_ns1;
137  app_addr_r2 <= #TCQ app_addr_ns2;
138  end
139  app_cmd_r1 <= #TCQ app_cmd_ns1;
140  app_cmd_r2 <= #TCQ app_cmd_ns2;
141  app_sz_r1 <= #TCQ app_sz_ns1;
142  app_sz_r2 <= #TCQ app_sz_ns2;
143  app_hi_pri_r1 <= #TCQ app_hi_pri_ns1;
144  app_hi_pri_r2 <= #TCQ app_hi_pri_ns2;
145  app_en_r1 <= #TCQ app_en_ns1;
146  app_en_r2 <= #TCQ app_en_ns2;
147  end // always @ (posedge clk)
148 
149  wire use_addr_lcl = app_en_r2 && app_rdy_r;
150  output wire use_addr;
151  assign use_addr = use_addr_lcl;
152 
153  output wire [RANK_WIDTH-1:0] rank;
154  output wire [BANK_WIDTH-1:0] bank;
155  output wire [ROW_WIDTH-1:0] row;
156  output wire [COL_WIDTH-1:0] col;
157  output wire size;
158  output wire [2:0] cmd;
159  output wire hi_priority;
160 
161 /* assign col = app_rdy_r
162  ? app_addr_r1[0+:COL_WIDTH]
163  : app_addr_r2[0+:COL_WIDTH];**/
164  generate
165  begin
166  if (MEM_ADDR_ORDER == "TG_TEST")
167  begin
168  assign col[4:0] = app_rdy_r
169  ? app_addr_r1[0+:5]
170  : app_addr_r2[0+:5];
171 
172  if (RANKS==1)
173  begin
174  assign col[COL_WIDTH-1:COL_WIDTH-2] = app_rdy_r
175  ? app_addr_r1[5+3+BANK_WIDTH+:2]
176  : app_addr_r2[5+3+BANK_WIDTH+:2];
177  assign col[COL_WIDTH-3:5] = app_rdy_r
178  ? app_addr_r1[5+3+BANK_WIDTH+2+2+:COL_WIDTH-7]
179  : app_addr_r2[5+3+BANK_WIDTH+2+2+:COL_WIDTH-7];
180  end
181  else
182  begin
183  assign col[COL_WIDTH-1:COL_WIDTH-2] = app_rdy_r
184  ? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+:2]
185  : app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+:2];
186  assign col[COL_WIDTH-3:5] = app_rdy_r
187  ? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+2+:COL_WIDTH-7]
188  : app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+2+:COL_WIDTH-7];
189  end
190  assign row[2:0] = app_rdy_r
191  ? app_addr_r1[5+:3]
192  : app_addr_r2[5+:3];
193  if (RANKS==1)
194  begin
195  assign row[ROW_WIDTH-1:ROW_WIDTH-2] = app_rdy_r
196  ? app_addr_r1[5+3+BANK_WIDTH+2+:2]
197  : app_addr_r2[5+3+BANK_WIDTH+2+:2];
198  assign row[ROW_WIDTH-3:3] = app_rdy_r
199  ? app_addr_r1[5+3+BANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5]
200  : app_addr_r2[5+3+BANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5];
201  end
202  else
203  begin
204  assign row[ROW_WIDTH-1:ROW_WIDTH-2] = app_rdy_r
205  ? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+:2]
206  : app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+:2];
207  assign row[ROW_WIDTH-3:3] = app_rdy_r
208  ? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5]
209  : app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5];
210  end
211  assign bank = app_rdy_r
212  ? app_addr_r1[5+3+:BANK_WIDTH]
213  : app_addr_r2[5+3+:BANK_WIDTH];
214  assign rank = (RANKS == 1)
215  ? 1'b0
216  : app_rdy_r
217  ? app_addr_r1[5+3+BANK_WIDTH+:RANK_WIDTH]
218  : app_addr_r2[5+3+BANK_WIDTH+:RANK_WIDTH];
219  end
220  else if (MEM_ADDR_ORDER == "ROW_BANK_COLUMN")
221  begin
222  assign col = app_rdy_r
223  ? app_addr_r1[0+:COL_WIDTH]
224  : app_addr_r2[0+:COL_WIDTH];
225  assign row = app_rdy_r
226  ? app_addr_r1[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH]
227  : app_addr_r2[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH];
228  assign bank = app_rdy_r
229  ? app_addr_r1[COL_WIDTH+:BANK_WIDTH]
230  : app_addr_r2[COL_WIDTH+:BANK_WIDTH];
231  assign rank = (RANKS == 1)
232  ? 1'b0
233  : app_rdy_r
234  ? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]
235  : app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
236  end
237  else
238  begin
239  assign col = app_rdy_r
240  ? app_addr_r1[0+:COL_WIDTH]
241  : app_addr_r2[0+:COL_WIDTH];
242  assign row = app_rdy_r
243  ? app_addr_r1[COL_WIDTH+:ROW_WIDTH]
244  : app_addr_r2[COL_WIDTH+:ROW_WIDTH];
245  assign bank = app_rdy_r
246  ? app_addr_r1[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH]
247  : app_addr_r2[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH];
248  assign rank = (RANKS == 1)
249  ? 1'b0
250  : app_rdy_r
251  ? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]
252  : app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
253  end
254  end
255  endgenerate
256 
257 /* assign rank = (RANKS == 1)
258  ? 1'b0
259  : app_rdy_r
260  ? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]
261  : app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];**/
262  assign size = app_rdy_r
263  ? app_sz_r1
264  : app_sz_r2;
265  assign cmd = app_rdy_r
266  ? app_cmd_r1
267  : app_cmd_r2;
268  assign hi_priority = app_rdy_r
269  ? app_hi_pri_r1
270  : app_hi_pri_r2;
271 
272  wire request_accepted = use_addr_lcl && app_rdy_r;
273  wire rd = app_cmd_r2[1:0] == 2'b01;
274  wire wr = app_cmd_r2[1:0] == 2'b00;
275  wire wr_bytes = app_cmd_r2[1:0] == 2'b11;
276  wire write = wr || wr_bytes;
277  output wire rd_accepted;
278  assign rd_accepted = request_accepted && rd;
279  output wire wr_accepted;
280  assign wr_accepted = request_accepted && write;
281 
282  input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;
283  input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r;
284  output wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
285 
286  assign data_buf_addr = ~write ? rd_data_buf_addr_r : wr_data_buf_addr;
287 
288 endmodule // ui_cmd
289 
290 // Local Variables:
291 // verilog-library-directories:(".")
292 // End:
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