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51 // /___/ \ / Vendor : Xilinx
52 // \ \ \/ Version : %version
53 // \ \ Application : MIG
54 // / / Filename : mem_intfc.v
55 // /___/ /\ Date Last Modified : $date$
56 // \ \ / \ Date Created : Aug 03 2009
60 //Design Name : DDR3 SDRAM
61 //Purpose : Top level memory interface block. Instantiates a clock
62 // and reset generator, the memory controller, the phy and
63 // the user interface blocks.
66 //*****************************************************************************
68 `timescale 1 ps /
1 ps
73 parameter PAYLOAD_WIDTH =
64,
74 parameter ADDR_CMD_MODE =
"1T",
75 parameter AL =
"0",
// Additive Latency option
76 parameter BANK_WIDTH =
3,
// # of bank bits
77 parameter BM_CNT_WIDTH =
2,
// Bank machine counter width
78 parameter BURST_MODE =
"8",
// Burst length
79 parameter BURST_TYPE =
"SEQ",
// Burst type
80 parameter CA_MIRROR =
"OFF",
// C/A mirror opt for DDR3 dual rank
81 parameter CK_WIDTH =
1,
// # of CK/CK# outputs to memory
82 // five fields, one per possible I/O bank, 4 bits in each field, 1 per lane
84 parameter DATA_CTL_B0 =
4'hc,
85 parameter DATA_CTL_B1 =
4'hf,
86 parameter DATA_CTL_B2 =
4'hf,
87 parameter DATA_CTL_B3 =
4'hf,
88 parameter DATA_CTL_B4 =
4'hf,
89 // defines the byte lanes in I/O banks being used in the interface
91 parameter BYTE_LANES_B0 =
4'b1111,
92 parameter BYTE_LANES_B1 =
4'b0000,
93 parameter BYTE_LANES_B2 =
4'b0000,
94 parameter BYTE_LANES_B3 =
4'b0000,
95 parameter BYTE_LANES_B4 =
4'b0000,
96 // defines the bit lanes in I/O banks being used in the interface. Each
97 // parameter = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused
98 parameter PHY_0_BITLANES =
48'h0000_0000_0000,
99 parameter PHY_1_BITLANES =
48'h0000_0000_0000,
100 parameter PHY_2_BITLANES =
48'h0000_0000_0000,
102 // control/address/data pin mapping parameters
103 parameter CK_BYTE_MAP
104 =
144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
106 =
192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
107 parameter BANK_MAP =
36'h000_000_000,
108 parameter CAS_MAP =
12'h000,
109 parameter CKE_ODT_BYTE_MAP =
8'h00,
110 parameter CKE_MAP =
96'h000_000_000_000_000_000_000_000,
111 parameter ODT_MAP =
96'h000_000_000_000_000_000_000_000,
112 parameter CKE_ODT_AUX =
"FALSE",
113 parameter CS_MAP =
120'h000_000_000_000_000_000_000_000_000_000,
114 parameter PARITY_MAP =
12'h000,
115 parameter RAS_MAP =
12'h000,
116 parameter WE_MAP =
12'h000,
117 parameter DQS_BYTE_MAP
118 =
144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
119 parameter DATA0_MAP =
96'h000_000_000_000_000_000_000_000,
120 parameter DATA1_MAP =
96'h000_000_000_000_000_000_000_000,
121 parameter DATA2_MAP =
96'h000_000_000_000_000_000_000_000,
122 parameter DATA3_MAP =
96'h000_000_000_000_000_000_000_000,
123 parameter DATA4_MAP =
96'h000_000_000_000_000_000_000_000,
124 parameter DATA5_MAP =
96'h000_000_000_000_000_000_000_000,
125 parameter DATA6_MAP =
96'h000_000_000_000_000_000_000_000,
126 parameter DATA7_MAP =
96'h000_000_000_000_000_000_000_000,
127 parameter DATA8_MAP =
96'h000_000_000_000_000_000_000_000,
128 parameter DATA9_MAP =
96'h000_000_000_000_000_000_000_000,
129 parameter DATA10_MAP =
96'h000_000_000_000_000_000_000_000,
130 parameter DATA11_MAP =
96'h000_000_000_000_000_000_000_000,
131 parameter DATA12_MAP =
96'h000_000_000_000_000_000_000_000,
132 parameter DATA13_MAP =
96'h000_000_000_000_000_000_000_000,
133 parameter DATA14_MAP =
96'h000_000_000_000_000_000_000_000,
134 parameter DATA15_MAP =
96'h000_000_000_000_000_000_000_000,
135 parameter DATA16_MAP =
96'h000_000_000_000_000_000_000_000,
136 parameter DATA17_MAP =
96'h000_000_000_000_000_000_000_000,
137 parameter MASK0_MAP =
108'h000_000_000_000_000_000_000_000_000,
138 parameter MASK1_MAP =
108'h000_000_000_000_000_000_000_000_000,
140 // calibration Address. The address given below will be used for calibration
141 // read and write operations.
142 parameter CALIB_ROW_ADD =
16'h0000,
// Calibration row address
143 parameter CALIB_COL_ADD =
12'h000,
// Calibration column address
144 parameter CALIB_BA_ADD =
3'h0,
// Calibration bank address
146 parameter COL_WIDTH =
12,
// column address width
147 parameter CMD_PIPE_PLUS1 =
"ON",
// add pipeline stage between MC and PHY
148 parameter CS_WIDTH =
1,
// # of unique CS outputs
149 parameter CKE_WIDTH =
1,
// # of cke outputs
151 parameter DATA_WIDTH =
64,
152 parameter DATA_BUF_ADDR_WIDTH =
8,
153 parameter DATA_BUF_OFFSET_WIDTH =
1,
154 parameter DDR2_DQSN_ENABLE =
"YES",
// Enable differential DQS for DDR2
155 parameter DM_WIDTH =
8,
// # of DM (data mask)
156 parameter DQ_CNT_WIDTH =
6,
// = ceil(log2(DQ_WIDTH))
157 parameter DQ_WIDTH =
64,
// # of DQ (data)
158 parameter DQS_CNT_WIDTH =
3,
// = ceil(log2(DQS_WIDTH))
159 parameter DQS_WIDTH =
8,
// # of DQS (strobe)
160 parameter DRAM_TYPE =
"DDR3",
161 parameter DRAM_WIDTH =
8,
// # of DQ per DQS
162 parameter ECC =
"OFF",
163 parameter ECC_WIDTH =
8,
164 parameter MC_ERR_ADDR_WIDTH =
31,
165 parameter nAL =
0,
// Additive latency (in clk cyc)
166 parameter nBANK_MACHS =
4,
167 parameter PRE_REV3ES =
"OFF",
// Delay O/Ps using Phaser_Out fine dly
168 parameter nCK_PER_CLK =
4,
// # of memory CKs per fabric CLK
169 parameter nCS_PER_RANK =
1,
// # of unique CS outputs per rank
170 // Hard PHY parameters
171 parameter PHYCTL_CMD_FIFO =
"FALSE",
172 parameter ORDERING =
"NORM",
173 parameter PHASE_DETECT =
"OFF" ,
// to phy_top
174 parameter IBUF_LPWR_MODE =
"OFF",
// to phy_top
175 parameter IODELAY_HP_MODE =
"ON",
// to phy_top
176 parameter BANK_TYPE =
"HP_IO",
// # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
177 parameter DATA_IO_PRIM_TYPE =
"DEFAULT",
// # = "HP_LP", "HR_LP", "DEFAULT"
178 parameter DATA_IO_IDLE_PWRDWN =
"ON",
// "ON" or "OFF"
179 parameter IODELAY_GRP =
"IODELAY_MIG",
//to phy_top
180 parameter OUTPUT_DRV =
"HIGH" ,
// to phy_top
181 parameter REG_CTRL =
"OFF" ,
// to phy_top
182 parameter RTT_NOM =
"60" ,
// to phy_top
183 parameter RTT_WR =
"120" ,
// to phy_top
184 parameter STARVE_LIMIT =
2,
185 parameter tCK =
2500,
// pS
186 parameter tCKE =
10000,
// pS
187 parameter tFAW =
40000,
// pS
188 parameter tPRDI =
1_000_000,
// pS
189 parameter tRAS =
37500,
// pS
190 parameter tRCD =
12500,
// pS
191 parameter tREFI =
7800000,
// pS
192 parameter tRFC =
110000,
// pS
193 parameter tRP =
12500,
// pS
194 parameter tRRD =
10000,
// pS
195 parameter tRTP =
7500,
// pS
196 parameter tWTR =
7500,
// pS
197 parameter tZQI =
128_000_000,
// nS
198 parameter tZQCS =
64,
// CKs
199 parameter WRLVL =
"OFF" ,
// to phy_top
200 parameter DEBUG_PORT =
"OFF" ,
// to phy_top
201 parameter CAL_WIDTH =
"HALF" ,
// to phy_top
202 parameter RANK_WIDTH =
1,
204 parameter ODT_WIDTH =
1,
205 parameter ROW_WIDTH =
16,
// DRAM address bus width
206 parameter [
7:
0]
SLOT_0_CONFIG =
8'b0000_0001,
207 parameter [
7:
0]
SLOT_1_CONFIG =
8'b0000_0000,
208 parameter SIM_BYPASS_INIT_CAL =
"OFF",
209 parameter REFCLK_FREQ =
300.0,
210 parameter nDQS_COL0 =
DQS_WIDTH,
211 parameter nDQS_COL1 =
0,
212 parameter nDQS_COL2 =
0,
213 parameter nDQS_COL3 =
0,
214 parameter DQS_LOC_COL0 =
144'h11100F0E0D0C0B0A09080706050403020100,
215 parameter DQS_LOC_COL1 =
0,
216 parameter DQS_LOC_COL2 =
0,
217 parameter DQS_LOC_COL3 =
0,
218 parameter USE_CS_PORT =
1,
// Support chip select output
219 parameter USE_DM_PORT =
1,
// Support data mask output
220 parameter USE_ODT_PORT =
1,
// Support ODT output
221 parameter MASTER_PHY_CTL =
0,
// The bank number where master PHY_CONTROL resides
222 parameter USER_REFRESH =
"OFF",
// Choose whether MC or User manages REF
223 parameter TEMP_MON_EN =
"ON" // Enable/disable temperature monitoring
236 input [
BANK_WIDTH-
1:
0]
bank,
// To mc0 of mc.v
238 input [
2:
0]
cmd,
// To mc0 of mc.v
239 input [
COL_WIDTH-
1:
0]
col,
// To mc0 of mc.v
241 input [
DATA_BUF_ADDR_WIDTH-
1:
0]
data_buf_addr,
// To mc0 of mc.v
243 input dbg_idel_down_all,
244 input dbg_idel_down_cpt,
245 input dbg_idel_up_all,
246 input dbg_idel_up_cpt,
247 input dbg_sel_all_idel_cpt,
248 input [
DQS_CNT_WIDTH-
1:
0]
dbg_sel_idel_cpt,
249 input hi_priority,
// To mc0 of mc.v
250 input [
RANK_WIDTH-
1:
0]
rank,
// To mc0 of mc.v
251 input [
2*
nCK_PER_CLK-
1:
0]
raw_not_ecc,
252 input [
ROW_WIDTH-
1:
0]
row,
// To mc0 of mc.v
253 input rst,
// To mc0 of mc.v, ...
254 input size,
// To mc0 of mc.v
255 input [
7:
0]
slot_0_present,
// To mc0 of mc.v
256 input [
7:
0]
slot_1_present,
// To mc0 of mc.v
257 input use_addr,
// To mc0 of mc.v
258 input [
2*
nCK_PER_CLK*
PAYLOAD_WIDTH-
1:
0]
wr_data,
259 input [
2*
nCK_PER_CLK*
DATA_WIDTH/
8-
1:
0]
wr_data_mask,
261 output accept,
// From mc0 of mc.v
262 output accept_ns,
// From mc0 of mc.v
263 output [
BM_CNT_WIDTH-
1:
0]
bank_mach_next,
// From mc0 of mc.v
266 output app_sr_active,
272 output [
255:
0]
dbg_calib_top,
273 output [
6*
DQS_WIDTH*
RANKS-
1:
0]
dbg_cpt_first_edge_cnt,
274 output [
6*
DQS_WIDTH*
RANKS-
1:
0]
dbg_cpt_second_edge_cnt,
275 output [
255:
0]
dbg_phy_rdlvl,
276 output [
99:
0]
dbg_phy_wrcal,
277 output [
6*
DQS_WIDTH-
1:
0]
dbg_final_po_fine_tap_cnt,
278 output [
3*
DQS_WIDTH-
1:
0]
dbg_final_po_coarse_tap_cnt,
279 output [
DQS_WIDTH-
1:
0]
dbg_rd_data_edge_detect,
280 output [
2*
nCK_PER_CLK*
DQ_WIDTH-
1:
0]
dbg_rddata,
281 output [
1:
0]
dbg_rdlvl_done,
282 output [
1:
0]
dbg_rdlvl_err,
283 output [
1:
0]
dbg_rdlvl_start,
284 output [
5:
0]
dbg_tap_cnt_during_wrlvl,
285 output dbg_wl_edge_detect_valid,
286 output dbg_wrlvl_done,
287 output dbg_wrlvl_err,
288 output dbg_wrlvl_start,
290 output [
ROW_WIDTH-
1:
0]
ddr_addr,
// From phy_top0 of phy_top.v
291 output [
BANK_WIDTH-
1:
0]
ddr_ba,
// From phy_top0 of phy_top.v
292 output ddr_cas_n,
// From phy_top0 of phy_top.v
293 output [
CK_WIDTH-
1:
0]
ddr_ck_n,
// From phy_top0 of phy_top.v
294 output [
CK_WIDTH-
1:
0]
ddr_ck ,
// From phy_top0 of phy_top.v
295 output [
CKE_WIDTH-
1:
0]
ddr_cke,
// From phy_top0 of phy_top.v
296 output [
CS_WIDTH*
nCS_PER_RANK-
1:
0]
ddr_cs_n,
// From phy_top0 of phy_top.v
297 output [
DM_WIDTH-
1:
0]
ddr_dm,
// From phy_top0 of phy_top.v
298 output [
ODT_WIDTH-
1:
0]
ddr_odt,
// From phy_top0 of phy_top.v
299 output ddr_ras_n,
// From phy_top0 of phy_top.v
300 output ddr_reset_n,
// From phy_top0 of phy_top.v
302 output ddr_we_n,
// From phy_top0 of phy_top.v
303 output init_calib_complete,
304 output init_wrcal_complete,
305 output [
MC_ERR_ADDR_WIDTH-
1:
0]
ecc_err_addr,
306 output [
2*
nCK_PER_CLK-
1:
0]
ecc_multiple,
307 output [
2*
nCK_PER_CLK-
1:
0]
ecc_single,
309 output wire [
2*
nCK_PER_CLK*
PAYLOAD_WIDTH-
1:
0]
rd_data,
310 output [
DATA_BUF_ADDR_WIDTH-
1:
0]
rd_data_addr,
312 output rd_data_en,
// From mc0 of mc.v
313 output rd_data_end,
// From mc0 of mc.v
314 output [
DATA_BUF_OFFSET_WIDTH-
1:
0]
rd_data_offset,
// From mc0 of mc.v
315 output [
DATA_BUF_ADDR_WIDTH-
1:
0]
wr_data_addr,
// From mc0 of mc.v
316 output wr_data_en,
// From mc0 of mc.v
317 output [
DATA_BUF_OFFSET_WIDTH-
1:
0]
wr_data_offset,
// From mc0 of mc.v
319 inout [
DQ_WIDTH-
1:
0]
ddr_dq,
// To/From phy_top0 of phy_top.v
320 inout [
DQS_WIDTH-
1:
0]
ddr_dqs_n,
// To/From phy_top0 of phy_top.v
321 inout [
DQS_WIDTH-
1:
0]
ddr_dqs // To/From phy_top0 of phy_top.v
323 ,
input [
11:
0]
device_temp
325 ,
input dbg_sel_pi_incdec
326 ,
input dbg_sel_po_incdec
327 ,
input [
DQS_CNT_WIDTH:
0]
dbg_byte_sel
331 ,
input dbg_po_f_stg23_sel
333 ,
output [
6*
DQS_WIDTH*
RANKS-
1:
0]
dbg_cpt_tap_cnt
334 ,
output [
5*
DQS_WIDTH*
RANKS-
1:
0]
dbg_dq_idelay_tap_cnt
335 ,
output dbg_rddata_valid
336 ,
output [
6*
DQS_WIDTH-
1:
0]
dbg_wrlvl_fine_tap_cnt
337 ,
output [
3*
DQS_WIDTH-
1:
0]
dbg_wrlvl_coarse_tap_cnt
338 ,
output [
255:
0]
dbg_phy_wrlvl
339 ,
output [
5:
0]
dbg_pi_counter_read_val
340 ,
output [
8:
0]
dbg_po_counter_read_val
342 ,
input rst_phaser_ref
343 ,
output [
6*
RANKS-
1:
0]
dbg_rd_data_offset
344 ,
output [
255:
0]
dbg_phy_init
345 ,
output [
255:
0]
dbg_prbs_rdlvl
346 ,
output [
255:
0]
dbg_dqs_found_cal
347 ,
output dbg_pi_phaselock_start
348 ,
output dbg_pi_phaselocked_done
349 ,
output dbg_pi_phaselock_err
350 ,
output dbg_pi_dqsfound_start
351 ,
output dbg_pi_dqsfound_done
352 ,
output dbg_pi_dqsfound_err
353 ,
output dbg_wrcal_start
354 ,
output dbg_wrcal_done
355 ,
output dbg_wrcal_err
356 ,
output [
11:
0]
dbg_pi_dqs_found_lanes_phy4lanes
357 ,
output [
11:
0]
dbg_pi_phase_locked_phy4lanes
358 ,
output [
6*
RANKS-
1:
0]
dbg_calib_rd_data_offset_1
359 ,
output [
6*
RANKS-
1:
0]
dbg_calib_rd_data_offset_2
360 ,
output [
5:
0]
dbg_data_offset
361 ,
output [
5:
0]
dbg_data_offset_1
362 ,
output [
5:
0]
dbg_data_offset_2
363 ,
output dbg_oclkdelay_calib_start
364 ,
output dbg_oclkdelay_calib_done
365 ,
output [
255:
0]
dbg_phy_oclkdelay_cal
366 ,
output [
DRAM_WIDTH*
16 -
1:
0]
dbg_oclkdelay_rd_data
370 localparam nSLOTS =
1 + (|
SLOT_1_CONFIG ?
1 :
0);
371 localparam SLOT_0_CONFIG_MC = (
nSLOTS ==
2)?
8'b0000_0101 :
8'b0000_1111;
372 localparam SLOT_1_CONFIG_MC = (
nSLOTS ==
2)?
8'b0000_1010 :
8'b0000_0000;
374 reg [
7:
0]
slot_0_present_mc;
375 reg [
7:
0]
slot_1_present_mc;
377 reg user_periodic_rd_req =
1'b0;
378 reg user_ref_req =
1'b0;
379 reg user_zq_req =
1'b0;
382 wire [
nCK_PER_CLK-
1:
0]
mc_ras_n;
383 wire [
nCK_PER_CLK-
1:
0]
mc_cas_n;
384 wire [
nCK_PER_CLK-
1:
0]
mc_we_n;
385 wire [
nCK_PER_CLK*
ROW_WIDTH-
1:
0]
mc_address;
386 wire [
nCK_PER_CLK*
BANK_WIDTH-
1:
0]
mc_bank;
387 wire [
nCK_PER_CLK-
1 :
0]
mc_cke ;
389 wire [
CS_WIDTH*
nCS_PER_RANK*
nCK_PER_CLK-
1:
0]
mc_cs_n;
391 wire [
2*
nCK_PER_CLK*
DQ_WIDTH-
1:
0]
mc_wrdata;
392 wire [
2*
nCK_PER_CLK*
DQ_WIDTH/
8-
1:
0]
mc_wrdata_mask;
395 wire tempmon_sample_en;
401 wire [
1:
0]
mc_cas_slot;
402 wire [
5:
0]
mc_data_offset;
403 wire [
5:
0]
mc_data_offset_1;
404 wire [
5:
0]
mc_data_offset_2;
405 wire [
3:
0]
mc_aux_out0;
406 wire [
3:
0]
mc_aux_out1;
407 wire [
1:
0]
mc_rank_cnt;
409 wire phy_mc_ctl_full;
410 wire phy_mc_cmd_full;
411 wire phy_mc_data_full;
412 wire [
2*
nCK_PER_CLK*
DQ_WIDTH-
1:
0]
phy_rd_data;
413 wire phy_rddata_valid;
415 wire [
6*
RANKS-
1:
0]
calib_rd_data_offset_0;
416 wire [
6*
RANKS-
1:
0]
calib_rd_data_offset_1;
417 wire [
6*
RANKS-
1:
0]
calib_rd_data_offset_2;
418 wire init_calib_complete_w;
419 wire init_wrcal_complete_w;
422 // assigning CWL = CL -1 for DDR2. DDR2 customers will not know anything
423 // about CWL. There is also nCWL parameter. Need to clean it up.
424 localparam CWL_T = (
DRAM_TYPE ==
"DDR3") ?
CWL :
CL-
1;
426 assign init_calib_complete =
init_calib_complete_w;
427 assign init_wrcal_complete =
init_wrcal_complete_w;
428 assign mux_calib_complete = (
PRE_REV3ES ==
"OFF") ?
init_calib_complete_w :
429 (
init_calib_complete_w |
init_wrcal_complete_w);
430 assign mux_rst = (
PRE_REV3ES ==
"OFF") ?
rst :
reset;
431 assign dbg_calib_rd_data_offset_1 =
calib_rd_data_offset_1;
432 assign dbg_calib_rd_data_offset_2 =
calib_rd_data_offset_2;
433 assign dbg_data_offset =
mc_data_offset;
434 assign dbg_data_offset_1 =
mc_data_offset_1;
435 assign dbg_data_offset_2 =
mc_data_offset_2;
437 // Enable / disable temperature monitoring
438 assign tempmon_sample_en =
TEMP_MON_EN ==
"OFF" ?
1'b0 :
mc_ref_zq_wip;
441 if (
nSLOTS ==
1)
begin:
gen_single_slot_odt
442 always @ (
slot_0_present or slot_1_present)
begin
443 slot_0_present_mc =
slot_0_present;
444 slot_1_present_mc =
slot_1_present;
446 end else if (
nSLOTS ==
2)
begin:
gen_dual_slot_odt
447 always @ (
slot_0_present[
0]
or slot_0_present[
1]
448 or slot_1_present[
0]
or slot_1_present[
1])
begin
449 case ({
slot_0_present[
0],
slot_0_present[
1],
450 slot_1_present[
0],
slot_1_present[
1]})
451 //Two slot configuration, one slot present, single rank
453 slot_0_present_mc =
8'b0000_0001;
454 slot_1_present_mc =
8'b0000_0000;
457 slot_0_present_mc =
8'b0000_0000;
458 slot_1_present_mc =
8'b0000_0010;
460 // Two slot configuration, one slot present, dual rank
462 slot_0_present_mc =
8'b0000_0101;
463 slot_1_present_mc =
8'b0000_0000;
466 slot_0_present_mc =
8'b0000_0000;
467 slot_1_present_mc =
8'b0000_1010;
469 // Two slot configuration, one rank per slot
471 slot_0_present_mc =
8'b0000_0001;
472 slot_1_present_mc =
8'b0000_0010;
474 // Two Slots - One slot with dual rank and the other with single rank
476 slot_0_present_mc =
8'b0000_0001;
477 slot_1_present_mc =
8'b0000_1010;
480 slot_0_present_mc =
8'b0000_0101;
481 slot_1_present_mc =
8'b0000_0010;
483 // Two Slots - two ranks per slot
485 slot_0_present_mc =
8'b0000_0101;
486 slot_1_present_mc =
8'b0000_1010;
496 .
PAYLOAD_WIDTH (
PAYLOAD_WIDTH),
497 .
MC_ERR_ADDR_WIDTH (
MC_ERR_ADDR_WIDTH),
498 .
ADDR_CMD_MODE (
ADDR_CMD_MODE),
499 .
BANK_WIDTH (
BANK_WIDTH),
500 .
BM_CNT_WIDTH (
BM_CNT_WIDTH),
501 .
BURST_MODE (
BURST_MODE),
502 .
COL_WIDTH (
COL_WIDTH),
503 .
CMD_PIPE_PLUS1 (
CMD_PIPE_PLUS1),
504 .
CS_WIDTH (
CS_WIDTH),
505 .
DATA_WIDTH (
DATA_WIDTH),
506 .
DATA_BUF_ADDR_WIDTH (
DATA_BUF_ADDR_WIDTH),
507 .
DATA_BUF_OFFSET_WIDTH (
DATA_BUF_OFFSET_WIDTH),
508 .
DRAM_TYPE (
DRAM_TYPE),
509 .
CKE_ODT_AUX (
CKE_ODT_AUX),
510 .
DQS_WIDTH (
DQS_WIDTH),
511 .
DQ_WIDTH (
DQ_WIDTH),
513 .
ECC_WIDTH (
ECC_WIDTH),
514 .
nBANK_MACHS (
nBANK_MACHS),
515 .
nCK_PER_CLK (
nCK_PER_CLK),
518 .
nCS_PER_RANK (
nCS_PER_RANK),
520 .
ORDERING (
ORDERING),
521 .
RANK_WIDTH (
RANK_WIDTH),
523 .
REG_CTRL (
REG_CTRL),
524 .
ROW_WIDTH (
ROW_WIDTH),
527 .
STARVE_LIMIT (
STARVE_LIMIT),
528 .
SLOT_0_CONFIG (
SLOT_0_CONFIG_MC),
529 .
SLOT_1_CONFIG (
SLOT_1_CONFIG_MC),
544 .
USER_REFRESH (
USER_REFRESH))
546 (.
app_periodic_rd_req (
1'b0),
547 .
app_sr_req (
app_sr_req),
548 .
app_sr_active (
app_sr_active),
549 .
app_ref_req (
app_ref_req),
550 .
app_ref_ack (
app_ref_ack),
551 .
app_zq_req (
app_zq_req),
552 .
app_zq_ack (
app_zq_ack),
553 .
ecc_single (
ecc_single),
554 .
ecc_multiple (
ecc_multiple),
555 .
ecc_err_addr (
ecc_err_addr),
556 .
mc_address (
mc_address),
557 .
mc_aux_out0 (
mc_aux_out0),
558 .
mc_aux_out1 (
mc_aux_out1),
562 .
mc_cas_n (
mc_cas_n),
564 .
mc_cmd_wren (
mc_cmd_wren),
566 .
mc_ctl_wren (
mc_ctl_wren),
567 .
mc_data_offset (
mc_data_offset),
568 .
mc_data_offset_1 (
mc_data_offset_1),
569 .
mc_data_offset_2 (
mc_data_offset_2),
570 .
mc_cas_slot (
mc_cas_slot),
571 .
mc_rank_cnt (
mc_rank_cnt),
572 .
mc_ras_n (
mc_ras_n),
573 .
mc_reset_n (
mc_reset_n),
575 .
mc_wrdata (
mc_wrdata),
576 .
mc_wrdata_en (
mc_wrdata_en),
577 .
mc_wrdata_mask (
mc_wrdata_mask),
580 .
accept_ns (
accept_ns),
581 .
bank_mach_next (
bank_mach_next[
BM_CNT_WIDTH-
1:
0]),
582 .
rd_data_addr (
rd_data_addr[
DATA_BUF_ADDR_WIDTH-
1:
0]),
583 .
rd_data_en (
rd_data_en),
584 .
rd_data_end (
rd_data_end),
585 .
rd_data_offset (
rd_data_offset),
586 .
wr_data_addr (
wr_data_addr[
DATA_BUF_ADDR_WIDTH-
1:
0]),
587 .
wr_data_en (
wr_data_en),
588 .
wr_data_offset (
wr_data_offset),
591 .
wr_data_mask (
wr_data_mask),
592 .
mc_read_idle (
idle),
593 .
mc_ref_zq_wip (
mc_ref_zq_wip),
595 .
init_calib_complete (
mux_calib_complete),
596 .
calib_rd_data_offset (
calib_rd_data_offset_0),
597 .
calib_rd_data_offset_1 (
calib_rd_data_offset_1),
598 .
calib_rd_data_offset_2 (
calib_rd_data_offset_2),
599 .
phy_mc_ctl_full (
phy_mc_ctl_full),
600 .
phy_mc_cmd_full (
phy_mc_cmd_full),
601 .
phy_mc_data_full (
phy_mc_data_full),
602 .
phy_rd_data (
phy_rd_data),
603 .
phy_rddata_valid (
phy_rddata_valid),
604 .
correct_en (
correct_en),
605 .
bank (
bank[
BANK_WIDTH-
1:
0]),
608 .
col (
col[
COL_WIDTH-
1:
0]),
609 .
data_buf_addr (
data_buf_addr[
DATA_BUF_ADDR_WIDTH-
1:
0]),
610 .
hi_priority (
hi_priority),
611 .
rank (
rank[
RANK_WIDTH-
1:
0]),
612 .
raw_not_ecc (
raw_not_ecc[
2*
nCK_PER_CLK-
1 :
0]),
613 .
row (
row[
ROW_WIDTH-
1:
0]),
616 .
slot_0_present (
slot_0_present_mc[
7:
0]),
617 .
slot_1_present (
slot_1_present_mc[
7:
0]),
618 .
use_addr (
use_addr));
620 // following calculations should be moved inside PHY
621 // odt bus should be added to PHY.
622 localparam CLK_PERIOD =
tCK *
nCK_PER_CLK;
624 localparam nCWL =
CWL_T;
626 ddr2_improper_CL: assert property
627 (@(
posedge clk) (~((DRAM_TYPE ==
"DDR2") && ((CL >
6) || (CL <
3)))));
628 // Not needed after the CWL fix for DDR2
629 // ddr2_improper_CWL: assert property
630 // (@(posedge clk) (~((DRAM_TYPE == "DDR2") && ((CL - CWL) != 1))));
633 mig_7series_v1_9_ddr_phy_top #
636 .REFCLK_FREQ (REFCLK_FREQ),
637 .BYTE_LANES_B0 (BYTE_LANES_B0),
638 .BYTE_LANES_B1 (BYTE_LANES_B1),
639 .BYTE_LANES_B2 (BYTE_LANES_B2),
640 .BYTE_LANES_B3 (BYTE_LANES_B3),
641 .BYTE_LANES_B4 (BYTE_LANES_B4),
642 .PHY_0_BITLANES (PHY_0_BITLANES),
643 .PHY_1_BITLANES (PHY_1_BITLANES),
644 .PHY_2_BITLANES (PHY_2_BITLANES),
645 .CA_MIRROR (CA_MIRROR),
646 .CK_BYTE_MAP (CK_BYTE_MAP),
647 .ADDR_MAP (ADDR_MAP),
648 .BANK_MAP (BANK_MAP),
650 .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
653 .CKE_ODT_AUX (CKE_ODT_AUX),
655 .PARITY_MAP (PARITY_MAP),
658 .DQS_BYTE_MAP (DQS_BYTE_MAP),
659 .DATA0_MAP (DATA0_MAP),
660 .DATA1_MAP (DATA1_MAP),
661 .DATA2_MAP (DATA2_MAP),
662 .DATA3_MAP (DATA3_MAP),
663 .DATA4_MAP (DATA4_MAP),
664 .DATA5_MAP (DATA5_MAP),
665 .DATA6_MAP (DATA6_MAP),
666 .DATA7_MAP (DATA7_MAP),
667 .DATA8_MAP (DATA8_MAP),
668 .DATA9_MAP (DATA9_MAP),
669 .DATA10_MAP (DATA10_MAP),
670 .DATA11_MAP (DATA11_MAP),
671 .DATA12_MAP (DATA12_MAP),
672 .DATA13_MAP (DATA13_MAP),
673 .DATA14_MAP (DATA14_MAP),
674 .DATA15_MAP (DATA15_MAP),
675 .DATA16_MAP (DATA16_MAP),
676 .DATA17_MAP (DATA17_MAP),
677 .MASK0_MAP (MASK0_MAP),
678 .MASK1_MAP (MASK1_MAP),
679 .CALIB_ROW_ADD (CALIB_ROW_ADD),
680 .CALIB_COL_ADD (CALIB_COL_ADD),
681 .CALIB_BA_ADD (CALIB_BA_ADD),
682 .nCS_PER_RANK (nCS_PER_RANK),
683 .CS_WIDTH (CS_WIDTH),
684 .nCK_PER_CLK (nCK_PER_CLK),
685 .PRE_REV3ES (PRE_REV3ES),
686 .CKE_WIDTH (CKE_WIDTH),
687 .DATA_CTL_B0 (DATA_CTL_B0),
688 .DATA_CTL_B1 (DATA_CTL_B1),
689 .DATA_CTL_B2 (DATA_CTL_B2),
690 .DATA_CTL_B3 (DATA_CTL_B3),
691 .DATA_CTL_B4 (DATA_CTL_B4),
692 .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
693 .DRAM_TYPE (DRAM_TYPE),
694 .BANK_WIDTH (BANK_WIDTH),
695 .CK_WIDTH (CK_WIDTH),
696 .COL_WIDTH (COL_WIDTH),
697 .DM_WIDTH (DM_WIDTH),
698 .DQ_WIDTH (DQ_WIDTH),
699 .DQS_CNT_WIDTH (DQS_CNT_WIDTH),
700 .DQS_WIDTH (DQS_WIDTH),
701 .DRAM_WIDTH (DRAM_WIDTH),
702 .PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO),
703 .ROW_WIDTH (ROW_WIDTH),
705 .ADDR_CMD_MODE (ADDR_CMD_MODE),
706 .BURST_MODE (BURST_MODE),
707 .BURST_TYPE (BURST_TYPE),
712 .OUTPUT_DRV (OUTPUT_DRV),
714 .ODT_WIDTH (ODT_WIDTH),
715 .REG_CTRL (REG_CTRL),
718 .SLOT_1_CONFIG (SLOT_1_CONFIG),
720 .IODELAY_HP_MODE (IODELAY_HP_MODE),
721 .BANK_TYPE (BANK_TYPE),
722 .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
723 .DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN),
724 .IODELAY_GRP (IODELAY_GRP),
725 // Prevent the following simulation-related parameters from
726 // being overridden for synthesis - for synthesis only the
727 // default values of these parameters should be used
728 // synthesis translate_off
729 .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
730 // synthesis translate_on
731 .USE_CS_PORT (USE_CS_PORT),
732 .USE_DM_PORT (USE_DM_PORT),
733 .USE_ODT_PORT (USE_ODT_PORT),
734 .MASTER_PHY_CTL (MASTER_PHY_CTL),
735 .DEBUG_PORT (DEBUG_PORT)
740 .calib_rd_data_offset_0 (calib_rd_data_offset_0),
741 .calib_rd_data_offset_1 (calib_rd_data_offset_1),
742 .calib_rd_data_offset_2 (calib_rd_data_offset_2),
744 .ddr_ck_n (ddr_ck_n),
745 .ddr_addr (ddr_addr),
747 .ddr_ras_n (ddr_ras_n),
748 .ddr_cas_n (ddr_cas_n),
749 .ddr_we_n (ddr_we_n),
750 .ddr_cs_n (ddr_cs_n),
753 .ddr_reset_n (ddr_reset_n),
754 .ddr_parity (ddr_parity),
756 .dbg_calib_top (dbg_calib_top),
757 .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
758 .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
759 .dbg_phy_rdlvl (dbg_phy_rdlvl),
760 .dbg_phy_wrcal (dbg_phy_wrcal),
761 .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
762 .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
763 .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
764 .dbg_rddata (dbg_rddata),
765 .dbg_rdlvl_done (dbg_rdlvl_done),
766 .dbg_rdlvl_err (dbg_rdlvl_err),
767 .dbg_rdlvl_start (dbg_rdlvl_start),
768 .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
769 .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
770 .dbg_wrlvl_done (dbg_wrlvl_done),
771 .dbg_wrlvl_err (dbg_wrlvl_err),
772 .dbg_wrlvl_start (dbg_wrlvl_start),
773 .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
774 .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
775 .init_calib_complete (init_calib_complete_w),
776 .init_wrcal_complete (init_wrcal_complete_w),
777 .mc_address (mc_address),
778 .mc_aux_out0 (mc_aux_out0),
779 .mc_aux_out1 (mc_aux_out1),
783 .mc_cas_n (mc_cas_n),
785 .mc_cmd_wren (mc_cmd_wren),
786 .mc_cas_slot (mc_cas_slot),
788 .mc_ctl_wren (mc_ctl_wren),
789 .mc_data_offset (mc_data_offset),
790 .mc_data_offset_1 (mc_data_offset_1),
791 .mc_data_offset_2 (mc_data_offset_2),
792 .mc_rank_cnt (mc_rank_cnt),
793 .mc_ras_n (mc_ras_n),
794 .mc_reset_n (mc_reset_n),
796 .mc_wrdata (mc_wrdata),
797 .mc_wrdata_en (mc_wrdata_en),
798 .mc_wrdata_mask (mc_wrdata_mask),
800 .mem_refclk (mem_refclk),
801 .phy_mc_ctl_full (phy_mc_ctl_full),
802 .phy_mc_cmd_full (phy_mc_cmd_full),
803 .phy_mc_data_full (phy_mc_data_full),
804 .phy_rd_data (phy_rd_data),
805 .phy_rddata_valid (phy_rddata_valid),
806 .pll_lock (pll_lock),
807 .sync_pulse (sync_pulse),
810 .ddr_dqs_n (ddr_dqs_n),
814 .freq_refclk (freq_refclk),
818 .rst_tg_mc (rst_tg_mc),
819 .slot_0_present (slot_0_present),
820 .slot_1_present (slot_1_present),
821 .dbg_idel_up_all (dbg_idel_up_all),
822 .dbg_idel_down_all (dbg_idel_down_all),
823 .dbg_idel_up_cpt (dbg_idel_up_cpt),
824 .dbg_idel_down_cpt (dbg_idel_down_cpt),
825 .dbg_sel_idel_cpt (dbg_sel_idel_cpt),
826 .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt)
828 ,.device_temp (device_temp)
829 ,.tempmon_sample_en (tempmon_sample_en)
830 ,.dbg_sel_pi_incdec (dbg_sel_pi_incdec)
831 ,.dbg_sel_po_incdec (dbg_sel_po_incdec)
832 ,.dbg_byte_sel (dbg_byte_sel)
833 ,.dbg_pi_f_inc (dbg_pi_f_inc)
834 ,.dbg_po_f_inc (dbg_po_f_inc)
835 ,.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel)
836 ,.dbg_pi_f_dec (dbg_pi_f_dec)
837 ,.dbg_po_f_dec (dbg_po_f_dec)
838 ,.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt)
839 ,.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt)
840 ,.dbg_rddata_valid (dbg_rddata_valid)
841 ,.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt)
842 ,.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt)
843 ,.dbg_phy_wrlvl (dbg_phy_wrlvl)
844 ,.ref_dll_lock (ref_dll_lock)
845 ,.rst_phaser_ref (rst_phaser_ref)
846 ,.dbg_rd_data_offset (dbg_rd_data_offset)
847 ,.dbg_phy_init (dbg_phy_init)
848 ,.dbg_prbs_rdlvl (dbg_prbs_rdlvl)
849 ,.dbg_dqs_found_cal (dbg_dqs_found_cal)
850 ,.dbg_po_counter_read_val (dbg_po_counter_read_val)
851 ,.dbg_pi_counter_read_val (dbg_pi_counter_read_val)
852 ,.dbg_pi_phaselock_start (dbg_pi_phaselock_start)
853 ,.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done)
854 ,.dbg_pi_phaselock_err (dbg_pi_phaselock_err)
855 ,.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start)
856 ,.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done)
857 ,.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err)
858 ,.dbg_wrcal_start (dbg_wrcal_start)
859 ,.dbg_wrcal_done (dbg_wrcal_done)
860 ,.dbg_wrcal_err (dbg_wrcal_err)
861 ,.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal)
862 ,.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data)
863 ,.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start)
864 ,.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done)
1.8.1
