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ddr3_1_9_a
ecc
mig_7series_v1_9_ecc_gen.v
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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : ecc_gen.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Tue Jun 30 2009
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// \___\/\___\
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//
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//Device : 7-Series
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//Design Name : DDR3 SDRAM
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//Purpose :
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//Reference :
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//Revision History :
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//*****************************************************************************
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`timescale
1ps/1ps
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// Generate the ecc code. Note that the synthesizer should
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// generate this as a static logic. Code in this block should
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// never run during simulation phase, or directly impact timing.
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//
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// The code generated is a single correct, double detect code.
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// It is the classic Hamming code. Instead, the code is
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// optimized for minimal/balanced tree depth and size. See
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// Hsiao IBM Technial Journal 1970.
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//
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// The code is returned as a single bit vector, h_rows. This was
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// the only way to "subroutinize" this with the restrictions of
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// disallowed include files and that matrices cannot be passed
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// in ports.
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//
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// Factorial and the combos functions are defined. Combos
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// simply computes the number of combinations from the set
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// size and elements at a time.
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//
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// The function next_combo computes the next combination in
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// lexicographical order given the "current" combination. Its
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// output is undefined if given the last combination in the
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// lexicographical order.
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//
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// next_combo is insensitive to the number of elements in the
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// combinations.
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//
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// An H transpose matrix is generated because that's the easiest
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// way to do it. The H transpose matrix is generated by taking
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// the one at a time combinations, then the 3 at a time, then
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// the 5 at a time. The number combinations used is equal to
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// the width of the code (CODE_WIDTH). The boundaries between
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// the 1, 3 and 5 groups are hardcoded in the for loop.
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//
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// At the same time the h_rows vector is generated from the
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// H transpose matrix.
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module
mig_7series_v1_9_ecc_gen
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#(
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parameter
CODE_WIDTH
=
72
,
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parameter
ECC_WIDTH
=
8
,
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parameter
DATA_WIDTH
=
64
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)
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(
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/*AUTOARG**/
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// Outputs
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h_rows
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);
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function
integer
factorial
(
input
integer
i
);
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integer
index
;
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if
(
i
==
1
)
factorial
=
1
;
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else
begin
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factorial
=
1
;
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for
(
index
=
2
;
index
<=
i
;
index
=
index
+
1
)
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factorial
=
factorial
*
index
;
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end
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endfunction
// factorial
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function
integer
combos
(
input
integer
n
,
k
);
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combos
=
factorial
(
n
)/(
factorial
(
k
)*
factorial
(
n
-
k
));
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endfunction
// combinations
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// function next_combo
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// Given a combination, return the next combo in lexicographical
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// order. Scans from right to left. Assumes the first combination
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// is k ones all of the way to the left.
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//
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// Upon entry, initialize seen0, trig1, and ones. "seen0" means
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// that a zero has been observed while scanning from right to left.
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// "trig1" means that a one have been observed _after_ seen0 is set.
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// "ones" counts the number of ones observed while scanning the input.
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//
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// If trig1 is one, just copy the input bit to the output and increment
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// to the next bit. Otherwise set the the output bit to zero, if the
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// input is a one, increment ones. If the input bit is a one and seen0
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// is true, dump out the accumulated ones. Set seen0 to the complement
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// of the input bit. Note that seen0 is not used subsequent to trig1
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// getting set.
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function
[
ECC_WIDTH
-
1
:
0
]
next_combo
(
input
[
ECC_WIDTH
-
1
:
0
]
i
);
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integer
index
;
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integer
dump_index
;
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reg
seen0
;
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reg
trig1
;
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// integer ones;
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reg
[
ECC_WIDTH
-
1
:
0
]
ones
;
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begin
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seen0
=
1'b0
;
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trig1
=
1'b0
;
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ones
=
0
;
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for
(
index
=
0
;
index
<
ECC_WIDTH
;
index
=
index
+
1
)
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begin
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// The "== 1'bx" is so this will converge at time zero.
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// XST assumes false, which should be OK.
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if
((&
i
==
1'bx
) ||
trig1
)
next_combo
[
index
] =
i
[
index
];
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else
begin
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next_combo
[
index
] =
1'b0
;
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ones
=
ones
+
i
[
index
];
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if
(
i
[
index
] &&
seen0
)
begin
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trig1
=
1'b1
;
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for
(
dump_index
=
index
-
1
;
dump_index
>=
0
;
dump_index
=
dump_index
-
1
)
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if
(
dump_index
>=
index
-
ones
)
next_combo
[
dump_index
] =
1'b1
;
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end
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seen0
= ~
i
[
index
];
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end
// else: !if(trig1)
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end
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end
// function
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endfunction
// next_combo
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wire
[
ECC_WIDTH
-
1
:
0
]
ht_matrix
[
CODE_WIDTH
-
1
:
0
];
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output
wire
[
CODE_WIDTH
*
ECC_WIDTH
-
1
:
0
]
h_rows
;
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localparam
COMBOS_3
=
combos
(
ECC_WIDTH
,
3
);
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localparam
COMBOS_5
=
combos
(
ECC_WIDTH
,
5
);
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genvar
n
;
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genvar
s
;
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generate
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for
(
n
=
0
;
n
<
CODE_WIDTH
;
n
=
n
+
1
)
begin
:
ht
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if
(
n
==
0
)
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assign
ht_matrix
[
n
] = {{
3
{
1'b1
}}, {
ECC_WIDTH
-
3
{
1'b0
}}};
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else
if
(
n
==
COMBOS_3
&&
n
<
DATA_WIDTH
)
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assign
ht_matrix
[
n
] = {{
5
{
1'b1
}}, {
ECC_WIDTH
-
5
{
1'b0
}}};
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else
if
((
n
==
COMBOS_3
+
COMBOS_5
) &&
n
<
DATA_WIDTH
)
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assign
ht_matrix
[
n
] = {{
7
{
1'b1
}}, {
ECC_WIDTH
-
7
{
1'b0
}}};
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else
if
(
n
==
DATA_WIDTH
)
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assign
ht_matrix
[
n
] = {{
1
{
1'b1
}}, {
ECC_WIDTH
-
1
{
1'b0
}}};
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else
assign
ht_matrix
[
n
] =
next_combo
(
ht_matrix
[
n
-
1
]);
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for
(
s
=
0
;
s
<
ECC_WIDTH
;
s
=
s
+
1
)
begin
:
h_row
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assign
h_rows
[
s
*
CODE_WIDTH
+
n
] =
ht_matrix
[
n
][
s
];
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end
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end
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endgenerate
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endmodule
// ecc_gen
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