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49 // THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
53 // Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $
55 // $DateTime: 2010/05/11 18:05:17 $
58 // This verilog file is the parameterizable 4-byte lane phy primitive top
59 // This module may be ganged to create an N-lane phy.
62 // Date Engineer Description
63 // 04/01/2010 G. Martin Initial Checkin.
65 ///////////////////////////////////////////////////////////
66 ***********************************************************/
73 parameter GENERATE_IDELAYCTRL =
"TRUE",
74 parameter IODELAY_GRP =
"IODELAY_MIG",
75 parameter BANK_TYPE =
"HP_IO",
// # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
76 parameter BYTELANES_DDR_CK =
24'b0010_0010_0010_0010_0010_0010,
77 parameter NUM_DDR_CK =
1,
78 // next three parameter fields correspond to byte lanes for lane order DCBA
79 parameter BYTE_LANES =
4'b1111,
// lane existence, one per lane
80 parameter DATA_CTL_N =
4'b1111,
// data or control, per lane
81 parameter BITLANES =
48'hffff_ffff_ffff,
82 parameter BITLANES_OUTONLY =
48'h0000_0000_0000,
83 parameter LANE_REMAP =
16'h3210,
// 4-bit index
84 // used to rewire to one of four
85 // input/output buss lanes
86 // example: 0321 remaps lanes as:
91 parameter LAST_BANK =
"FALSE",
92 parameter USE_PRE_POST_FIFO =
"FALSE",
93 parameter RCLK_SELECT_LANE =
"B",
94 parameter real TCK =
0.00,
95 parameter SYNTHESIS =
"FALSE",
96 parameter PO_CTL_COARSE_BYPASS =
"FALSE",
97 parameter PO_FINE_DELAY =
0,
98 parameter PI_SEL_CLK_OFFSET =
0,
100 // phy_control paramter used in other paramsters
101 parameter PC_CLK_RATIO =
4,
103 //phaser_in parameters
104 parameter A_PI_FREQ_REF_DIV =
"NONE",
105 parameter A_PI_CLKOUT_DIV =
2,
106 parameter A_PI_BURST_MODE =
"TRUE",
107 parameter A_PI_OUTPUT_CLK_SRC =
"DELAYED_REF" ,
//"DELAYED_REF",
108 parameter A_PI_FINE_DELAY =
60,
109 parameter A_PI_SYNC_IN_DIV_RST =
"TRUE",
111 parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
112 parameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
113 parameter B_PI_BURST_MODE = A_PI_BURST_MODE,
114 parameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
115 parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY,
116 parameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
118 parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
119 parameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
120 parameter C_PI_BURST_MODE = A_PI_BURST_MODE,
121 parameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
122 parameter C_PI_FINE_DELAY =
0,
123 parameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
125 parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
126 parameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
127 parameter D_PI_BURST_MODE = A_PI_BURST_MODE,
128 parameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
129 parameter D_PI_FINE_DELAY =
0,
130 parameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
132 //phaser_out parameters
133 parameter A_PO_CLKOUT_DIV = (DATA_CTL_N[
0] ==
0) ?
1.8.1
