AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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mig_7series_v1_9_ddr_mc_phy.v
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47 
48 //
49 //
50 // Owner: Gary Martin
51 // Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/mc_phy.v#5 $
52 // $Author: gary $
53 // $DateTime: 2010/05/11 18:05:17 $
54 // $Change: 490882 $
55 // Description:
56 // This verilog file is a parameterizable wrapper instantiating
57 // up to 5 memory banks of 4-lane phy primitives. There
58 // There are always 2 control banks leaving 18 lanes for data.
59 //
60 // History:
61 // Date Engineer Description
62 // 04/01/2010 G. Martin Initial Checkin.
63 //
64 ////////////////////////////////////////////////////////////
65 ************************************************************/
66 
67 
68 `timescale 1ps/1ps
69 
70 module mig_7series_v1_9_ddr_mc_phy
71  #(
72 // five fields, one per possible I/O bank, 4 bits in each field, 1 per lane data=1/ctl=0
73  parameter BYTE_LANES_B0 = 4'b1111,
74  parameter BYTE_LANES_B1 = 4'b0000,
75  parameter BYTE_LANES_B2 = 4'b0000,
76  parameter BYTE_LANES_B3 = 4'b0000,
77  parameter BYTE_LANES_B4 = 4'b0000,
78  parameter DATA_CTL_B0 = 4'hc,
79  parameter DATA_CTL_B1 = 4'hf,
80  parameter DATA_CTL_B2 = 4'hf,
81  parameter DATA_CTL_B3 = 4'hf,
82  parameter DATA_CTL_B4 = 4'hf,
83  parameter RCLK_SELECT_BANK = 0,
84  parameter RCLK_SELECT_LANE = "B",
85  parameter RCLK_SELECT_EDGE = 4'b1111,
86  parameter GENERATE_DDR_CK_MAP = "0B",
87  parameter BYTELANES_DDR_CK = 72'h00_0000_0000_0000_0002,
88  parameter USE_PRE_POST_FIFO = "TRUE",
89  parameter SYNTHESIS = "FALSE",
90  parameter PO_CTL_COARSE_BYPASS = "FALSE",
91  parameter PI_SEL_CLK_OFFSET = 6,
92 
93  parameter PHYCTL_CMD_FIFO = "FALSE",
94  parameter PHY_CLK_RATIO = 4, // phy to controller divide ratio
95 
96 // common to all i/o banks
97  parameter PHY_FOUR_WINDOW_CLOCKS = 63,
98  parameter PHY_EVENTS_DELAY = 18,
99  parameter PHY_COUNT_EN = "TRUE",
100  parameter PHY_SYNC_MODE = "TRUE",
101  parameter PHY_DISABLE_SEQ_MATCH = "FALSE",
102  parameter MASTER_PHY_CTL = 0,
103 // common to instance 0
104  parameter PHY_0_BITLANES = 48'hdffd_fffe_dfff,
105  parameter PHY_0_BITLANES_OUTONLY = 48'h0000_0000_0000,
106  parameter PHY_0_LANE_REMAP = 16'h3210,
107  parameter PHY_0_GENERATE_IDELAYCTRL = "FALSE",
108  parameter PHY_0_IODELAY_GRP = "IODELAY_MIG",
109  parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
110  parameter NUM_DDR_CK = 1,
111  parameter PHY_0_DATA_CTL = DATA_CTL_B0,
112  parameter PHY_0_CMD_OFFSET = 0,
113  parameter PHY_0_RD_CMD_OFFSET_0 = 0,
114  parameter PHY_0_RD_CMD_OFFSET_1 = 0,
115  parameter PHY_0_RD_CMD_OFFSET_2 = 0,
116  parameter PHY_0_RD_CMD_OFFSET_3 = 0,
117  parameter PHY_0_RD_DURATION_0 = 0,
118  parameter PHY_0_RD_DURATION_1 = 0,
119  parameter PHY_0_RD_DURATION_2 = 0,
120  parameter PHY_0_RD_DURATION_3 = 0,
121  parameter PHY_0_WR_CMD_OFFSET_0 = 0,
122  parameter PHY_0_WR_CMD_OFFSET_1 = 0,
123  parameter PHY_0_WR_CMD_OFFSET_2 = 0,
124  parameter PHY_0_WR_CMD_OFFSET_3 = 0,
125  parameter PHY_0_WR_DURATION_0 = 0,
126  parameter PHY_0_WR_DURATION_1 = 0,
127  parameter PHY_0_WR_DURATION_2 = 0,
128  parameter PHY_0_WR_DURATION_3 = 0,
129  parameter PHY_0_AO_WRLVL_EN = 0,
130  parameter PHY_0_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
131  parameter PHY_0_OF_ALMOST_FULL_VALUE = 1,
132  parameter PHY_0_IF_ALMOST_EMPTY_VALUE = 1,
133 // per lane parameters
134  parameter PHY_0_A_PI_FREQ_REF_DIV = "NONE",
135  parameter PHY_0_A_PI_CLKOUT_DIV = 2,
136  parameter PHY_0_A_PO_CLKOUT_DIV = 2,
137  parameter PHY_0_A_BURST_MODE = "TRUE",
138  parameter PHY_0_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF",
139  parameter PHY_0_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
140  parameter PHY_0_A_PO_OCLK_DELAY = 25,
141  parameter PHY_0_B_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
142  parameter PHY_0_C_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
143  parameter PHY_0_D_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
144  parameter PHY_0_A_PO_OCLKDELAY_INV = "FALSE",
145  parameter PHY_0_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
146  parameter PHY_0_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
147  parameter PHY_0_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
148  parameter PHY_0_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
149  parameter PHY_0_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
150  parameter PHY_0_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
151  parameter PHY_0_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
152  parameter PHY_0_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
153  parameter PHY_0_A_OSERDES_DATA_RATE = "UNDECLARED",
154  parameter PHY_0_A_OSERDES_DATA_WIDTH = "UNDECLARED",
155  parameter PHY_0_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
156  parameter PHY_0_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
157  parameter PHY_0_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
158  parameter PHY_0_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
159  parameter PHY_0_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
160  parameter PHY_0_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
161  parameter PHY_0_A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
162  parameter PHY_0_A_IDELAYE2_IDELAY_VALUE = 00,
163  parameter PHY_0_B_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
164  parameter PHY_0_B_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
165  parameter PHY_0_C_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
166  parameter PHY_0_C_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
167  parameter PHY_0_D_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
168  parameter PHY_0_D_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
169 
170 // common to instance 1
171  parameter PHY_1_BITLANES = PHY_0_BITLANES,
172  parameter PHY_1_BITLANES_OUTONLY = 48'h0000_0000_0000,
173  parameter PHY_1_LANE_REMAP = 16'h3210,
174  parameter PHY_1_GENERATE_IDELAYCTRL = "FALSE",
175  parameter PHY_1_IODELAY_GRP = PHY_0_IODELAY_GRP,
176  parameter PHY_1_DATA_CTL = DATA_CTL_B1,
177  parameter PHY_1_CMD_OFFSET = PHY_0_CMD_OFFSET,
178  parameter PHY_1_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
179  parameter PHY_1_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
180  parameter PHY_1_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
181  parameter PHY_1_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
182  parameter PHY_1_RD_DURATION_0 = PHY_0_RD_DURATION_0,
183  parameter PHY_1_RD_DURATION_1 = PHY_0_RD_DURATION_1,
184  parameter PHY_1_RD_DURATION_2 = PHY_0_RD_DURATION_2,
185  parameter PHY_1_RD_DURATION_3 = PHY_0_RD_DURATION_3,
186  parameter PHY_1_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
187  parameter PHY_1_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
188  parameter PHY_1_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
189  parameter PHY_1_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
190  parameter PHY_1_WR_DURATION_0 = PHY_0_WR_DURATION_0,
191  parameter PHY_1_WR_DURATION_1 = PHY_0_WR_DURATION_1,
192  parameter PHY_1_WR_DURATION_2 = PHY_0_WR_DURATION_2,
193  parameter PHY_1_WR_DURATION_3 = PHY_0_WR_DURATION_3,
194  parameter PHY_1_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
195  parameter PHY_1_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
196  parameter PHY_1_OF_ALMOST_FULL_VALUE = 1,
197  parameter PHY_1_IF_ALMOST_EMPTY_VALUE = 1,
198 // per lane parameters
199  parameter PHY_1_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
200  parameter PHY_1_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV,
201  parameter PHY_1_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
202  parameter PHY_1_A_BURST_MODE = PHY_0_A_BURST_MODE,
203  parameter PHY_1_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
204  parameter PHY_1_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC ,
205  parameter PHY_1_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
206  parameter PHY_1_B_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
207  parameter PHY_1_C_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
208  parameter PHY_1_D_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
209  parameter PHY_1_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
210  parameter PHY_1_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
211  parameter PHY_1_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
212  parameter PHY_1_B_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
213  parameter PHY_1_B_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
214  parameter PHY_1_C_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
215  parameter PHY_1_C_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
216  parameter PHY_1_D_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
217  parameter PHY_1_D_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
218  parameter PHY_1_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
219  parameter PHY_1_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
220  parameter PHY_1_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
221  parameter PHY_1_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
222  parameter PHY_1_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
223  parameter PHY_1_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
224  parameter PHY_1_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
225  parameter PHY_1_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
226  parameter PHY_1_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
227  parameter PHY_1_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
228  parameter PHY_1_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
229  parameter PHY_1_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
230  parameter PHY_1_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
231  parameter PHY_1_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
232  parameter PHY_1_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
233  parameter PHY_1_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
234 
235 // common to instance 2
236  parameter PHY_2_BITLANES = PHY_0_BITLANES,
237  parameter PHY_2_BITLANES_OUTONLY = 48'h0000_0000_0000,
238  parameter PHY_2_LANE_REMAP = 16'h3210,
239  parameter PHY_2_GENERATE_IDELAYCTRL = "FALSE",
240  parameter PHY_2_IODELAY_GRP = PHY_0_IODELAY_GRP,
241  parameter PHY_2_DATA_CTL = DATA_CTL_B2,
242  parameter PHY_2_CMD_OFFSET = PHY_0_CMD_OFFSET,
243  parameter PHY_2_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
244  parameter PHY_2_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
245  parameter PHY_2_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
246  parameter PHY_2_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
247  parameter PHY_2_RD_DURATION_0 = PHY_0_RD_DURATION_0,
248  parameter PHY_2_RD_DURATION_1 = PHY_0_RD_DURATION_1,
249  parameter PHY_2_RD_DURATION_2 = PHY_0_RD_DURATION_2,
250  parameter PHY_2_RD_DURATION_3 = PHY_0_RD_DURATION_3,
251  parameter PHY_2_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
252  parameter PHY_2_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
253  parameter PHY_2_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
254  parameter PHY_2_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
255  parameter PHY_2_WR_DURATION_0 = PHY_0_WR_DURATION_0,
256  parameter PHY_2_WR_DURATION_1 = PHY_0_WR_DURATION_1,
257  parameter PHY_2_WR_DURATION_2 = PHY_0_WR_DURATION_2,
258  parameter PHY_2_WR_DURATION_3 = PHY_0_WR_DURATION_3,
259  parameter PHY_2_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
260  parameter PHY_2_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
261  parameter PHY_2_OF_ALMOST_FULL_VALUE = 1,
262  parameter PHY_2_IF_ALMOST_EMPTY_VALUE = 1,
263 // per lane parameters
264  parameter PHY_2_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
265  parameter PHY_2_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV ,
266  parameter PHY_2_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
267  parameter PHY_2_A_BURST_MODE = PHY_0_A_BURST_MODE ,
268  parameter PHY_2_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
269  parameter PHY_2_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC,
270  parameter PHY_2_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
271  parameter PHY_2_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
272  parameter PHY_2_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
273  parameter PHY_2_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
274  parameter PHY_2_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
275  parameter PHY_2_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
276  parameter PHY_2_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
277  parameter PHY_2_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
278  parameter PHY_2_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
279  parameter PHY_2_B_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
280  parameter PHY_2_C_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
281  parameter PHY_2_D_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
282  parameter PHY_2_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
283  parameter PHY_2_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
284  parameter PHY_2_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
285  parameter PHY_2_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
286  parameter PHY_2_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
287  parameter PHY_2_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
288  parameter PHY_2_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
289  parameter PHY_2_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
290  parameter PHY_2_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
291  parameter PHY_2_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
292  parameter PHY_2_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
293  parameter PHY_2_B_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
294  parameter PHY_2_B_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
295  parameter PHY_2_C_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
296  parameter PHY_2_C_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
297  parameter PHY_2_D_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
298  parameter PHY_2_D_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
299  parameter PHY_0_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) || (BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : "TRUE",
300  parameter PHY_1_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) && ((BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0))) ? "FALSE" : ((PHY_0_IS_LAST_BANK) ? "FALSE" : "TRUE"),
301  parameter PHY_2_IS_LAST_BANK = (BYTE_LANES_B2 != 0) && ((BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : ((PHY_0_IS_LAST_BANK || PHY_1_IS_LAST_BANK) ? "FALSE" : "TRUE"),
302  parameter TCK = 2500,
303 
304 // local computational use, do not pass down
305  parameter N_LANES = (0+BYTE_LANES_B0[0]) + (0+BYTE_LANES_B0[1]) + (0+BYTE_LANES_B0[2]) + (0+BYTE_LANES_B0[3])
306  + (0+BYTE_LANES_B1[0]) + (0+BYTE_LANES_B1[1]) + (0+BYTE_LANES_B1[2]) + (0+BYTE_LANES_B1[3]) + (0+BYTE_LANES_B2[0]) + (0+BYTE_LANES_B2[1]) + (0+BYTE_LANES_B2[2]) + (0+BYTE_LANES_B2[3])
307  , // must not delete comma for syntax
308  parameter HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))),
309  parameter HIGHEST_LANE_B0 = ((PHY_0_IS_LAST_BANK == "FALSE") ? 4 : BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0) ,
310  parameter HIGHEST_LANE_B1 = (HIGHEST_BANK > 2) ? 4 : ( BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0) ,
311  parameter HIGHEST_LANE_B2 = (HIGHEST_BANK > 3) ? 4 : ( BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0) ,
312  parameter HIGHEST_LANE_B3 = 0,
313  parameter HIGHEST_LANE_B4 = 0,
314 
315  parameter HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))),
316  parameter LP_DDR_CK_WIDTH = 2,
317  parameter GENERATE_SIGNAL_SPLIT = "FALSE"
318  ,parameter CKE_ODT_AUX = "FALSE"
319  )
320  (
321  input rst,
322  input ddr_rst_in_n ,
323  input phy_clk,
324  input freq_refclk,
325  input mem_refclk,
326  input mem_refclk_div4,
327  input pll_lock,
328  input sync_pulse,
329  input auxout_clk,
330  input idelayctrl_refclk,
331  input [HIGHEST_LANE*80-1:0] phy_dout,
332  input phy_cmd_wr_en,
333  input phy_data_wr_en,
334  input phy_rd_en,
335  input [31:0] phy_ctl_wd,
336  input [3:0] aux_in_1,
337  input [3:0] aux_in_2,
338  input [5:0] data_offset_1,
339  input [5:0] data_offset_2,
340  input phy_ctl_wr,
341  input if_rst,
342  input if_empty_def,
343  input cke_in,
344  input idelay_ce,
345  input idelay_ld,
346  input idelay_inc,
347  input phyGo,
348  input input_sink,
349  output if_a_empty,
350 (* keep = "true", max_fanout = 3 *) output if_empty /* synthesis syn_maxfan = 3 **/,
351  output if_empty_or,
352  output if_empty_and,
353  output of_ctl_a_full,
354  output of_data_a_full,
355  output of_ctl_full,
356  output of_data_full,
357  output pre_data_a_full,
358  output [HIGHEST_LANE*80-1:0] phy_din,
359  output phy_ctl_a_full,
360 (* keep = "true", max_fanout = 3 *) output wire [3:0] phy_ctl_full,
361  output [HIGHEST_LANE*12-1:0] mem_dq_out,
362  output [HIGHEST_LANE*12-1:0] mem_dq_ts,
363  input [HIGHEST_LANE*10-1:0] mem_dq_in,
364  output [HIGHEST_LANE-1:0] mem_dqs_out,
365  output [HIGHEST_LANE-1:0] mem_dqs_ts,
366  input [HIGHEST_LANE-1:0] mem_dqs_in,
367 
368 (* IOB = "FORCE" *) output reg [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out, // to memory, odt , 4 per phy controller
369  output phy_ctl_ready, // to fabric
370  output reg rst_out, // to memory
371  output [(NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
372 // output rclk,
373  output mcGo,
374  output ref_dll_lock,
375 // calibration signals
376  input phy_write_calib,
377  input phy_read_calib,
378  input [5:0] calib_sel,
379  input [HIGHEST_BANK-1:0]calib_zero_inputs, // bit calib_sel[2], one per bank
380  input [HIGHEST_BANK-1:0]calib_zero_ctrl, // one bit per bank, zero's only control lane calibration inputs
381  input [HIGHEST_LANE-1:0] calib_zero_lanes, // one bit per lane
382  input calib_in_common,
383  input [2:0] po_fine_enable,
384  input [2:0] po_coarse_enable,
385  input [2:0] po_fine_inc,
386  input [2:0] po_coarse_inc,
387  input po_counter_load_en,
388  input [2:0] po_sel_fine_oclk_delay,
389  input [8:0] po_counter_load_val,
390  input po_counter_read_en,
391  output reg po_coarse_overflow,
392  output reg po_fine_overflow,
393  output reg [8:0] po_counter_read_val,
394 
395 
396  input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
397  input pi_fine_enable,
398  input pi_fine_inc,
399  input pi_counter_load_en,
400  input pi_counter_read_en,
401  input [5:0] pi_counter_load_val,
402  output reg pi_fine_overflow,
403  output reg [5:0] pi_counter_read_val,
404 
405  output reg pi_phase_locked,
406  output pi_phase_locked_all,
407  output reg pi_dqs_found,
408  output pi_dqs_found_all,
409  output pi_dqs_found_any,
410  output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,
411  output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
412  output reg pi_dqs_out_of_range
413  );
414 
415 
416 wire [7:0] calib_zero_inputs_int ;
417 wire [HIGHEST_BANK*4-1:0] calib_zero_lanes_int ;
418 
419 //Added the temporary variable for concadination operation
420 wire [2:0] calib_sel_byte0 ;
421 wire [2:0] calib_sel_byte1 ;
422 wire [2:0] calib_sel_byte2 ;
423 
424 wire [4:0] po_coarse_overflow_w;
425 wire [4:0] po_fine_overflow_w;
426 wire [8:0] po_counter_read_val_w[4:0];
427 wire [4:0] pi_fine_overflow_w;
428 wire [5:0] pi_counter_read_val_w[4:0];
429 wire [4:0] pi_dqs_found_w;
430 wire [4:0] pi_dqs_found_all_w;
431 wire [4:0] pi_dqs_found_any_w;
432 wire [4:0] pi_dqs_out_of_range_w;
433 wire [4:0] pi_phase_locked_w;
434 wire [4:0] pi_phase_locked_all_w;
435 wire [4:0] rclk_w;
436 wire [HIGHEST_BANK-1:0] phy_ctl_ready_w;
437 wire [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk_w [HIGHEST_BANK-1:0];
438 wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out_;
439 
440 
441 wire [3:0] if_q0;
442 wire [3:0] if_q1;
443 wire [3:0] if_q2;
444 wire [3:0] if_q3;
445 wire [3:0] if_q4;
446 wire [7:0] if_q5;
447 wire [7:0] if_q6;
448 wire [3:0] if_q7;
449 wire [3:0] if_q8;
450 wire [3:0] if_q9;
451 
452 wire [31:0] _phy_ctl_wd;
453 wire [3:0] aux_in_[4:1];
454 wire [3:0] rst_out_w;
455 
456 wire freq_refclk_split;
457 wire mem_refclk_split;
458 wire mem_refclk_div4_split;
459 wire sync_pulse_split;
460 wire phy_clk_split0;
461 wire phy_ctl_clk_split0;
462 wire [31:0] phy_ctl_wd_split0;
463 wire phy_ctl_wr_split0;
464 wire phy_ctl_clk_split1;
465 wire phy_clk_split1;
466 wire [31:0] phy_ctl_wd_split1;
467 wire phy_ctl_wr_split1;
468 wire [5:0] phy_data_offset_1_split1;
469 wire phy_ctl_clk_split2;
470 wire phy_clk_split2;
471 wire [31:0] phy_ctl_wd_split2;
472 wire phy_ctl_wr_split2;
473 wire [5:0] phy_data_offset_2_split2;
474 wire [HIGHEST_LANE*80-1:0] phy_dout_split0;
475 wire phy_cmd_wr_en_split0;
476 wire phy_data_wr_en_split0;
477 wire phy_rd_en_split0;
478 wire [HIGHEST_LANE*80-1:0] phy_dout_split1;
479 wire phy_cmd_wr_en_split1;
480 wire phy_data_wr_en_split1;
481 wire phy_rd_en_split1;
482 wire [HIGHEST_LANE*80-1:0] phy_dout_split2;
483 wire phy_cmd_wr_en_split2;
484 wire phy_data_wr_en_split2;
485 wire phy_rd_en_split2;
486 
487 wire phy_ctl_mstr_empty;
488 wire [HIGHEST_BANK-1:0] phy_ctl_empty;
489 
490 wire _phy_ctl_a_full_f;
491 wire _phy_ctl_a_empty_f;
492 wire _phy_ctl_full_f;
493 wire _phy_ctl_empty_f;
494 wire [HIGHEST_BANK-1:0] _phy_ctl_a_full_p;
495 wire [HIGHEST_BANK-1:0] _phy_ctl_full_p;
496 wire [HIGHEST_BANK-1:0] of_ctl_a_full_v;
497 wire [HIGHEST_BANK-1:0] of_ctl_full_v;
498 wire [HIGHEST_BANK-1:0] of_data_a_full_v;
499 wire [HIGHEST_BANK-1:0] of_data_full_v;
500 wire [HIGHEST_BANK-1:0] pre_data_a_full_v;
501 wire [HIGHEST_BANK-1:0] if_empty_v;
502 wire [HIGHEST_BANK-1:0] byte_rd_en_v;
503 wire [HIGHEST_BANK*2-1:0] byte_rd_en_oth_banks;
504 wire [HIGHEST_BANK-1:0] if_empty_or_v;
505 wire [HIGHEST_BANK-1:0] if_empty_and_v;
506 wire [HIGHEST_BANK-1:0] if_a_empty_v;
507 
508 localparam IF_ARRAY_MODE = "ARRAY_MODE_4_X_4";
509 localparam IF_SYNCHRONOUS_MODE = "FALSE";
510 localparam IF_SLOW_WR_CLK = "FALSE";
511 localparam IF_SLOW_RD_CLK = "FALSE";
512 
513 localparam PHY_MULTI_REGION = (HIGHEST_BANK > 1) ? "TRUE" : "FALSE";
514 localparam RCLK_NEG_EDGE = 3'b000;
515 localparam RCLK_POS_EDGE = 3'b111;
516 
517 localparam LP_PHY_0_BYTELANES_DDR_CK = BYTELANES_DDR_CK & 24'hFF_FFFF;
518 localparam LP_PHY_1_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 24) & 24'hFF_FFFF;
519 localparam LP_PHY_2_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 48) & 24'hFF_FFFF;
520 
521 // hi, lo positions for data offset field, MIG doesn't allow defines
522 localparam PC_DATA_OFFSET_RANGE_HI = 22;
523 localparam PC_DATA_OFFSET_RANGE_LO = 17;
524 
525 /* Phaser_In Output source coding table
526  "PHASE_REF" : 4'b0000;
527  "DELAYED_MEM_REF" : 4'b0101;
528  "DELAYED_PHASE_REF" : 4'b0011;
529  "DELAYED_REF" : 4'b0001;
530  "FREQ_REF" : 4'b1000;
531  "MEM_REF" : 4'b0010;
532 */
533 
534 localparam RCLK_PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF";
535 
536 
537 localparam DDR_TCK = TCK;
538 
539 localparam real FREQ_REF_PERIOD = DDR_TCK / (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
540 localparam real L_FREQ_REF_PERIOD_NS = FREQ_REF_PERIOD /1000.0;
541 localparam PO_S3_TAPS = 64 ; // Number of taps per clock cycle in OCLK_DELAYED delay line
542 localparam PI_S2_TAPS = 128 ; // Number of taps per clock cycle in stage 2 delay line
543 localparam PO_S2_TAPS = 128 ; // Number of taps per clock cycle in sta
544 
545 /*
546 Intrinsic delay of Phaser In Stage 1
547 @3300ps - 1.939ns - 58.8%
548 @2500ps - 1.657ns - 66.3%
549 @1875ps - 1.263ns - 67.4%
550 @1500ps - 1.021ns - 68.1%
551 @1250ps - 0.868ns - 69.4%
552 @1072ps - 0.752ns - 70.1%
553 @938ps - 0.667ns - 71.1%
554 */
555 
556 // If we use the Delayed Mem_Ref_Clk in the RCLK Phaser_In, then the Stage 1 intrinsic delay is 0.0
557 // Fraction of a full DDR_TCK period
558 localparam real PI_STG1_INTRINSIC_DELAY = (RCLK_PI_OUTPUT_CLK_SRC == "DELAYED_MEM_REF") ? 0.0 :
559  ((DDR_TCK < 1005) ? 0.667 :
560  (DDR_TCK < 1160) ? 0.752 :
561  (DDR_TCK < 1375) ? 0.868 :
562  (DDR_TCK < 1685) ? 1.021 :
563  (DDR_TCK < 2185) ? 1.263 :
564  (DDR_TCK < 2900) ? 1.657 :
565  (DDR_TCK < 3100) ? 1.771 : 1.939)*1000;
566 /*
567 Intrinsic delay of Phaser In Stage 2
568 @3300ps - 0.912ns - 27.6% - single tap - 13ps
569 @3000ps - 0.848ns - 28.3% - single tap - 11ps
570 @2500ps - 1.264ns - 50.6% - single tap - 19ps
571 @1875ps - 1.000ns - 53.3% - single tap - 15ps
572 @1500ps - 0.848ns - 56.5% - single tap - 11ps
573 @1250ps - 0.736ns - 58.9% - single tap - 9ps
574 @1072ps - 0.664ns - 61.9% - single tap - 8ps
575 @938ps - 0.608ns - 64.8% - single tap - 7ps
576 */
577 // Intrinsic delay = (.4218 + .0002freq(MHz))period(ps)
578 localparam real PI_STG2_INTRINSIC_DELAY = (0.4218*FREQ_REF_PERIOD + 200) + 16.75; // 12ps fudge factor
579 /*
580 Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 1
581 @3300ps - 1.294ns - 39.2%
582 @2500ps - 1.294ns - 51.8%
583 @1875ps - 1.030ns - 54.9%
584 @1500ps - 0.878ns - 58.5%
585 @1250ps - 0.766ns - 61.3%
586 @1072ps - 0.694ns - 64.7%
587 @938ps - 0.638ns - 68.0%
588 
589 Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 0
590 @3300ps - 2.084ns - 63.2% - single tap - 20ps
591 @2500ps - 2.084ns - 81.9% - single tap - 19ps
592 @1875ps - 1.676ns - 89.4% - single tap - 15ps
593 @1500ps - 1.444ns - 96.3% - single tap - 11ps
594 @1250ps - 1.276ns - 102.1% - single tap - 9ps
595 @1072ps - 1.164ns - 108.6% - single tap - 8ps
596 @938ps - 1.076ns - 114.7% - single tap - 7ps
597 */
598 // Fraction of a full DDR_TCK period
599 localparam real PO_STG1_INTRINSIC_DELAY = 0;
600 localparam real PO_STG2_FINE_INTRINSIC_DELAY = 0.4218*FREQ_REF_PERIOD + 200 + 42; // 42ps fudge factor
601 localparam real PO_STG2_COARSE_INTRINSIC_DELAY = 0.2256*FREQ_REF_PERIOD + 200 + 29; // 29ps fudge factor
602 localparam real PO_STG2_INTRINSIC_DELAY = PO_STG2_FINE_INTRINSIC_DELAY +
603  (PO_CTL_COARSE_BYPASS == "TRUE" ? 30 : PO_STG2_COARSE_INTRINSIC_DELAY);
604 
605 // When the PO_STG2_INTRINSIC_DELAY is approximately equal to tCK, then the Phaser Out's circular buffer can
606 // go metastable. The circular buffer must be prevented from getting into a metastable state. To accomplish this,
607 // a default programmed value must be programmed into the stage 2 delay. This delay is only needed at reset, adjustments
608 // to the stage 2 delay can be made after reset is removed.
609 
610 localparam real PO_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PO_S2_TAPS ; // average delay of taps in stage 2 fine delay line
611 localparam real PO_CIRC_BUF_META_ZONE = 200.0;
612 localparam PO_CIRC_BUF_EARLY = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? 1'b1 : 1'b0;
613 localparam real PO_CIRC_BUF_OFFSET = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? DDR_TCK - PO_STG2_INTRINSIC_DELAY : PO_STG2_INTRINSIC_DELAY - DDR_TCK;
614 // If the stage 2 intrinsic delay is less than the clock period, then see if it is less than the threshold
615 // If it is not more than the threshold than we must push the delay after the clock period plus a guardband.
616 
617 //A change in PO_CIRC_BUF_DELAY value will affect the localparam TAP_DEC value(=PO_CIRC_BUF_DELAY - 31) in ddr_phy_ck_addr_cmd_delay.v. Update TAP_DEC value when PO_CIRC_BUF_DELAY is updated.
618 localparam integer PO_CIRC_BUF_DELAY = 60;
619 
620 //localparam integer PO_CIRC_BUF_DELAY = PO_CIRC_BUF_EARLY ? (PO_CIRC_BUF_OFFSET > PO_CIRC_BUF_META_ZONE) ? 0 :
621 // (PO_CIRC_BUF_META_ZONE + PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE :
622 // (PO_CIRC_BUF_META_ZONE - PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE;
623 
624 localparam real PI_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PI_S2_TAPS ; // average delay of taps in stage 2 fine delay line
625 localparam real PI_MAX_STG2_DELAY = (PI_S2_TAPS/2 - 1) * PI_S2_TAPS_SIZE;
626 localparam real PI_INTRINSIC_DELAY = PI_STG1_INTRINSIC_DELAY + PI_STG2_INTRINSIC_DELAY;
627 localparam real PO_INTRINSIC_DELAY = PO_STG1_INTRINSIC_DELAY + PO_STG2_INTRINSIC_DELAY;
628 localparam real PO_DELAY = PO_INTRINSIC_DELAY + (PO_CIRC_BUF_DELAY*PO_S2_TAPS_SIZE);
629 localparam RCLK_BUFIO_DELAY = 1200; // estimate of clock insertion delay of rclk through BUFIO to ioi
630 // The PI_OFFSET is the difference between the Phaser Out delay path and the intrinsic delay path
631 // of the Phaser_In that drives the rclk. The objective is to align either the rising edges of the
632 // oserdes_oclk and the rclk or to align the rising to falling edges depending on which adjustment
633 // is within the range of the stage 2 delay line in the Phaser_In.
634 localparam integer RCLK_DELAY_INT= (PI_INTRINSIC_DELAY + RCLK_BUFIO_DELAY);
635 localparam integer PO_DELAY_INT = PO_DELAY;
636 localparam real PI_OFFSET = (PO_DELAY_INT % DDR_TCK) - (RCLK_DELAY_INT % DDR_TCK);
637 
638 // if pi_offset >= 0 align to oclk posedge by delaying pi path to where oclk is
639 // if pi_offset < 0 align to oclk negedge by delaying pi path the additional distance to next oclk edge.
640 // note that in this case PI_OFFSET is negative so invert before subtracting.
641 localparam real PI_STG2_DELAY_CAND = PI_OFFSET >= 0
642  ? PI_OFFSET
643  : ((-PI_OFFSET) < DDR_TCK/2) ?
644  (DDR_TCK/2 - (- PI_OFFSET)) :
645  (DDR_TCK - (- PI_OFFSET)) ;
646 
647 localparam real PI_STG2_DELAY =
648  (PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY ?
649  PI_MAX_STG2_DELAY : PI_STG2_DELAY_CAND);
650 localparam integer DEFAULT_RCLK_DELAY = PI_STG2_DELAY / PI_S2_TAPS_SIZE;
651 
652 localparam LP_RCLK_SELECT_EDGE = (RCLK_SELECT_EDGE != 4'b1111 ) ? RCLK_SELECT_EDGE : (PI_OFFSET >= 0 ? RCLK_POS_EDGE : (PI_OFFSET <= TCK/2 ? RCLK_NEG_EDGE : RCLK_POS_EDGE));
653 
654 localparam integer L_PHY_0_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
655 localparam integer L_PHY_1_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
656 localparam integer L_PHY_2_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
657 
658 localparam L_PHY_0_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[0]) ? DEFAULT_RCLK_DELAY : 33 ;
659 localparam L_PHY_0_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[1]) ? DEFAULT_RCLK_DELAY : 33 ;
660 localparam L_PHY_0_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[2]) ? DEFAULT_RCLK_DELAY : 33 ;
661 localparam L_PHY_0_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[3]) ? DEFAULT_RCLK_DELAY : 33 ;
662 
663 localparam L_PHY_1_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[0]) ? DEFAULT_RCLK_DELAY : 33 ;
664 localparam L_PHY_1_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[1]) ? DEFAULT_RCLK_DELAY : 33 ;
665 localparam L_PHY_1_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[2]) ? DEFAULT_RCLK_DELAY : 33 ;
666 localparam L_PHY_1_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[3]) ? DEFAULT_RCLK_DELAY : 33 ;
667 
668 localparam L_PHY_2_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[0]) ? DEFAULT_RCLK_DELAY : 33 ;
669 localparam L_PHY_2_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[1]) ? DEFAULT_RCLK_DELAY : 33 ;
670 localparam L_PHY_2_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[2]) ? DEFAULT_RCLK_DELAY : 33 ;
671 localparam L_PHY_2_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[3]) ? DEFAULT_RCLK_DELAY : 33 ;
672 
673 
674 localparam L_PHY_0_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
675 localparam L_PHY_0_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
676 localparam L_PHY_0_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
677 localparam L_PHY_0_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
678 
679 localparam L_PHY_1_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
680 localparam L_PHY_1_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
681 localparam L_PHY_1_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
682 localparam L_PHY_1_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
683 
684 localparam L_PHY_2_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
685 localparam L_PHY_2_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
686 localparam L_PHY_2_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
687 localparam L_PHY_2_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
688 
689 wire _phy_clk;
690 
691 wire [2:0] mcGo_w;
692 wire [HIGHEST_BANK-1:0] ref_dll_lock_w;
693 reg [15:0] mcGo_r;
694 
695 
696 assign ref_dll_lock = & ref_dll_lock_w;
697 
698 initial begin
699  if ( SYNTHESIS == "FALSE" ) begin
700  $display("%m : BYTE_LANES_B0 = %x BYTE_LANES_B1 = %x DATA_CTL_B0 = %x DATA_CTL_B1 = %x", BYTE_LANES_B0, BYTE_LANES_B1, DATA_CTL_B0, DATA_CTL_B1);
701  $display("%m : HIGHEST_LANE = %d HIGHEST_LANE_B0 = %d HIGHEST_LANE_B1 = %d", HIGHEST_LANE, HIGHEST_LANE_B0, HIGHEST_LANE_B1);
702  $display("%m : HIGHEST_BANK = %d", HIGHEST_BANK);
703 
704  $display("%m : FREQ_REF_PERIOD = %0.2f ", FREQ_REF_PERIOD);
705  $display("%m : DDR_TCK = %0d ", DDR_TCK);
706  $display("%m : PO_S2_TAPS_SIZE = %0.2f ", PO_S2_TAPS_SIZE);
707  $display("%m : PO_CIRC_BUF_EARLY = %0d ", PO_CIRC_BUF_EARLY);
708  $display("%m : PO_CIRC_BUF_OFFSET = %0.2f ", PO_CIRC_BUF_OFFSET);
709  $display("%m : PO_CIRC_BUF_META_ZONE = %0.2f ", PO_CIRC_BUF_META_ZONE);
710  $display("%m : PO_STG2_FINE_INTR_DLY = %0.2f ", PO_STG2_FINE_INTRINSIC_DELAY);
711  $display("%m : PO_STG2_COARSE_INTR_DLY = %0.2f ", PO_STG2_COARSE_INTRINSIC_DELAY);
712  $display("%m : PO_STG2_INTRINSIC_DELAY = %0.2f ", PO_STG2_INTRINSIC_DELAY);
713  $display("%m : PO_CIRC_BUF_DELAY = %0d ", PO_CIRC_BUF_DELAY);
714  $display("%m : PO_INTRINSIC_DELAY = %0.2f ", PO_INTRINSIC_DELAY);
715  $display("%m : PO_DELAY = %0.2f ", PO_DELAY);
716  $display("%m : PO_OCLK_DELAY = %0d ", PHY_0_A_PO_OCLK_DELAY);
717  $display("%m : L_PHY_0_PO_FINE_DELAY = %0d ", L_PHY_0_PO_FINE_DELAY);
718 
719  $display("%m : PI_STG1_INTRINSIC_DELAY = %0.2f ", PI_STG1_INTRINSIC_DELAY);
720  $display("%m : PI_STG2_INTRINSIC_DELAY = %0.2f ", PI_STG2_INTRINSIC_DELAY);
721  $display("%m : PI_INTRINSIC_DELAY = %0.2f ", PI_INTRINSIC_DELAY);
722  $display("%m : PI_MAX_STG2_DELAY = %0.2f ", PI_MAX_STG2_DELAY);
723  $display("%m : PI_OFFSET = %0.2f ", PI_OFFSET);
724  if ( PI_OFFSET < 0) $display("%m : a negative PI_OFFSET means that rclk path is longer than oclk path so rclk will be delayed to next oclk edge and the negedge of rclk may be used.");
725  $display("%m : PI_STG2_DELAY = %0.2f ", PI_STG2_DELAY);
726  $display("%m :PI_STG2_DELAY_CAND = %0.2f ",PI_STG2_DELAY_CAND);
727  $display("%m : DEFAULT_RCLK_DELAY = %0d ", DEFAULT_RCLK_DELAY);
728  $display("%m : RCLK_SELECT_EDGE = %0b ", LP_RCLK_SELECT_EDGE);
729  end // SYNTHESIS
730  if ( PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY) $display("WARNING: %m: The required delay though the phaser_in to internally match the aux_out clock to ddr clock exceeds the maximum allowable delay. The clock edge will occur at the output registers of aux_out %0.2f ps before the ddr clock edge. If aux_out is used for memory inputs, this may violate setup or hold time.", PI_STG2_DELAY_CAND - PI_MAX_STG2_DELAY);
731 end
732 
733  assign sync_pulse_split = sync_pulse;
734  assign mem_refclk_split = mem_refclk;
735  assign freq_refclk_split = freq_refclk;
736  assign mem_refclk_div4_split = mem_refclk_div4;
737  assign phy_ctl_clk_split0 = _phy_clk;
738  assign phy_ctl_wd_split0 = phy_ctl_wd;
739  assign phy_ctl_wr_split0 = phy_ctl_wr;
740  assign phy_clk_split0 = phy_clk;
741  assign phy_cmd_wr_en_split0 = phy_cmd_wr_en;
742  assign phy_data_wr_en_split0 = phy_data_wr_en;
743  assign phy_rd_en_split0 = phy_rd_en;
744  assign phy_dout_split0 = phy_dout;
745  assign phy_ctl_clk_split1 = phy_clk;
746  assign phy_ctl_wd_split1 = phy_ctl_wd;
747  assign phy_data_offset_1_split1 = data_offset_1;
748  assign phy_ctl_wr_split1 = phy_ctl_wr;
749  assign phy_clk_split1 = phy_clk;
750  assign phy_cmd_wr_en_split1 = phy_cmd_wr_en;
751  assign phy_data_wr_en_split1 = phy_data_wr_en;
752  assign phy_rd_en_split1 = phy_rd_en;
753  assign phy_dout_split1 = phy_dout;
754  assign phy_ctl_clk_split2 = phy_clk;
755  assign phy_ctl_wd_split2 = phy_ctl_wd;
756  assign phy_data_offset_2_split2 = data_offset_2;
757  assign phy_ctl_wr_split2 = phy_ctl_wr;
758  assign phy_clk_split2 = phy_clk;
759  assign phy_cmd_wr_en_split2 = phy_cmd_wr_en;
760  assign phy_data_wr_en_split2 = phy_data_wr_en;
761  assign phy_rd_en_split2 = phy_rd_en;
762  assign phy_dout_split2 = phy_dout;
763 
764 // these wires are needed to coerce correct synthesis
765 // the synthesizer did not always see the widths of the
766 // parameters as 4 bits.
767 
768 wire [3:0] blb0 = BYTE_LANES_B0;
769 wire [3:0] blb1 = BYTE_LANES_B1;
770 wire [3:0] blb2 = BYTE_LANES_B2;
771 
772 wire [3:0] dcb0 = DATA_CTL_B0;
773 wire [3:0] dcb1 = DATA_CTL_B1;
774 wire [3:0] dcb2 = DATA_CTL_B2;
775 
776 assign pi_dqs_found_all = & (pi_dqs_found_lanes | ~ {blb2, blb1, blb0} | ~ {dcb2, dcb1, dcb0});
777 assign pi_dqs_found_any = | (pi_dqs_found_lanes & {blb2, blb1, blb0} & {dcb2, dcb1, dcb0});
778 assign pi_phase_locked_all = & pi_phase_locked_all_w[HIGHEST_BANK-1:0];
779 assign calib_zero_inputs_int = {3'bxxx, calib_zero_inputs};
780 //Added to remove concadination in the instantiation
781 assign calib_sel_byte0 = {calib_zero_inputs_int[0], calib_sel[1:0]} ;
782 assign calib_sel_byte1 = {calib_zero_inputs_int[1], calib_sel[1:0]} ;
783 assign calib_sel_byte2 = {calib_zero_inputs_int[2], calib_sel[1:0]} ;
784 
785 assign calib_zero_lanes_int = calib_zero_lanes;
786 
787 assign phy_ctl_ready = &phy_ctl_ready_w[HIGHEST_BANK-1:0];
788 
789 assign phy_ctl_mstr_empty = phy_ctl_empty[MASTER_PHY_CTL];
790 
791 assign of_ctl_a_full = |of_ctl_a_full_v;
792 assign of_ctl_full = |of_ctl_full_v;
793 assign of_data_a_full = |of_data_a_full_v;
794 assign of_data_full = |of_data_full_v;
795 assign pre_data_a_full= |pre_data_a_full_v;
796 // if if_empty_def == 1, empty is asserted only if all are empty;
797 // this allows the user to detect a skewed fifo depth and self-clear
798 // if desired. It avoids a reset to clear the flags.
799 assign if_empty = !if_empty_def ? |if_empty_v : &if_empty_v;
800 assign if_empty_or = |if_empty_or_v;
801 assign if_empty_and = &if_empty_and_v;
802 assign if_a_empty = |if_a_empty_v;
803 
804 
805 generate
806 genvar i;
807 for (i = 0; i != NUM_DDR_CK; i = i + 1) begin : ddr_clk_gen
808  case ((GENERATE_DDR_CK_MAP >> (16*i)) & 16'hffff)
809  16'h3041: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
810  16'h3042: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
811  16'h3043: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
812  16'h3044: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
813  16'h3141: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
814  16'h3142: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
815  16'h3143: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
816  16'h3144: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
817  16'h3241: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
818  16'h3242: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
819  16'h3243: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
820  16'h3244: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
821  default : initial $display("ERROR: mc_phy ddr_clk_gen : invalid specification for parameter GENERATE_DDR_CK_MAP , clock index = %d, spec= %x (hex) ", i, (( GENERATE_DDR_CK_MAP >> (16 * i )) & 16'hffff ));
822  endcase
823 end
824 endgenerate
825 
826 //assign rclk = rclk_w[RCLK_SELECT_BANK];
827 
828 reg rst_auxout;
829 reg rst_auxout_r;
830 reg rst_auxout_rr;
831 
832 always @(posedge auxout_clk or posedge rst) begin
833  if ( rst) begin
834  rst_auxout_r <= #(1) 1'b1;
835  rst_auxout_rr <= #(1) 1'b1;
836  end
837  else begin
838  rst_auxout_r <= #(1) rst;
839  rst_auxout_rr <= #(1) rst_auxout_r;
840  end
841 end
842 if ( LP_RCLK_SELECT_EDGE[0]) begin
843  always @(posedge auxout_clk or posedge rst) begin
844  if ( rst) begin
845  rst_auxout <= #(1) 1'b1;
846  end
847  else begin
848  rst_auxout <= #(1) rst_auxout_rr;
849  end
850  end
851 end
852 else begin
853  always @(negedge auxout_clk or posedge rst) begin
854  if ( rst) begin
855  rst_auxout <= #(1) 1'b1;
856  end
857  else begin
858  rst_auxout <= #(1) rst_auxout_rr;
859  end
860  end
861 end
862 
863 localparam L_RESET_SELECT_BANK =
864  (BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK) ? 0 : RCLK_SELECT_BANK;
865 
866 always @(*) begin
867  rst_out = rst_out_w[L_RESET_SELECT_BANK] & ddr_rst_in_n;
868 end
869 
870 always @(posedge phy_clk or posedge rst) begin
871  if ( rst)
872  mcGo_r <= #(1) 0;
873  else
874  mcGo_r <= #(1) (mcGo_r << 1) | &mcGo_w;
875 end
876 
877 assign mcGo = mcGo_r[15];
878 
879 
880 generate
881 
882 
883 // this is an optional 1 clock delay to add latency to the phy_control programming path
884 
885 if (PHYCTL_CMD_FIFO == "TRUE") begin : cmd_fifo_soft
886  reg [31:0] phy_wd_reg = 0;
887  reg [3:0] aux_in1_reg = 0;
888  reg [3:0] aux_in2_reg = 0;
889  reg sfifo_ready = 0;
890  assign _phy_ctl_wd = phy_wd_reg;
891  assign aux_in_[1] = aux_in1_reg;
892  assign aux_in_[2] = aux_in2_reg;
893  assign phy_ctl_a_full = |_phy_ctl_a_full_p;
894  assign phy_ctl_full[0] = |_phy_ctl_full_p;
895  assign phy_ctl_full[1] = |_phy_ctl_full_p;
896  assign phy_ctl_full[2] = |_phy_ctl_full_p;
897  assign phy_ctl_full[3] = |_phy_ctl_full_p;
898  assign _phy_clk = phy_clk;
899 
900  always @(posedge phy_clk) begin
901  phy_wd_reg <= #1 phy_ctl_wd;
902  aux_in1_reg <= #1 aux_in_1;
903  aux_in2_reg <= #1 aux_in_2;
904  sfifo_ready <= #1 phy_ctl_wr;
905  end
906 
907 end
908 
909 else if (PHYCTL_CMD_FIFO == "FALSE") begin
910  assign _phy_ctl_wd = phy_ctl_wd;
911  assign aux_in_[1] = aux_in_1;
912  assign aux_in_[2] = aux_in_2;
913  assign phy_ctl_a_full = |_phy_ctl_a_full_p;
914  assign phy_ctl_full[0] = |_phy_ctl_full_p;
915  assign phy_ctl_full[3:1] = 3'b000;
916  assign _phy_clk = phy_clk;
917 
918 end
919 endgenerate
920 
921 
922 // instance of four-lane phy
923 
924 generate
925 
926 if (HIGHEST_BANK == 3) begin : banks_3
927  assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],byte_rd_en_v[2]};
928  assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],byte_rd_en_v[2]};
929  assign byte_rd_en_oth_banks[5:4] = {byte_rd_en_v[0],byte_rd_en_v[1]};
930 end
931 else if (HIGHEST_BANK == 2) begin : banks_2
932  assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],1'b1};
933  assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],1'b1};
934 end
935 else begin : banks_1
936  assign byte_rd_en_oth_banks[1:0] = {1'b1,1'b1};
937 end
938 
939 if ( BYTE_LANES_B0 != 0) begin : ddr_phy_4lanes_0
940 mig_7series_v1_9_ddr_phy_4lanes #
941  (
942  .BYTE_LANES (BYTE_LANES_B0), /* four bits, one per lanes **/
943  .DATA_CTL_N (PHY_0_DATA_CTL), /* four bits, one per lane **/
944  .PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
945  .PO_FINE_DELAY (L_PHY_0_PO_FINE_DELAY),
946  .BITLANES (PHY_0_BITLANES),
947  .BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
948  .BYTELANES_DDR_CK (LP_PHY_0_BYTELANES_DDR_CK),
949  .LAST_BANK (PHY_0_IS_LAST_BANK),
950  .LANE_REMAP (PHY_0_LANE_REMAP),
951  .OF_ALMOST_FULL_VALUE (PHY_0_OF_ALMOST_FULL_VALUE),
952  .IF_ALMOST_EMPTY_VALUE (PHY_0_IF_ALMOST_EMPTY_VALUE),
953  .GENERATE_IDELAYCTRL (PHY_0_GENERATE_IDELAYCTRL),
954  .IODELAY_GRP (PHY_0_IODELAY_GRP),
955  .BANK_TYPE (BANK_TYPE),
956  .NUM_DDR_CK (NUM_DDR_CK),
957  .TCK (TCK),
958  .RCLK_SELECT_LANE (RCLK_SELECT_LANE),
959  .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
960  .SYNTHESIS (SYNTHESIS),
961  .PC_CLK_RATIO (PHY_CLK_RATIO),
962  .PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
963  .PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
964  .PC_BURST_MODE (PHY_0_A_BURST_MODE),
965  .PC_SYNC_MODE (PHY_SYNC_MODE),
966  .PC_MULTI_REGION (PHY_MULTI_REGION),
967  .PC_PHY_COUNT_EN (PHY_COUNT_EN),
968  .PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
969  .PC_CMD_OFFSET (PHY_0_CMD_OFFSET),
970  .PC_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
971  .PC_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
972  .PC_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
973  .PC_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
974  .PC_RD_DURATION_0 (PHY_0_RD_DURATION_0),
975  .PC_RD_DURATION_1 (PHY_0_RD_DURATION_1),
976  .PC_RD_DURATION_2 (PHY_0_RD_DURATION_2),
977  .PC_RD_DURATION_3 (PHY_0_RD_DURATION_3),
978  .PC_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
979  .PC_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
980  .PC_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
981  .PC_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
982  .PC_WR_DURATION_0 (PHY_0_WR_DURATION_0),
983  .PC_WR_DURATION_1 (PHY_0_WR_DURATION_1),
984  .PC_WR_DURATION_2 (PHY_0_WR_DURATION_2),
985  .PC_WR_DURATION_3 (PHY_0_WR_DURATION_3),
986  .PC_AO_WRLVL_EN (PHY_0_AO_WRLVL_EN),
987  .PC_AO_TOGGLE (PHY_0_AO_TOGGLE),
988 
989  .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
990 
991  .A_PI_FINE_DELAY (L_PHY_0_A_PI_FINE_DELAY),
992  .B_PI_FINE_DELAY (L_PHY_0_B_PI_FINE_DELAY),
993  .C_PI_FINE_DELAY (L_PHY_0_C_PI_FINE_DELAY),
994  .D_PI_FINE_DELAY (L_PHY_0_D_PI_FINE_DELAY),
995 
996  .A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
997  .A_PI_BURST_MODE (PHY_0_A_BURST_MODE),
998  .A_PI_OUTPUT_CLK_SRC (L_PHY_0_A_PI_OUTPUT_CLK_SRC),
999  .B_PI_OUTPUT_CLK_SRC (L_PHY_0_B_PI_OUTPUT_CLK_SRC),
1000  .C_PI_OUTPUT_CLK_SRC (L_PHY_0_C_PI_OUTPUT_CLK_SRC),
1001  .D_PI_OUTPUT_CLK_SRC (L_PHY_0_D_PI_OUTPUT_CLK_SRC),
1002  .A_PO_OUTPUT_CLK_SRC (PHY_0_A_PO_OUTPUT_CLK_SRC),
1003  .A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
1004  .A_PO_OCLKDELAY_INV (PHY_0_A_PO_OCLKDELAY_INV),
1005  .A_OF_ARRAY_MODE (PHY_0_A_OF_ARRAY_MODE),
1006  .B_OF_ARRAY_MODE (PHY_0_B_OF_ARRAY_MODE),
1007  .C_OF_ARRAY_MODE (PHY_0_C_OF_ARRAY_MODE),
1008  .D_OF_ARRAY_MODE (PHY_0_D_OF_ARRAY_MODE),
1009  .A_IF_ARRAY_MODE (PHY_0_A_IF_ARRAY_MODE),
1010  .B_IF_ARRAY_MODE (PHY_0_B_IF_ARRAY_MODE),
1011  .C_IF_ARRAY_MODE (PHY_0_C_IF_ARRAY_MODE),
1012  .D_IF_ARRAY_MODE (PHY_0_D_IF_ARRAY_MODE),
1013  .A_OS_DATA_RATE (PHY_0_A_OSERDES_DATA_RATE),
1014  .A_OS_DATA_WIDTH (PHY_0_A_OSERDES_DATA_WIDTH),
1015  .B_OS_DATA_RATE (PHY_0_B_OSERDES_DATA_RATE),
1016  .B_OS_DATA_WIDTH (PHY_0_B_OSERDES_DATA_WIDTH),
1017  .C_OS_DATA_RATE (PHY_0_C_OSERDES_DATA_RATE),
1018  .C_OS_DATA_WIDTH (PHY_0_C_OSERDES_DATA_WIDTH),
1019  .D_OS_DATA_RATE (PHY_0_D_OSERDES_DATA_RATE),
1020  .D_OS_DATA_WIDTH (PHY_0_D_OSERDES_DATA_WIDTH),
1021  .A_IDELAYE2_IDELAY_TYPE (PHY_0_A_IDELAYE2_IDELAY_TYPE),
1022  .A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE)
1023  ,.CKE_ODT_AUX (CKE_ODT_AUX)
1024 )
1025  u_ddr_phy_4lanes
1026 (
1027  .rst (rst),
1028  .phy_clk (phy_clk_split0),
1029  .phy_ctl_clk (phy_ctl_clk_split0),
1030  .phy_ctl_wd (phy_ctl_wd_split0),
1031  .data_offset (phy_ctl_wd_split0[PC_DATA_OFFSET_RANGE_HI : PC_DATA_OFFSET_RANGE_LO]),
1032  .phy_ctl_wr (phy_ctl_wr_split0),
1033  .mem_refclk (mem_refclk_split),
1034  .freq_refclk (freq_refclk_split),
1035  .mem_refclk_div4 (mem_refclk_div4_split),
1036  .sync_pulse (sync_pulse_split),
1037  .phy_dout (phy_dout_split0[HIGHEST_LANE_B0*80-1:0]),
1038  .phy_cmd_wr_en (phy_cmd_wr_en_split0),
1039  .phy_data_wr_en (phy_data_wr_en_split0),
1040  .phy_rd_en (phy_rd_en_split0),
1041  .pll_lock (pll_lock),
1042  .ddr_clk (ddr_clk_w[0]),
1043  .rclk (),
1044  .rst_out (rst_out_w[0]),
1045  .mcGo (mcGo_w[0]),
1046  .ref_dll_lock (ref_dll_lock_w[0]),
1047  .idelayctrl_refclk (idelayctrl_refclk),
1048  .idelay_inc (idelay_inc),
1049  .idelay_ce (idelay_ce),
1050  .idelay_ld (idelay_ld),
1051  .phy_ctl_mstr_empty (phy_ctl_mstr_empty),
1052  .if_rst (if_rst),
1053  .if_empty_def (if_empty_def),
1054  .byte_rd_en_oth_banks (byte_rd_en_oth_banks[1:0]),
1055  .if_a_empty (if_a_empty_v[0]),
1056  .if_empty (if_empty_v[0]),
1057  .byte_rd_en (byte_rd_en_v[0]),
1058  .if_empty_or (if_empty_or_v[0]),
1059  .if_empty_and (if_empty_and_v[0]),
1060  .of_ctl_a_full (of_ctl_a_full_v[0]),
1061  .of_data_a_full (of_data_a_full_v[0]),
1062  .of_ctl_full (of_ctl_full_v[0]),
1063  .of_data_full (of_data_full_v[0]),
1064  .pre_data_a_full (pre_data_a_full_v[0]),
1065  .phy_din (phy_din[HIGHEST_LANE_B0*80-1:0]),
1066  .phy_ctl_a_full (_phy_ctl_a_full_p[0]),
1067  .phy_ctl_full (_phy_ctl_full_p[0]),
1068  .phy_ctl_empty (phy_ctl_empty[0]),
1069  .mem_dq_out (mem_dq_out[HIGHEST_LANE_B0*12-1:0]),
1070  .mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B0*12-1:0]),
1071  .mem_dq_in (mem_dq_in[HIGHEST_LANE_B0*10-1:0]),
1072  .mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B0-1:0]),
1073  .mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B0-1:0]),
1074  .mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B0-1:0]),
1075  .aux_out (aux_out_[3:0]),
1076  .phy_ctl_ready (phy_ctl_ready_w[0]),
1077  .phy_write_calib (phy_write_calib),
1078  .phy_read_calib (phy_read_calib),
1079 // .scan_test_bus_A (scan_test_bus_A),
1080 // .scan_test_bus_B (),
1081 // .scan_test_bus_C (),
1082 // .scan_test_bus_D (),
1083  .phyGo (phyGo),
1084  .input_sink (input_sink),
1085 
1086  .calib_sel (calib_sel_byte0),
1087  .calib_zero_ctrl (calib_zero_ctrl[0]),
1088  .calib_zero_lanes (calib_zero_lanes_int[3:0]),
1089  .calib_in_common (calib_in_common),
1090  .po_coarse_enable (po_coarse_enable[0]),
1091  .po_fine_enable (po_fine_enable[0]),
1092  .po_fine_inc (po_fine_inc[0]),
1093  .po_coarse_inc (po_coarse_inc[0]),
1094  .po_counter_load_en (po_counter_load_en),
1095  .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[0]),
1096  .po_counter_load_val (po_counter_load_val),
1097  .po_counter_read_en (po_counter_read_en),
1098  .po_coarse_overflow (po_coarse_overflow_w[0]),
1099  .po_fine_overflow (po_fine_overflow_w[0]),
1100  .po_counter_read_val (po_counter_read_val_w[0]),
1101 
1102  .pi_rst_dqs_find (pi_rst_dqs_find[0]),
1103  .pi_fine_enable (pi_fine_enable),
1104  .pi_fine_inc (pi_fine_inc),
1105  .pi_counter_load_en (pi_counter_load_en),
1106  .pi_counter_read_en (pi_counter_read_en),
1107  .pi_counter_load_val (pi_counter_load_val),
1108  .pi_fine_overflow (pi_fine_overflow_w[0]),
1109  .pi_counter_read_val (pi_counter_read_val_w[0]),
1110  .pi_dqs_found (pi_dqs_found_w[0]),
1111  .pi_dqs_found_all (pi_dqs_found_all_w[0]),
1112  .pi_dqs_found_any (pi_dqs_found_any_w[0]),
1113  .pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0]),
1114  .pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0]),
1115  .pi_dqs_out_of_range (pi_dqs_out_of_range_w[0]),
1116  .pi_phase_locked (pi_phase_locked_w[0]),
1117  .pi_phase_locked_all (pi_phase_locked_all_w[0])
1118 );
1119 
1120  always @(posedge auxout_clk or posedge rst_auxout) begin
1121  if (rst_auxout) begin
1122  aux_out[0] <= #100 0;
1123  aux_out[2] <= #100 0;
1124  end
1125  else begin
1126  aux_out[0] <= #100 aux_out_[0];
1127  aux_out[2] <= #100 aux_out_[2];
1128  end
1129  end
1130  if ( LP_RCLK_SELECT_EDGE[0]) begin
1131  always @(posedge auxout_clk or posedge rst_auxout) begin
1132  if (rst_auxout) begin
1133  aux_out[1] <= #100 0;
1134  aux_out[3] <= #100 0;
1135  end
1136  else begin
1137  aux_out[1] <= #100 aux_out_[1];
1138  aux_out[3] <= #100 aux_out_[3];
1139  end
1140  end
1141  end
1142  else begin
1143  always @(negedge auxout_clk or posedge rst_auxout) begin
1144  if (rst_auxout) begin
1145  aux_out[1] <= #100 0;
1146  aux_out[3] <= #100 0;
1147  end
1148  else begin
1149  aux_out[1] <= #100 aux_out_[1];
1150  aux_out[3] <= #100 aux_out_[3];
1151  end
1152  end
1153  end
1154 end
1155 else begin
1156  if ( HIGHEST_BANK > 0) begin
1157  assign phy_din[HIGHEST_LANE_B0*80-1:0] = 0;
1158  assign _phy_ctl_a_full_p[0] = 0;
1159  assign of_ctl_a_full_v[0] = 0;
1160  assign of_ctl_full_v[0] = 0;
1161  assign of_data_a_full_v[0] = 0;
1162  assign of_data_full_v[0] = 0;
1163  assign pre_data_a_full_v[0] = 0;
1164  assign if_empty_v[0] = 0;
1165  assign byte_rd_en_v[0] = 1;
1166  always @(*)
1167  aux_out[3:0] = 0;
1168  end
1169  assign pi_dqs_found_w[0] = 1;
1170  assign pi_dqs_found_all_w[0] = 1;
1171  assign pi_dqs_found_any_w[0] = 0;
1172  assign pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
1173  assign pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
1174  assign pi_dqs_out_of_range_w[0] = 0;
1175  assign pi_phase_locked_w[0] = 1;
1176  assign po_fine_overflow_w[0] = 0;
1177  assign po_coarse_overflow_w[0] = 0;
1178  assign po_fine_overflow_w[0] = 0;
1179  assign pi_fine_overflow_w[0] = 0;
1180  assign po_counter_read_val_w[0] = 0;
1181  assign pi_counter_read_val_w[0] = 0;
1182  assign mcGo_w[0] = 1;
1183  if ( RCLK_SELECT_BANK == 0)
1184  always @(*)
1185  aux_out[3:0] = 0;
1186 end
1187 
1188 if ( BYTE_LANES_B1 != 0) begin : ddr_phy_4lanes_1
1189 
1190 mig_7series_v1_9_ddr_phy_4lanes #
1191  (
1192  .BYTE_LANES (BYTE_LANES_B1), /* four bits, one per lanes **/
1193  .DATA_CTL_N (PHY_1_DATA_CTL), /* four bits, one per lane **/
1194  .PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
1195  .PO_FINE_DELAY (L_PHY_1_PO_FINE_DELAY),
1196  .BITLANES (PHY_1_BITLANES),
1197  .BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
1198  .BYTELANES_DDR_CK (LP_PHY_1_BYTELANES_DDR_CK),
1199  .LAST_BANK (PHY_1_IS_LAST_BANK ),
1200  .LANE_REMAP (PHY_1_LANE_REMAP),
1201  .OF_ALMOST_FULL_VALUE (PHY_1_OF_ALMOST_FULL_VALUE),
1202  .IF_ALMOST_EMPTY_VALUE (PHY_1_IF_ALMOST_EMPTY_VALUE),
1203  .GENERATE_IDELAYCTRL (PHY_1_GENERATE_IDELAYCTRL),
1204  .IODELAY_GRP (PHY_1_IODELAY_GRP),
1205  .BANK_TYPE (BANK_TYPE),
1206  .NUM_DDR_CK (NUM_DDR_CK),
1207  .TCK (TCK),
1208  .RCLK_SELECT_LANE (RCLK_SELECT_LANE),
1209  .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
1210  .SYNTHESIS (SYNTHESIS),
1211  .PC_CLK_RATIO (PHY_CLK_RATIO),
1212  .PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
1213  .PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
1214  .PC_BURST_MODE (PHY_1_A_BURST_MODE),
1215  .PC_SYNC_MODE (PHY_SYNC_MODE),
1216  .PC_MULTI_REGION (PHY_MULTI_REGION),
1217  .PC_PHY_COUNT_EN (PHY_COUNT_EN),
1218  .PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
1219  .PC_CMD_OFFSET (PHY_1_CMD_OFFSET),
1220  .PC_RD_CMD_OFFSET_0 (PHY_1_RD_CMD_OFFSET_0),
1221  .PC_RD_CMD_OFFSET_1 (PHY_1_RD_CMD_OFFSET_1),
1222  .PC_RD_CMD_OFFSET_2 (PHY_1_RD_CMD_OFFSET_2),
1223  .PC_RD_CMD_OFFSET_3 (PHY_1_RD_CMD_OFFSET_3),
1224  .PC_RD_DURATION_0 (PHY_1_RD_DURATION_0),
1225  .PC_RD_DURATION_1 (PHY_1_RD_DURATION_1),
1226  .PC_RD_DURATION_2 (PHY_1_RD_DURATION_2),
1227  .PC_RD_DURATION_3 (PHY_1_RD_DURATION_3),
1228  .PC_WR_CMD_OFFSET_0 (PHY_1_WR_CMD_OFFSET_0),
1229  .PC_WR_CMD_OFFSET_1 (PHY_1_WR_CMD_OFFSET_1),
1230  .PC_WR_CMD_OFFSET_2 (PHY_1_WR_CMD_OFFSET_2),
1231  .PC_WR_CMD_OFFSET_3 (PHY_1_WR_CMD_OFFSET_3),
1232  .PC_WR_DURATION_0 (PHY_1_WR_DURATION_0),
1233  .PC_WR_DURATION_1 (PHY_1_WR_DURATION_1),
1234  .PC_WR_DURATION_2 (PHY_1_WR_DURATION_2),
1235  .PC_WR_DURATION_3 (PHY_1_WR_DURATION_3),
1236  .PC_AO_WRLVL_EN (PHY_1_AO_WRLVL_EN),
1237  .PC_AO_TOGGLE (PHY_1_AO_TOGGLE),
1238 
1239  .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
1240 
1241  .A_PI_FINE_DELAY (L_PHY_1_A_PI_FINE_DELAY),
1242  .B_PI_FINE_DELAY (L_PHY_1_B_PI_FINE_DELAY),
1243  .C_PI_FINE_DELAY (L_PHY_1_C_PI_FINE_DELAY),
1244  .D_PI_FINE_DELAY (L_PHY_1_D_PI_FINE_DELAY),
1245 
1246  .A_PI_FREQ_REF_DIV (PHY_1_A_PI_FREQ_REF_DIV),
1247  .A_PI_BURST_MODE (PHY_1_A_BURST_MODE),
1248  .A_PI_OUTPUT_CLK_SRC (L_PHY_1_A_PI_OUTPUT_CLK_SRC),
1249  .B_PI_OUTPUT_CLK_SRC (L_PHY_1_B_PI_OUTPUT_CLK_SRC),
1250  .C_PI_OUTPUT_CLK_SRC (L_PHY_1_C_PI_OUTPUT_CLK_SRC),
1251  .D_PI_OUTPUT_CLK_SRC (L_PHY_1_D_PI_OUTPUT_CLK_SRC),
1252  .A_PO_OUTPUT_CLK_SRC (PHY_1_A_PO_OUTPUT_CLK_SRC),
1253  .A_PO_OCLK_DELAY (PHY_1_A_PO_OCLK_DELAY),
1254  .A_PO_OCLKDELAY_INV (PHY_1_A_PO_OCLKDELAY_INV),
1255  .A_OF_ARRAY_MODE (PHY_1_A_OF_ARRAY_MODE),
1256  .B_OF_ARRAY_MODE (PHY_1_B_OF_ARRAY_MODE),
1257  .C_OF_ARRAY_MODE (PHY_1_C_OF_ARRAY_MODE),
1258  .D_OF_ARRAY_MODE (PHY_1_D_OF_ARRAY_MODE),
1259  .A_IF_ARRAY_MODE (PHY_1_A_IF_ARRAY_MODE),
1260  .B_IF_ARRAY_MODE (PHY_1_B_IF_ARRAY_MODE),
1261  .C_IF_ARRAY_MODE (PHY_1_C_IF_ARRAY_MODE),
1262  .D_IF_ARRAY_MODE (PHY_1_D_IF_ARRAY_MODE),
1263  .A_OS_DATA_RATE (PHY_1_A_OSERDES_DATA_RATE),
1264  .A_OS_DATA_WIDTH (PHY_1_A_OSERDES_DATA_WIDTH),
1265  .B_OS_DATA_RATE (PHY_1_B_OSERDES_DATA_RATE),
1266  .B_OS_DATA_WIDTH (PHY_1_B_OSERDES_DATA_WIDTH),
1267  .C_OS_DATA_RATE (PHY_1_C_OSERDES_DATA_RATE),
1268  .C_OS_DATA_WIDTH (PHY_1_C_OSERDES_DATA_WIDTH),
1269  .D_OS_DATA_RATE (PHY_1_D_OSERDES_DATA_RATE),
1270  .D_OS_DATA_WIDTH (PHY_1_D_OSERDES_DATA_WIDTH),
1271  .A_IDELAYE2_IDELAY_TYPE (PHY_1_A_IDELAYE2_IDELAY_TYPE),
1272  .A_IDELAYE2_IDELAY_VALUE (PHY_1_A_IDELAYE2_IDELAY_VALUE)
1273  ,.CKE_ODT_AUX (CKE_ODT_AUX)
1274 )
1275  u_ddr_phy_4lanes
1276 (
1277  .rst (rst),
1278  .phy_clk (phy_clk_split1),
1279  .phy_ctl_clk (phy_ctl_clk_split1),
1280  .phy_ctl_wd (phy_ctl_wd_split1),
1281  .data_offset (phy_data_offset_1_split1),
1282  .phy_ctl_wr (phy_ctl_wr_split1),
1283  .mem_refclk (mem_refclk_split),
1284  .freq_refclk (freq_refclk_split),
1285  .mem_refclk_div4 (mem_refclk_div4_split),
1286  .sync_pulse (sync_pulse_split),
1287  .phy_dout (phy_dout_split1[HIGHEST_LANE_B1*80+320-1:320]),
1288  .phy_cmd_wr_en (phy_cmd_wr_en_split1),
1289  .phy_data_wr_en (phy_data_wr_en_split1),
1290  .phy_rd_en (phy_rd_en_split1),
1291  .pll_lock (pll_lock),
1292  .ddr_clk (ddr_clk_w[1]),
1293  .rclk (),
1294  .rst_out (rst_out_w[1]),
1295  .mcGo (mcGo_w[1]),
1296  .ref_dll_lock (ref_dll_lock_w[1]),
1297  .idelayctrl_refclk (idelayctrl_refclk),
1298  .idelay_inc (idelay_inc),
1299  .idelay_ce (idelay_ce),
1300  .idelay_ld (idelay_ld),
1301  .phy_ctl_mstr_empty (phy_ctl_mstr_empty),
1302  .if_rst (if_rst),
1303  .if_empty_def (if_empty_def),
1304  .byte_rd_en_oth_banks (byte_rd_en_oth_banks[3:2]),
1305  .if_a_empty (if_a_empty_v[1]),
1306  .if_empty (if_empty_v[1]),
1307  .byte_rd_en (byte_rd_en_v[1]),
1308  .if_empty_or (if_empty_or_v[1]),
1309  .if_empty_and (if_empty_and_v[1]),
1310  .of_ctl_a_full (of_ctl_a_full_v[1]),
1311  .of_data_a_full (of_data_a_full_v[1]),
1312  .of_ctl_full (of_ctl_full_v[1]),
1313  .of_data_full (of_data_full_v[1]),
1314  .pre_data_a_full (pre_data_a_full_v[1]),
1315  .phy_din (phy_din[HIGHEST_LANE_B1*80+320-1:320]),
1316  .phy_ctl_a_full (_phy_ctl_a_full_p[1]),
1317  .phy_ctl_full (_phy_ctl_full_p[1]),
1318  .phy_ctl_empty (phy_ctl_empty[1]),
1319  .mem_dq_out (mem_dq_out[HIGHEST_LANE_B1*12+48-1:48]),
1320  .mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B1*12+48-1:48]),
1321  .mem_dq_in (mem_dq_in[HIGHEST_LANE_B1*10+40-1:40]),
1322  .mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B1+4-1:4]),
1323  .mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B1+4-1:4]),
1324  .mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B1+4-1:4]),
1325  .aux_out (aux_out_[7:4]),
1326  .phy_ctl_ready (phy_ctl_ready_w[1]),
1327  .phy_write_calib (phy_write_calib),
1328  .phy_read_calib (phy_read_calib),
1329 // .scan_test_bus_A (scan_test_bus_A),
1330 // .scan_test_bus_B (),
1331 // .scan_test_bus_C (),
1332 // .scan_test_bus_D (),
1333  .phyGo (phyGo),
1334  .input_sink (input_sink),
1335 
1336  .calib_sel (calib_sel_byte1),
1337  .calib_zero_ctrl (calib_zero_ctrl[1]),
1338  .calib_zero_lanes (calib_zero_lanes_int[7:4]),
1339  .calib_in_common (calib_in_common),
1340  .po_coarse_enable (po_coarse_enable[1]),
1341  .po_fine_enable (po_fine_enable[1]),
1342  .po_fine_inc (po_fine_inc[1]),
1343  .po_coarse_inc (po_coarse_inc[1]),
1344  .po_counter_load_en (po_counter_load_en),
1345  .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[1]),
1346  .po_counter_load_val (po_counter_load_val),
1347  .po_counter_read_en (po_counter_read_en),
1348  .po_coarse_overflow (po_coarse_overflow_w[1]),
1349  .po_fine_overflow (po_fine_overflow_w[1]),
1350  .po_counter_read_val (po_counter_read_val_w[1]),
1351 
1352  .pi_rst_dqs_find (pi_rst_dqs_find[1]),
1353  .pi_fine_enable (pi_fine_enable),
1354  .pi_fine_inc (pi_fine_inc),
1355  .pi_counter_load_en (pi_counter_load_en),
1356  .pi_counter_read_en (pi_counter_read_en),
1357  .pi_counter_load_val (pi_counter_load_val),
1358  .pi_fine_overflow (pi_fine_overflow_w[1]),
1359  .pi_counter_read_val (pi_counter_read_val_w[1]),
1360  .pi_dqs_found (pi_dqs_found_w[1]),
1361  .pi_dqs_found_all (pi_dqs_found_all_w[1]),
1362  .pi_dqs_found_any (pi_dqs_found_any_w[1]),
1363  .pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4]),
1364  .pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4]),
1365  .pi_dqs_out_of_range (pi_dqs_out_of_range_w[1]),
1366  .pi_phase_locked (pi_phase_locked_w[1]),
1367  .pi_phase_locked_all (pi_phase_locked_all_w[1])
1368 );
1369 
1370  always @(posedge auxout_clk or posedge rst_auxout) begin
1371  if (rst_auxout) begin
1372  aux_out[4] <= #100 0;
1373  aux_out[6] <= #100 0;
1374  end
1375  else begin
1376  aux_out[4] <= #100 aux_out_[4];
1377  aux_out[6] <= #100 aux_out_[6];
1378  end
1379  end
1380  if ( LP_RCLK_SELECT_EDGE[1]) begin
1381  always @(posedge auxout_clk or posedge rst_auxout) begin
1382  if (rst_auxout) begin
1383  aux_out[5] <= #100 0;
1384  aux_out[7] <= #100 0;
1385  end
1386  else begin
1387  aux_out[5] <= #100 aux_out_[5];
1388  aux_out[7] <= #100 aux_out_[7];
1389  end
1390  end
1391  end
1392  else begin
1393  always @(negedge auxout_clk or posedge rst_auxout) begin
1394  if (rst_auxout) begin
1395  aux_out[5] <= #100 0;
1396  aux_out[7] <= #100 0;
1397  end
1398  else begin
1399  aux_out[5] <= #100 aux_out_[5];
1400  aux_out[7] <= #100 aux_out_[7];
1401  end
1402  end
1403  end
1404 end
1405 else begin
1406  if ( HIGHEST_BANK > 1) begin
1407  assign phy_din[HIGHEST_LANE_B1*80+320-1:320] = 0;
1408  assign _phy_ctl_a_full_p[1] = 0;
1409  assign of_ctl_a_full_v[1] = 0;
1410  assign of_ctl_full_v[1] = 0;
1411  assign of_data_a_full_v[1] = 0;
1412  assign of_data_full_v[1] = 0;
1413  assign pre_data_a_full_v[1] = 0;
1414  assign if_empty_v[1] = 0;
1415  assign byte_rd_en_v[1] = 1;
1416  assign pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
1417  assign pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
1418  always @(*)
1419  aux_out[7:4] = 0;
1420  end
1421  assign pi_dqs_found_w[1] = 1;
1422  assign pi_dqs_found_all_w[1] = 1;
1423  assign pi_dqs_found_any_w[1] = 0;
1424  assign pi_dqs_out_of_range_w[1] = 0;
1425  assign pi_phase_locked_w[1] = 1;
1426  assign po_coarse_overflow_w[1] = 0;
1427  assign po_fine_overflow_w[1] = 0;
1428  assign pi_fine_overflow_w[1] = 0;
1429  assign po_counter_read_val_w[1] = 0;
1430  assign pi_counter_read_val_w[1] = 0;
1431  assign mcGo_w[1] = 1;
1432 end
1433 
1434 if ( BYTE_LANES_B2 != 0) begin : ddr_phy_4lanes_2
1435 
1436 mig_7series_v1_9_ddr_phy_4lanes #
1437  (
1438  .BYTE_LANES (BYTE_LANES_B2), /* four bits, one per lanes **/
1439  .DATA_CTL_N (PHY_2_DATA_CTL), /* four bits, one per lane **/
1440  .PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
1441  .PO_FINE_DELAY (L_PHY_2_PO_FINE_DELAY),
1442  .BITLANES (PHY_2_BITLANES),
1443  .BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
1444  .BYTELANES_DDR_CK (LP_PHY_2_BYTELANES_DDR_CK),
1445  .LAST_BANK (PHY_2_IS_LAST_BANK ),
1446  .LANE_REMAP (PHY_2_LANE_REMAP),
1447  .OF_ALMOST_FULL_VALUE (PHY_2_OF_ALMOST_FULL_VALUE),
1448  .IF_ALMOST_EMPTY_VALUE (PHY_2_IF_ALMOST_EMPTY_VALUE),
1449  .GENERATE_IDELAYCTRL (PHY_2_GENERATE_IDELAYCTRL),
1450  .IODELAY_GRP (PHY_2_IODELAY_GRP),
1451  .BANK_TYPE (BANK_TYPE),
1452  .NUM_DDR_CK (NUM_DDR_CK),
1453  .TCK (TCK),
1454  .RCLK_SELECT_LANE (RCLK_SELECT_LANE),
1455  .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
1456  .SYNTHESIS (SYNTHESIS),
1457  .PC_CLK_RATIO (PHY_CLK_RATIO),
1458  .PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
1459  .PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
1460  .PC_BURST_MODE (PHY_2_A_BURST_MODE),
1461  .PC_SYNC_MODE (PHY_SYNC_MODE),
1462  .PC_MULTI_REGION (PHY_MULTI_REGION),
1463  .PC_PHY_COUNT_EN (PHY_COUNT_EN),
1464  .PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
1465  .PC_CMD_OFFSET (PHY_2_CMD_OFFSET),
1466  .PC_RD_CMD_OFFSET_0 (PHY_2_RD_CMD_OFFSET_0),
1467  .PC_RD_CMD_OFFSET_1 (PHY_2_RD_CMD_OFFSET_1),
1468  .PC_RD_CMD_OFFSET_2 (PHY_2_RD_CMD_OFFSET_2),
1469  .PC_RD_CMD_OFFSET_3 (PHY_2_RD_CMD_OFFSET_3),
1470  .PC_RD_DURATION_0 (PHY_2_RD_DURATION_0),
1471  .PC_RD_DURATION_1 (PHY_2_RD_DURATION_1),
1472  .PC_RD_DURATION_2 (PHY_2_RD_DURATION_2),
1473  .PC_RD_DURATION_3 (PHY_2_RD_DURATION_3),
1474  .PC_WR_CMD_OFFSET_0 (PHY_2_WR_CMD_OFFSET_0),
1475  .PC_WR_CMD_OFFSET_1 (PHY_2_WR_CMD_OFFSET_1),
1476  .PC_WR_CMD_OFFSET_2 (PHY_2_WR_CMD_OFFSET_2),
1477  .PC_WR_CMD_OFFSET_3 (PHY_2_WR_CMD_OFFSET_3),
1478  .PC_WR_DURATION_0 (PHY_2_WR_DURATION_0),
1479  .PC_WR_DURATION_1 (PHY_2_WR_DURATION_1),
1480  .PC_WR_DURATION_2 (PHY_2_WR_DURATION_2),
1481  .PC_WR_DURATION_3 (PHY_2_WR_DURATION_3),
1482  .PC_AO_WRLVL_EN (PHY_2_AO_WRLVL_EN),
1483  .PC_AO_TOGGLE (PHY_2_AO_TOGGLE),
1484 
1485  .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
1486 
1487  .A_PI_FINE_DELAY (L_PHY_2_A_PI_FINE_DELAY),
1488  .B_PI_FINE_DELAY (L_PHY_2_B_PI_FINE_DELAY),
1489  .C_PI_FINE_DELAY (L_PHY_2_C_PI_FINE_DELAY),
1490  .D_PI_FINE_DELAY (L_PHY_2_D_PI_FINE_DELAY),
1491  .A_PI_FREQ_REF_DIV (PHY_2_A_PI_FREQ_REF_DIV),
1492  .A_PI_BURST_MODE (PHY_2_A_BURST_MODE),
1493  .A_PI_OUTPUT_CLK_SRC (L_PHY_2_A_PI_OUTPUT_CLK_SRC),
1494  .B_PI_OUTPUT_CLK_SRC (L_PHY_2_B_PI_OUTPUT_CLK_SRC),
1495  .C_PI_OUTPUT_CLK_SRC (L_PHY_2_C_PI_OUTPUT_CLK_SRC),
1496  .D_PI_OUTPUT_CLK_SRC (L_PHY_2_D_PI_OUTPUT_CLK_SRC),
1497  .A_PO_OUTPUT_CLK_SRC (PHY_2_A_PO_OUTPUT_CLK_SRC),
1498  .A_PO_OCLK_DELAY (PHY_2_A_PO_OCLK_DELAY),
1499  .A_PO_OCLKDELAY_INV (PHY_2_A_PO_OCLKDELAY_INV),
1500  .A_OF_ARRAY_MODE (PHY_2_A_OF_ARRAY_MODE),
1501  .B_OF_ARRAY_MODE (PHY_2_B_OF_ARRAY_MODE),
1502  .C_OF_ARRAY_MODE (PHY_2_C_OF_ARRAY_MODE),
1503  .D_OF_ARRAY_MODE (PHY_2_D_OF_ARRAY_MODE),
1504  .A_IF_ARRAY_MODE (PHY_2_A_IF_ARRAY_MODE),
1505  .B_IF_ARRAY_MODE (PHY_2_B_IF_ARRAY_MODE),
1506  .C_IF_ARRAY_MODE (PHY_2_C_IF_ARRAY_MODE),
1507  .D_IF_ARRAY_MODE (PHY_2_D_IF_ARRAY_MODE),
1508  .A_OS_DATA_RATE (PHY_2_A_OSERDES_DATA_RATE),
1509  .A_OS_DATA_WIDTH (PHY_2_A_OSERDES_DATA_WIDTH),
1510  .B_OS_DATA_RATE (PHY_2_B_OSERDES_DATA_RATE),
1511  .B_OS_DATA_WIDTH (PHY_2_B_OSERDES_DATA_WIDTH),
1512  .C_OS_DATA_RATE (PHY_2_C_OSERDES_DATA_RATE),
1513  .C_OS_DATA_WIDTH (PHY_2_C_OSERDES_DATA_WIDTH),
1514  .D_OS_DATA_RATE (PHY_2_D_OSERDES_DATA_RATE),
1515  .D_OS_DATA_WIDTH (PHY_2_D_OSERDES_DATA_WIDTH),
1516  .A_IDELAYE2_IDELAY_TYPE (PHY_2_A_IDELAYE2_IDELAY_TYPE),
1517  .A_IDELAYE2_IDELAY_VALUE (PHY_2_A_IDELAYE2_IDELAY_VALUE)
1518  ,.CKE_ODT_AUX (CKE_ODT_AUX)
1519 )
1520  u_ddr_phy_4lanes
1521 (
1522  .rst (rst),
1523  .phy_clk (phy_clk_split2),
1524  .phy_ctl_clk (phy_ctl_clk_split2),
1525  .phy_ctl_wd (phy_ctl_wd_split2),
1526  .data_offset (phy_data_offset_2_split2),
1527  .phy_ctl_wr (phy_ctl_wr_split2),
1528  .mem_refclk (mem_refclk_split),
1529  .freq_refclk (freq_refclk_split),
1530  .mem_refclk_div4 (mem_refclk_div4_split),
1531  .sync_pulse (sync_pulse_split),
1532  .phy_dout (phy_dout_split2[HIGHEST_LANE_B2*80+640-1:640]),
1533  .phy_cmd_wr_en (phy_cmd_wr_en_split2),
1534  .phy_data_wr_en (phy_data_wr_en_split2),
1535  .phy_rd_en (phy_rd_en_split2),
1536  .pll_lock (pll_lock),
1537  .ddr_clk (ddr_clk_w[2]),
1538  .rclk (),
1539  .rst_out (rst_out_w[2]),
1540  .mcGo (mcGo_w[2]),
1541  .ref_dll_lock (ref_dll_lock_w[2]),
1542  .idelayctrl_refclk (idelayctrl_refclk),
1543  .idelay_inc (idelay_inc),
1544  .idelay_ce (idelay_ce),
1545  .idelay_ld (idelay_ld),
1546  .phy_ctl_mstr_empty (phy_ctl_mstr_empty),
1547  .if_rst (if_rst),
1548  .if_empty_def (if_empty_def),
1549  .byte_rd_en_oth_banks (byte_rd_en_oth_banks[5:4]),
1550  .if_a_empty (if_a_empty_v[2]),
1551  .if_empty (if_empty_v[2]),
1552  .byte_rd_en (byte_rd_en_v[2]),
1553  .if_empty_or (if_empty_or_v[2]),
1554  .if_empty_and (if_empty_and_v[2]),
1555  .of_ctl_a_full (of_ctl_a_full_v[2]),
1556  .of_data_a_full (of_data_a_full_v[2]),
1557  .of_ctl_full (of_ctl_full_v[2]),
1558  .of_data_full (of_data_full_v[2]),
1559  .pre_data_a_full (pre_data_a_full_v[2]),
1560  .phy_din (phy_din[HIGHEST_LANE_B2*80+640-1:640]),
1561  .phy_ctl_a_full (_phy_ctl_a_full_p[2]),
1562  .phy_ctl_full (_phy_ctl_full_p[2]),
1563  .phy_ctl_empty (phy_ctl_empty[2]),
1564  .mem_dq_out (mem_dq_out[HIGHEST_LANE_B2*12+96-1:96]),
1565  .mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B2*12+96-1:96]),
1566  .mem_dq_in (mem_dq_in[HIGHEST_LANE_B2*10+80-1:80]),
1567  .mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B2-1+8:8]),
1568  .mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B2-1+8:8]),
1569  .mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B2-1+8:8]),
1570  .aux_out (aux_out_[11:8]),
1571  .phy_ctl_ready (phy_ctl_ready_w[2]),
1572  .phy_write_calib (phy_write_calib),
1573  .phy_read_calib (phy_read_calib),
1574 // .scan_test_bus_A (scan_test_bus_A),
1575 // .scan_test_bus_B (),
1576 // .scan_test_bus_C (),
1577 // .scan_test_bus_D (),
1578  .phyGo (phyGo),
1579  .input_sink (input_sink),
1580 
1581  .calib_sel (calib_sel_byte2),
1582  .calib_zero_ctrl (calib_zero_ctrl[2]),
1583  .calib_zero_lanes (calib_zero_lanes_int[11:8]),
1584  .calib_in_common (calib_in_common),
1585  .po_coarse_enable (po_coarse_enable[2]),
1586  .po_fine_enable (po_fine_enable[2]),
1587  .po_fine_inc (po_fine_inc[2]),
1588  .po_coarse_inc (po_coarse_inc[2]),
1589  .po_counter_load_en (po_counter_load_en),
1590  .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[2]),
1591  .po_counter_load_val (po_counter_load_val),
1592  .po_counter_read_en (po_counter_read_en),
1593  .po_coarse_overflow (po_coarse_overflow_w[2]),
1594  .po_fine_overflow (po_fine_overflow_w[2]),
1595  .po_counter_read_val (po_counter_read_val_w[2]),
1596 
1597  .pi_rst_dqs_find (pi_rst_dqs_find[2]),
1598  .pi_fine_enable (pi_fine_enable),
1599  .pi_fine_inc (pi_fine_inc),
1600  .pi_counter_load_en (pi_counter_load_en),
1601  .pi_counter_read_en (pi_counter_read_en),
1602  .pi_counter_load_val (pi_counter_load_val),
1603  .pi_fine_overflow (pi_fine_overflow_w[2]),
1604  .pi_counter_read_val (pi_counter_read_val_w[2]),
1605  .pi_dqs_found (pi_dqs_found_w[2]),
1606  .pi_dqs_found_all (pi_dqs_found_all_w[2]),
1607  .pi_dqs_found_any (pi_dqs_found_any_w[2]),
1608  .pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8]),
1609  .pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8]),
1610  .pi_dqs_out_of_range (pi_dqs_out_of_range_w[2]),
1611  .pi_phase_locked (pi_phase_locked_w[2]),
1612  .pi_phase_locked_all (pi_phase_locked_all_w[2])
1613 );
1614  always @(posedge auxout_clk or posedge rst_auxout) begin
1615  if (rst_auxout) begin
1616  aux_out[8] <= #100 0;
1617  aux_out[10] <= #100 0;
1618  end
1619  else begin
1620  aux_out[8] <= #100 aux_out_[8];
1621  aux_out[10] <= #100 aux_out_[10];
1622  end
1623  end
1624  if ( LP_RCLK_SELECT_EDGE[1]) begin
1625  always @(posedge auxout_clk or posedge rst_auxout) begin
1626  if (rst_auxout) begin
1627  aux_out[9] <= #100 0;
1628  aux_out[11] <= #100 0;
1629  end
1630  else begin
1631  aux_out[9] <= #100 aux_out_[9];
1632  aux_out[11] <= #100 aux_out_[11];
1633  end
1634  end
1635  end
1636  else begin
1637  always @(negedge auxout_clk or posedge rst_auxout) begin
1638  if (rst_auxout) begin
1639  aux_out[9] <= #100 0;
1640  aux_out[11] <= #100 0;
1641  end
1642  else begin
1643  aux_out[9] <= #100 aux_out_[9];
1644  aux_out[11] <= #100 aux_out_[11];
1645  end
1646  end
1647  end
1648 end
1649 else begin
1650  if ( HIGHEST_BANK > 2) begin
1651  assign phy_din[HIGHEST_LANE_B2*80+640-1:640] = 0;
1652  assign _phy_ctl_a_full_p[2] = 0;
1653  assign of_ctl_a_full_v[2] = 0;
1654  assign of_ctl_full_v[2] = 0;
1655  assign of_data_a_full_v[2] = 0;
1656  assign of_data_full_v[2] = 0;
1657  assign pre_data_a_full_v[2] = 0;
1658  assign if_empty_v[2] = 0;
1659  assign byte_rd_en_v[2] = 1;
1660  assign pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
1661  assign pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
1662  always @(*)
1663  aux_out[11:8] = 0;
1664  end
1665  assign pi_dqs_found_w[2] = 1;
1666  assign pi_dqs_found_all_w[2] = 1;
1667  assign pi_dqs_found_any_w[2] = 0;
1668  assign pi_dqs_out_of_range_w[2] = 0;
1669  assign pi_phase_locked_w[2] = 1;
1670  assign po_coarse_overflow_w[2] = 0;
1671  assign po_fine_overflow_w[2] = 0;
1672  assign po_counter_read_val_w[2] = 0;
1673  assign pi_counter_read_val_w[2] = 0;
1674  assign mcGo_w[2] = 1;
1675 end
1676 endgenerate
1677 
1678 generate
1679 
1680 // for single bank , emit an extra phaser_in to generate rclk
1681 // so that auxout can be placed in another region
1682 // if desired
1683 
1684 if ( BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK>0)
1685 begin : phaser_in_rclk
1686 
1687 localparam L_EXTRA_PI_FINE_DELAY = DEFAULT_RCLK_DELAY;
1688 
1689 PHASER_IN_PHY #(
1690  .BURST_MODE ( PHY_0_A_BURST_MODE),
1691  .CLKOUT_DIV ( PHY_0_A_PI_CLKOUT_DIV),
1692  .FREQ_REF_DIV ( PHY_0_A_PI_FREQ_REF_DIV),
1693  .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
1694  .FINE_DELAY ( L_EXTRA_PI_FINE_DELAY),
1695  .OUTPUT_CLK_SRC ( RCLK_PI_OUTPUT_CLK_SRC)
1696 ) phaser_in_rclk (
1697  .DQSFOUND (),
1698  .DQSOUTOFRANGE (),
1699  .FINEOVERFLOW (),
1700  .PHASELOCKED (),
1701  .ISERDESRST (),
1702  .ICLKDIV (),
1703  .ICLK (),
1704  .COUNTERREADVAL (),
1705  .RCLK (),
1706  .WRENABLE (),
1707  .BURSTPENDINGPHY (),
1708  .ENCALIBPHY (),
1709  .FINEENABLE (0),
1710  .FREQREFCLK (freq_refclk),
1711  .MEMREFCLK (mem_refclk),
1712  .RANKSELPHY (0),
1713  .PHASEREFCLK (),
1714  .RSTDQSFIND (0),
1715  .RST (rst),
1716  .FINEINC (),
1717  .COUNTERLOADEN (),
1718  .COUNTERREADEN (),
1719  .COUNTERLOADVAL (),
1720  .SYNCIN (sync_pulse),
1721  .SYSCLK (phy_clk)
1722 );
1723 
1724 end
1725 
1726 endgenerate
1727 
1728 
1729 
1730 always @(*) begin
1731  case (calib_sel[5:3])
1732  3'b000: begin
1733  po_coarse_overflow = po_coarse_overflow_w[0];
1734  po_fine_overflow = po_fine_overflow_w[0];
1735  po_counter_read_val = po_counter_read_val_w[0];
1736  pi_fine_overflow = pi_fine_overflow_w[0];
1737  pi_counter_read_val = pi_counter_read_val_w[0];
1738  pi_phase_locked = pi_phase_locked_w[0];
1739  if ( calib_in_common)
1740  pi_dqs_found = pi_dqs_found_any;
1741  else
1742  pi_dqs_found = pi_dqs_found_w[0];
1743  pi_dqs_out_of_range = pi_dqs_out_of_range_w[0];
1744  end
1745  3'b001: begin
1746  po_coarse_overflow = po_coarse_overflow_w[1];
1747  po_fine_overflow = po_fine_overflow_w[1];
1748  po_counter_read_val = po_counter_read_val_w[1];
1749  pi_fine_overflow = pi_fine_overflow_w[1];
1750  pi_counter_read_val = pi_counter_read_val_w[1];
1751  pi_phase_locked = pi_phase_locked_w[1];
1752  if ( calib_in_common)
1753  pi_dqs_found = pi_dqs_found_any;
1754  else
1755  pi_dqs_found = pi_dqs_found_w[1];
1756  pi_dqs_out_of_range = pi_dqs_out_of_range_w[1];
1757  end
1758  3'b010: begin
1759  po_coarse_overflow = po_coarse_overflow_w[2];
1760  po_fine_overflow = po_fine_overflow_w[2];
1761  po_counter_read_val = po_counter_read_val_w[2];
1762  pi_fine_overflow = pi_fine_overflow_w[2];
1763  pi_counter_read_val = pi_counter_read_val_w[2];
1764  pi_phase_locked = pi_phase_locked_w[2];
1765  if ( calib_in_common)
1766  pi_dqs_found = pi_dqs_found_any;
1767  else
1768  pi_dqs_found = pi_dqs_found_w[2];
1769  pi_dqs_out_of_range = pi_dqs_out_of_range_w[2];
1770  end
1771  default: begin
1772  po_coarse_overflow = 0;
1773  po_fine_overflow = 0;
1774  po_counter_read_val = 0;
1775  pi_fine_overflow = 0;
1776  pi_counter_read_val = 0;
1777  pi_phase_locked = 0;
1778  pi_dqs_found = 0;
1779  pi_dqs_out_of_range = 0;
1780  end
1781  endcase
1782 end
1783 
1784 endmodule // mc_phy
Generated on Wed Apr 18 2018 10:55:27 for AMC13 by   doxygen 1.8.1