AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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mig_7series_v1_9_arb_mux.v
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49 // ____ ____
50 // / /\/ /
51 // /___/ \ / Vendor : Xilinx
52 // \ \ \/ Version : %version
53 // \ \ Application : MIG
54 // / / Filename : arb_mux.v
55 // /___/ /\ Date Last Modified : $date$
56 // \ \ / \ Date Created : Tue Jun 30 2009
57 // \___\/\___\
58 //
59 //Device : 7-Series
60 //Design Name : DDR3 SDRAM
61 //Purpose :
62 //Reference :
63 //Revision History :
64 //*****************************************************************************
65 
66 
67 `timescale 1ps/1ps
68 
69 module mig_7series_v1_9_arb_mux #
70  (
71  parameter TCQ = 100,
72  parameter EVEN_CWL_2T_MODE = "OFF",
73  parameter ADDR_CMD_MODE = "1T",
74  parameter BANK_VECT_INDX = 11,
75  parameter BANK_WIDTH = 3,
76  parameter BURST_MODE = "8",
77  parameter CS_WIDTH = 4,
78  parameter CL = 5,
79  parameter CWL = 5,
80  parameter DATA_BUF_ADDR_VECT_INDX = 31,
81  parameter DATA_BUF_ADDR_WIDTH = 8,
82  parameter DRAM_TYPE = "DDR3",
83  parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal
84  parameter EARLY_WR_DATA_ADDR = "OFF",
85  parameter ECC = "OFF",
86  parameter nBANK_MACHS = 4,
87  parameter nCK_PER_CLK = 2, // # DRAM CKs per fabric CLKs
88  parameter nCS_PER_RANK = 1,
89  parameter nRAS = 37500, // ACT->PRE cmd period (CKs)
90  parameter nRCD = 12500, // ACT->R/W delay (CKs)
91  parameter nSLOTS = 2,
92  parameter nWR = 6, // Write recovery (CKs)
93  parameter RANKS = 1,
94  parameter RANK_VECT_INDX = 15,
95  parameter RANK_WIDTH = 2,
96  parameter ROW_VECT_INDX = 63,
97  parameter ROW_WIDTH = 16,
98  parameter RTT_NOM = "40",
99  parameter RTT_WR = "120",
100  parameter SLOT_0_CONFIG = 8'b0000_0101,
101  parameter SLOT_1_CONFIG = 8'b0000_1010
102  )
103  (/*AUTOARG**/
104  // Outputs
105  output [ROW_WIDTH-1:0] col_a, // From arb_select0 of arb_select.v
106  output [BANK_WIDTH-1:0] col_ba, // From arb_select0 of arb_select.v
107  output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_select0 of arb_select.v
108  output col_periodic_rd, // From arb_select0 of arb_select.v
109  output [RANK_WIDTH-1:0] col_ra, // From arb_select0 of arb_select.v
110  output col_rmw, // From arb_select0 of arb_select.v
111  output col_rd_wr,
112  output [ROW_WIDTH-1:0] col_row, // From arb_select0 of arb_select.v
113  output col_size, // From arb_select0 of arb_select.v
114  output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_select0 of arb_select.v
115  output wire [nCK_PER_CLK-1:0] mc_ras_n,
116  output wire [nCK_PER_CLK-1:0] mc_cas_n,
117  output wire [nCK_PER_CLK-1:0] mc_we_n,
118  output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
119  output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
120  output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
121  output wire [1:0] mc_odt,
122  output wire [nCK_PER_CLK-1:0] mc_cke,
123  output wire [3:0] mc_aux_out0,
124  output wire [3:0] mc_aux_out1,
125  output [2:0] mc_cmd,
126  output [5:0] mc_data_offset,
127  output [5:0] mc_data_offset_1,
128  output [5:0] mc_data_offset_2,
129  output [1:0] mc_cas_slot,
130  output [RANK_WIDTH-1:0] rnk_config, // From arb_select0 of arb_select.v
131  output rnk_config_valid_r, // From arb_row_col0 of arb_row_col.v
132  output [nBANK_MACHS-1:0] sending_row, // From arb_row_col0 of arb_row_col.v
133  output [nBANK_MACHS-1:0] sending_pre,
134  output sent_col, // From arb_row_col0 of arb_row_col.v
135  output sent_col_r, // From arb_row_col0 of arb_row_col.v
136  output sent_row, // From arb_row_col0 of arb_row_col.v
137  output [nBANK_MACHS-1:0] sending_col,
138  output rnk_config_strobe,
139  output insert_maint_r1,
140  output rnk_config_kill_rts_col,
141 
142  // Inputs
143  input clk,
144  input rst,
145  input init_calib_complete,
146  input [6*RANKS-1:0] calib_rddata_offset,
147  input [6*RANKS-1:0] calib_rddata_offset_1,
148  input [6*RANKS-1:0] calib_rddata_offset_2,
149  input [ROW_VECT_INDX:0] col_addr, // To arb_select0 of arb_select.v
150  input [nBANK_MACHS-1:0] col_rdy_wr, // To arb_row_col0 of arb_row_col.v
151  input insert_maint_r, // To arb_row_col0 of arb_row_col.v
152  input [RANK_WIDTH-1:0] maint_rank_r, // To arb_select0 of arb_select.v
153  input maint_zq_r, // To arb_select0 of arb_select.v
154  input maint_sre_r, // To arb_select0 of arb_select.v
155  input maint_srx_r, // To arb_select0 of arb_select.v
156  input [nBANK_MACHS-1:0] rd_wr_r, // To arb_select0 of arb_select.v
157  input [BANK_VECT_INDX:0] req_bank_r, // To arb_select0 of arb_select.v
158  input [nBANK_MACHS-1:0] req_cas, // To arb_select0 of arb_select.v
159  input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,// To arb_select0 of arb_select.v
160  input [nBANK_MACHS-1:0] req_periodic_rd_r, // To arb_select0 of arb_select.v
161  input [RANK_VECT_INDX:0] req_rank_r, // To arb_select0 of arb_select.v
162  input [nBANK_MACHS-1:0] req_ras, // To arb_select0 of arb_select.v
163  input [ROW_VECT_INDX:0] req_row_r, // To arb_select0 of arb_select.v
164  input [nBANK_MACHS-1:0] req_size_r, // To arb_select0 of arb_select.v
165  input [nBANK_MACHS-1:0] req_wr_r, // To arb_select0 of arb_select.v
166  input [ROW_VECT_INDX:0] row_addr, // To arb_select0 of arb_select.v
167  input [nBANK_MACHS-1:0] row_cmd_wr, // To arb_select0 of arb_select.v
168  input [nBANK_MACHS-1:0] rtc, // To arb_row_col0 of arb_row_col.v
169  input [nBANK_MACHS-1:0] rts_col, // To arb_row_col0 of arb_row_col.v
170  input [nBANK_MACHS-1:0] rts_row, // To arb_row_col0 of arb_row_col.v
171  input [nBANK_MACHS-1:0] rts_pre, // To arb_row_col0 of arb_row_col.v
172  input [7:0] slot_0_present, // To arb_select0 of arb_select.v
173  input [7:0] slot_1_present // To arb_select0 of arb_select.v
174 
175  );
176 
177  /*AUTOINPUT**/
178  // Beginning of automatic inputs (from unused autoinst inputs)
179  // End of automatics
180 
181  /*AUTOOUTPUT**/
182  // Beginning of automatic outputs (from unused autoinst outputs)
183 
184  // End of automatics
185 
186  /*AUTOWIRE**/
187  // Beginning of automatic wires (for undeclared instantiated-module outputs)
188  wire cs_en0; // From arb_row_col0 of arb_row_col.v
189  wire cs_en1; // From arb_row_col0 of arb_row_col.v
190  wire [nBANK_MACHS-1:0] grant_col_r; // From arb_row_col0 of arb_row_col.v
191  wire [nBANK_MACHS-1:0] grant_col_wr; // From arb_row_col0 of arb_row_col.v
192  wire [nBANK_MACHS-1:0] grant_config_r; // From arb_row_col0 of arb_row_col.v
193  wire [nBANK_MACHS-1:0] grant_row_r; // From arb_row_col0 of arb_row_col.v
194  wire [nBANK_MACHS-1:0] grant_pre_r; // From arb_row_col0 of arb_row_col.v
195  wire send_cmd0_row; // From arb_row_col0 of arb_row_col.v
196  wire send_cmd0_col; // From arb_row_col0 of arb_row_col.v
197  wire send_cmd1_row; // From arb_row_col0 of arb_row_col.v
198  wire send_cmd1_col;
199  wire send_cmd2_row;
200  wire send_cmd2_col;
201  wire send_cmd2_pre;
202  wire send_cmd3_col;
203  wire [5:0] col_channel_offset;
204  // End of automatics
205 
206  wire sent_col_i;
207 
208  assign sent_col = sent_col_i;
209 
210  mig_7series_v1_9_arb_row_col #
211  (/*AUTOINSTPARAM**/
212  // Parameters
213  .TCQ (TCQ),
214  .ADDR_CMD_MODE (ADDR_CMD_MODE),
215  .CWL (CWL),
216  .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
217  .nBANK_MACHS (nBANK_MACHS),
218  .nCK_PER_CLK (nCK_PER_CLK),
219  .nRAS (nRAS),
220  .nRCD (nRCD),
221  .nWR (nWR))
222  arb_row_col0
223  (/*AUTOINST**/
224  // Outputs
225  .grant_row_r (grant_row_r[nBANK_MACHS-1:0]),
226  .grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]),
227  .sent_row (sent_row),
228  .sending_row (sending_row[nBANK_MACHS-1:0]),
229  .sending_pre (sending_pre[nBANK_MACHS-1:0]),
230  .grant_config_r (grant_config_r[nBANK_MACHS-1:0]),
231  .rnk_config_strobe (rnk_config_strobe),
232  .rnk_config_kill_rts_col (rnk_config_kill_rts_col),
233  .rnk_config_valid_r (rnk_config_valid_r),
234  .grant_col_r (grant_col_r[nBANK_MACHS-1:0]),
235  .sending_col (sending_col[nBANK_MACHS-1:0]),
236  .sent_col (sent_col_i),
237  .sent_col_r (sent_col_r),
238  .grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]),
239  .send_cmd0_row (send_cmd0_row),
240  .send_cmd0_col (send_cmd0_col),
241  .send_cmd1_row (send_cmd1_row),
242  .send_cmd1_col (send_cmd1_col),
243  .send_cmd2_row (send_cmd2_row),
244  .send_cmd2_col (send_cmd2_col),
245  .send_cmd2_pre (send_cmd2_pre),
246  .send_cmd3_col (send_cmd3_col),
247  .col_channel_offset (col_channel_offset),
248  .cs_en0 (cs_en0),
249  .cs_en1 (cs_en1),
250  .cs_en2 (cs_en2),
251  .cs_en3 (cs_en3),
252  .insert_maint_r1 (insert_maint_r1),
253  // Inputs
254  .clk (clk),
255  .rst (rst),
256  .rts_row (rts_row[nBANK_MACHS-1:0]),
257  .rts_pre (rts_pre[nBANK_MACHS-1:0]),
258  .insert_maint_r (insert_maint_r),
259  .rts_col (rts_col[nBANK_MACHS-1:0]),
260  .rtc (rtc[nBANK_MACHS-1:0]),
261  .col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]));
262 
263  mig_7series_v1_9_arb_select #
264  (/*AUTOINSTPARAM**/
265  // Parameters
266  .TCQ (TCQ),
267  .EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),
268  .ADDR_CMD_MODE (ADDR_CMD_MODE),
269  .BANK_VECT_INDX (BANK_VECT_INDX),
270  .BANK_WIDTH (BANK_WIDTH),
271  .BURST_MODE (BURST_MODE),
272  .CS_WIDTH (CS_WIDTH),
273  .CL (CL),
274  .CWL (CWL),
275  .DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX),
276  .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
277  .DRAM_TYPE (DRAM_TYPE),
278  .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
279  .ECC (ECC),
280  .CKE_ODT_AUX (CKE_ODT_AUX),
281  .nBANK_MACHS (nBANK_MACHS),
282  .nCK_PER_CLK (nCK_PER_CLK),
283  .nCS_PER_RANK (nCS_PER_RANK),
284  .nSLOTS (nSLOTS),
285  .RANKS (RANKS),
286  .RANK_VECT_INDX (RANK_VECT_INDX),
287  .RANK_WIDTH (RANK_WIDTH),
288  .ROW_VECT_INDX (ROW_VECT_INDX),
289  .ROW_WIDTH (ROW_WIDTH),
290  .RTT_NOM (RTT_NOM),
291  .RTT_WR (RTT_WR),
292  .SLOT_0_CONFIG (SLOT_0_CONFIG),
293  .SLOT_1_CONFIG (SLOT_1_CONFIG))
294  arb_select0
295  (/*AUTOINST**/
296  // Outputs
297  .col_periodic_rd (col_periodic_rd),
298  .col_ra (col_ra[RANK_WIDTH-1:0]),
299  .col_ba (col_ba[BANK_WIDTH-1:0]),
300  .col_a (col_a[ROW_WIDTH-1:0]),
301  .col_rmw (col_rmw),
302  .col_rd_wr (col_rd_wr),
303  .col_size (col_size),
304  .col_row (col_row[ROW_WIDTH-1:0]),
305  .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
306  .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
307  .mc_bank (mc_bank),
308  .mc_address (mc_address),
309  .mc_ras_n (mc_ras_n),
310  .mc_cas_n (mc_cas_n),
311  .mc_we_n (mc_we_n),
312  .mc_cs_n (mc_cs_n),
313  .mc_odt (mc_odt),
314  .mc_cke (mc_cke),
315  .mc_aux_out0 (mc_aux_out0),
316  .mc_aux_out1 (mc_aux_out1),
317  .mc_cmd (mc_cmd),
318  .mc_data_offset (mc_data_offset),
319  .mc_data_offset_1 (mc_data_offset_1),
320  .mc_data_offset_2 (mc_data_offset_2),
321  .mc_cas_slot (mc_cas_slot),
322  .col_channel_offset (col_channel_offset),
323  .rnk_config (rnk_config),
324  // Inputs
325  .clk (clk),
326  .rst (rst),
327  .init_calib_complete (init_calib_complete),
328  .calib_rddata_offset (calib_rddata_offset),
329  .calib_rddata_offset_1 (calib_rddata_offset_1),
330  .calib_rddata_offset_2 (calib_rddata_offset_2),
331  .req_rank_r (req_rank_r[RANK_VECT_INDX:0]),
332  .req_bank_r (req_bank_r[BANK_VECT_INDX:0]),
333  .req_ras (req_ras[nBANK_MACHS-1:0]),
334  .req_cas (req_cas[nBANK_MACHS-1:0]),
335  .req_wr_r (req_wr_r[nBANK_MACHS-1:0]),
336  .grant_row_r (grant_row_r[nBANK_MACHS-1:0]),
337  .grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]),
338  .row_addr (row_addr[ROW_VECT_INDX:0]),
339  .row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]),
340  .insert_maint_r1 (insert_maint_r1),
341  .maint_zq_r (maint_zq_r),
342  .maint_sre_r (maint_sre_r),
343  .maint_srx_r (maint_srx_r),
344  .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
345  .req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]),
346  .req_size_r (req_size_r[nBANK_MACHS-1:0]),
347  .rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]),
348  .req_row_r (req_row_r[ROW_VECT_INDX:0]),
349  .col_addr (col_addr[ROW_VECT_INDX:0]),
350  .req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]),
351  .grant_col_r (grant_col_r[nBANK_MACHS-1:0]),
352  .grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]),
353  .send_cmd0_row (send_cmd0_row),
354  .send_cmd0_col (send_cmd0_col),
355  .send_cmd1_row (send_cmd1_row),
356  .send_cmd1_col (send_cmd1_col),
357  .send_cmd2_row (send_cmd2_row),
358  .send_cmd2_col (send_cmd2_col),
359  .send_cmd2_pre (send_cmd2_pre),
360  .send_cmd3_col (send_cmd3_col),
361  .sent_col (EVEN_CWL_2T_MODE == "ON" ? sent_col_r : sent_col),
362  .cs_en0 (cs_en0),
363  .cs_en1 (cs_en1),
364  .cs_en2 (cs_en2),
365  .cs_en3 (cs_en3),
366  .grant_config_r (grant_config_r[nBANK_MACHS-1:0]),
367  .rnk_config_strobe (rnk_config_strobe),
368  .slot_0_present (slot_0_present[7:0]),
369  .slot_1_present (slot_1_present[7:0]));
370 
371 endmodule
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