AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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fake_event.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 13:09:26 05/16/2012
6 -- Design Name:
7 -- Module Name: fake_event - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 --use IEEE.NUMERIC_STD.ALL;
29 
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 library UNISIM;
33 use UNISIM.VComponents.all;
34 Library UNIMACRO;
35 use UNIMACRO.vcomponents.all;
36 
37 entity fake_event is
38  Port (
39  sysclk : in STD_LOGIC;
40  UsrClk : in STD_LOGIC;
41  reset : in STD_LOGIC;
42  fifo_rst : in STD_LOGIC;
43  fifo_en : in STD_LOGIC;
44  fake_en : in STD_LOGIC;
45  sync : in STD_LOGIC;
46  ovfl_warning : in STD_LOGIC;
47  fake_length : in std_logic_vector(19 downto 0); -- in 64 bit words
48  LinkFull : in STD_LOGIC;
49  L1A_DATA : in std_logic_vector(15 downto 0);
50  L1A_WrEn : in std_logic;
51  fake_header : out STD_LOGIC;
52  fake_CRC : out STD_LOGIC;
53  empty_event_flag : out STD_LOGIC;
54  fake_DATA : out STD_LOGIC_VECTOR (15 downto 0);
55  fake_WrEn : out STD_LOGIC
56  );
57 end fake_event;
58 
59 architecture Behavioral of fake_event is
60 signal L1A_infoDo : std_logic_vector(15 downto 0) := (others => '0');
61 signal L1A_info_RdEn : std_logic := '0';
62 signal L1A_info_WrEn : std_logic := '0';
63 signal L1A_info_Empty : std_logic := '0';
64 signal L1A_info_avl : std_logic_vector(2 downto 0) := (others => '0');
65 signal ovfl_warning_sync : std_logic_vector(3 downto 0) := (others =>'0');
66 signal fake_WrEn_i : std_logic := '0';
67 signal bld_event : std_logic := '0';
68 signal AMC_header : std_logic := '0';
69 signal data_header : std_logic := '0';
70 signal data_trailer : std_logic := '0';
71 signal data_trailer_dl : std_logic := '0';
72 signal evn_LSB : std_logic_vector(7 downto 0) := (others => '0');
73 signal data_wc : std_logic_vector(19 downto 0) := (others => '0');
74 signal wc2send : std_logic_vector(21 downto 0) := (others => '0');
75 signal last_word : std_logic := '0';
76 signal last_byte : std_logic := '0';
77 signal event_length : std_logic_vector(19 downto 0) := (others => '0');
78 signal ec_data_wc : std_logic := '0';
79 signal RDCOUNT : std_logic_vector(9 downto 0) := (others => '0');
80 signal WRCOUNT : std_logic_vector(9 downto 0) := (others => '0');
81 signal fake_CRC_i : std_logic := '0';
82 begin
83 fake_WrEn <= fake_WrEn_i;
84 fake_CRC <= fake_CRC_i;
85 i_L1A_info : FIFO_DUALCLOCK_MACRO
86  generic map (
87  DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"
88  ALMOST_FULL_OFFSET => X"0080", -- Sets almost full threshold
89  ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold
90  DATA_WIDTH => 16, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
91  FIFO_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
92  FIRST_WORD_FALL_THROUGH => TRUE) -- Sets the FIFO FWFT to TRUE or FALSE
93  port map (
94  ALMOSTEMPTY => open, -- 1-bit output almost empty
95  ALMOSTFULL => open, -- 1-bit output almost full
96  DO => L1A_infoDo, -- Output data, width defined by DATA_WIDTH parameter
97  EMPTY => L1A_info_Empty, -- 1-bit output empty
98  FULL => open, -- 1-bit output full
99  RDCOUNT => RDCOUNT, -- Output read count, width determined by FIFO depth
100  RDERR => open, -- 1-bit output read error
101  WRCOUNT => WRCOUNT, -- Output write count, width determined by FIFO depth
102  WRERR => open, -- 1-bit output write error
103  DI => L1A_Data, -- Input data, width defined by DATA_WIDTH parameter
104  RDCLK => UsrClk, -- 1-bit input read clock
105  RDEN => L1A_info_RdEn, -- 1-bit input read enable
106  RST => fifo_rst, -- 1-bit input reset
107  WRCLK => sysclk, -- 1-bit input write clock
108  WREN => L1A_info_WrEn -- 1-bit input write enable
109  );
110 L1A_info_WrEn <= fake_en and fifo_en and L1A_WrEn;
111 i_data_trailer_dl : SRL16E
112  port map (
113  Q => data_trailer_dl, -- SRL data output
114  A0 => '1', -- Select[0] input
115  A1 => '1', -- Select[1] input
116  A2 => '1', -- Select[2] input
117  A3 => '0', -- Select[3] input
118  CE => '1', -- Clock enable input
119  CLK => UsrClk, -- Clock input
120  D => data_trailer -- SRL data input
121  );
122 process(UsrClk)
123 begin
124  if(UsrClk'event and UsrClk = '1')then
125  ovfl_warning_sync <= ovfl_warning_sync(2 downto 0) & ovfl_warning;
126  if(data_header = '1')then
127  empty_event_flag <= ovfl_warning_sync(3);
128  if(ovfl_warning_sync(3) = '1')then
129  event_length <= x"00003";
130  elsif(and_reduce(fake_length(19 downto 2)) = '1')then
131  event_length <= x"fffff";
132  else
133  event_length <= fake_length + 3;
134  end if;
135  end if;
136  if(ec_data_wc = '0' and AMC_header = '1')then
137  wc2send(21 downto 2) <= event_length - 1;
138  wc2send(1 downto 0) <= "10";
139  elsif(ec_data_wc = '1')then
140  wc2send <= wc2send - 1;
141  end if;
142  fake_header <= not reset and AMC_header and data_wc(1) and data_wc(0);
143  fake_CRC_i <= data_trailer;
144  if(AMC_header = '1')then
145  if(data_wc(2 downto 0) = "000")then
146  fake_DATA <= event_length(15 downto 0);
147  elsif(data_wc(2 downto 0) = "001")then
148  fake_DATA <= L1A_infoDo(15 downto 4) & event_length(19 downto 16);
149  elsif(data_wc(2 downto 0) = "010")then
150  fake_DATA <= L1A_infoDo;
151  evn_LSB <= L1A_infoDo(7 downto 0);
152  elsif(data_wc(2 downto 0) = "011")then
153  fake_DATA <= x"00" & L1A_infoDo(7 downto 0);
154  else
155  fake_DATA <= x"0000";
156  end if;
157  elsif(L1A_info_RdEn = '1')then
158  fake_DATA <= L1A_infoDo;
159  elsif(last_word = '1' and wc2send(1) = '1')then
160  fake_DATA <= event_length(15 downto 0);
161  elsif(last_word = '1' and wc2send(0) = '1')then
162  fake_DATA <= evn_LSB & x"0" & event_length(19 downto 16);
163  else
164  fake_DATA <= data_wc(15 downto 0);
165  end if;
166  end if;
167 end process;
168 process(UsrClk,reset)
169 begin
170  if(reset = '1')then
171  L1A_info_avl <= (others => '0');
172  bld_event <= '0';
173  ec_data_wc <= '0';
174  AMC_header <= '0';
175  L1A_info_RdEn <= '0';
176  data_header <= '1';
177  data_trailer <= '0';
178  data_wc <= (others => '0');
179  fake_WrEn_i <= '0';
180  elsif(UsrClk'event and UsrClk = '1')then
181  if(L1A_info_empty = '1')then
182  L1A_info_avl <= (others => '0');
183  elsif(L1A_info_avl(2) = '0')then
184  L1A_info_avl <= L1A_info_avl + 1;
185  end if;
186  if(last_word = '1')then
187  bld_event <= '0';
188  elsif(AMC_header = '1')then
189  bld_event <= '1';
190  end if;
191  if(last_word = '1' and wc2send(1 downto 0) = "00")then
192  last_byte <= '1';
193  else
194  last_byte <= '0';
195  end if;
196  if(AMC_header = '1' or last_word = '1' or (data_wc(1 downto 0) = "00" and bld_event = '1' and LinkFull = '0'))then
197  ec_data_wc <= '1';
198  elsif(last_byte = '1' or (data_wc(1 downto 0) = "11" and (bld_event = '0' or LinkFull = '1')))then
199  ec_data_wc <= '0';
200  end if;
201  if(data_trailer_dl = '1')then
202  data_header <= '1';
203  elsif(ec_data_wc = '1')then
204  data_header <= '0';
205  end if;
206  if(LinkFull = '0' and L1A_info_avl(2) = '1' and data_header = '1' and sync = '1')then
207  AMC_header <= '1';
208  elsif(data_wc(2) = '1')then
209  AMC_header <= '0';
210  end if;
211  if(fifo_en = '0' or AMC_header = '0' or ec_data_wc = '0' or data_wc(1 downto 0) = "11")then
212  L1A_info_RdEn <= '0';
213  else
214  L1A_info_RdEn <= '1';
215  end if;
216  if(bld_event = '0')then
217  data_wc <= (others => '0');
218  elsif(ec_data_wc = '1')then
219  data_wc <= data_wc + 1;
220  end if;
221  if(data_header = '0' and or_reduce(wc2send(21 downto 2)) = '0' and wc2send(1 downto 0) /= "00")then
222  last_word <= '1';
223  else
224  last_word <= '0';
225  end if;
226  if(last_word = '1' and wc2send(0) = '1' and ec_data_wc = '1')then
227  data_trailer <= '1';
228  else
229  data_trailer <= '0';
230  end if;
231  fake_WrEn_i <= ec_data_wc;
232  end if;
233 end process;
234 end Behavioral;
235 
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