AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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mig_7series_v1_9_memc_ui_top_std Member List

This is the complete list of members for mig_7series_v1_9_memc_ui_top_std, including all inherited members.

TCQ (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
PAYLOAD_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ADDR_CMD_MODE (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
AL (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
BANK_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
BM_CNT_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
BURST_MODE (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
BURST_TYPE (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CA_MIRROR (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CK_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA_CTL_B0 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA_CTL_B1 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA_CTL_B2 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA_CTL_B3 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA_CTL_B4 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
BYTE_LANES_B0 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
BYTE_LANES_B1 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
BYTE_LANES_B2 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
BYTE_LANES_B3 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
BYTE_LANES_B4 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
PHY_0_BITLANES (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
PHY_1_BITLANES (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
PHY_2_BITLANES (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CK_BYTE_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ADDR_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
BANK_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CAS_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CKE_ODT_BYTE_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CKE_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ODT_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CKE_ODT_AUX (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CS_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
PARITY_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
RAS_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
WE_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DQS_BYTE_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA0_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA1_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA2_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA3_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA4_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA5_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA6_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA7_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA8_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA9_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA10_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA11_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA12_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA13_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA14_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA15_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA16_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA17_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
MASK0_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
MASK1_MAP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CALIB_ROW_ADD (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CALIB_COL_ADD (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CALIB_BA_ADD (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CL (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
COL_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CMD_PIPE_PLUS1 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CS_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CKE_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CWL (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA_BUF_ADDR_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA_BUF_OFFSET_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DDR2_DQSN_ENABLE (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DM_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DQ_CNT_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DQ_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DQS_CNT_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DQS_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DRAM_TYPE (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DRAM_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ECC (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ECC_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
MC_ERR_ADDR_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
nAL (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
nBANK_MACHS (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
PRE_REV3ES (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
nCK_PER_CLK (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
nCS_PER_RANK (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
PHYCTL_CMD_FIFO (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ORDERING (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
PHASE_DETECT (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
IBUF_LPWR_MODE (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
IODELAY_HP_MODE (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
BANK_TYPE (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA_IO_PRIM_TYPE (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DATA_IO_IDLE_PWRDWN (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
IODELAY_GRP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
OUTPUT_DRV (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
REG_CTRL (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
RTT_NOM (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
RTT_WR (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
STARVE_LIMIT (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
tCK (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
tCKE (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
tFAW (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
tPRDI (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
tRAS (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
tRCD (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
tREFI (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
tRFC (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
tRP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
tRRD (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
tRTP (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
tWTR (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
tZQI (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
tZQCS (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
WRLVL (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DEBUG_PORT (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CAL_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
RANK_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
RANKS (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ODT_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ROW_WIDTH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
SLOT_0_CONFIG (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
SLOT_1_CONFIG (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
SIM_BYPASS_INIT_CAL (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
REFCLK_FREQ (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
nDQS_COL0 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
nDQS_COL1 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
nDQS_COL2 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
nDQS_COL3 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DQS_LOC_COL0 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DQS_LOC_COL1 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DQS_LOC_COL2 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
DQS_LOC_COL3 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
USE_CS_PORT (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
USE_DM_PORT (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
USE_ODT_PORT (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
MASTER_PHY_CTL (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
USER_REFRESH (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
TEMP_MON_EN (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
clk_ref (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
freq_refclk (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mem_refclk (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
pll_lock (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
sync_pulse (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
error (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
reset (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
rst_tg_mc (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
bank (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
clk (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
cmd (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
col (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
correct_en (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
data_buf_addr (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_idel_down_all (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_idel_down_cpt (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_idel_up_all (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_idel_up_cpt (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_sel_all_idel_cpt (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_sel_idel_cpt (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
hi_priority (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
rank (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
raw_not_ecc (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
row (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
rst (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
size (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
slot_0_present (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
slot_1_present (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
use_addr (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
wr_data (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
wr_data_mask (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
accept (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
accept_ns (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
bank_mach_next (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
app_sr_req (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
app_sr_active (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
app_ref_req (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
app_ref_ack (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
app_zq_req (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
app_zq_ack (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_calib_top (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_cpt_first_edge_cnt (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_cpt_second_edge_cnt (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_phy_rdlvl (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_phy_wrcal (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_final_po_fine_tap_cnt (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_final_po_coarse_tap_cnt (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_rd_data_edge_detect (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_rddata (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_rdlvl_done (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_rdlvl_err (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_rdlvl_start (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_tap_cnt_during_wrlvl (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_wl_edge_detect_valid (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_wrlvl_done (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_wrlvl_err (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_wrlvl_start (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ddr_addr (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ddr_ba (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ddr_cas_n (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ddr_ck_n (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ddr_ck (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ddr_cke (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ddr_cs_n (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ddr_dm (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ddr_odt (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ddr_ras_n (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ddr_reset_n (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ddr_parity (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ddr_we_n (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
init_calib_complete (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
init_wrcal_complete (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ecc_err_addr (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ecc_multiple (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ecc_single (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
rd_data (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
rd_data_addr (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
rd_data_en (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
rd_data_end (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
rd_data_offset (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
wr_data_addr (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
wr_data_en (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
wr_data_offset (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ddr_dq (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ddr_dqs_n (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ddr_dqs (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
device_temp (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_sel_pi_incdec (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_sel_po_incdec (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_byte_sel (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_pi_f_inc (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_pi_f_dec (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_po_f_inc (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_po_f_stg23_sel (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_po_f_dec (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_cpt_tap_cnt (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_dq_idelay_tap_cnt (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_rddata_valid (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_wrlvl_fine_tap_cnt (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_wrlvl_coarse_tap_cnt (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_phy_wrlvl (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_pi_counter_read_val (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_po_counter_read_val (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
ref_dll_lock (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
rst_phaser_ref (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_rd_data_offset (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_phy_init (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_prbs_rdlvl (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_dqs_found_cal (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_pi_phaselock_start (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_pi_phaselocked_done (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_pi_phaselock_err (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_pi_dqsfound_start (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_pi_dqsfound_done (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_pi_dqsfound_err (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_wrcal_start (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_wrcal_done (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_wrcal_err (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_pi_dqs_found_lanes_phy4lanes (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_pi_phase_locked_phy4lanes (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_calib_rd_data_offset_1 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_calib_rd_data_offset_2 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_data_offset (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_data_offset_1 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_data_offset_2 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_oclkdelay_calib_start (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_oclkdelay_calib_done (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_phy_oclkdelay_cal (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
dbg_oclkdelay_rd_data (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
nSLOTS (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
SLOT_0_CONFIG_MC (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
SLOT_1_CONFIG_MC (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
slot_0_present_mc (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
slot_1_present_mc (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
user_periodic_rd_req (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
user_ref_req (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
user_zq_req (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_ras_n (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_cas_n (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_we_n (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_address (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_bank (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_cke (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_odt (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_cs_n (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_reset_n (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_wrdata (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_wrdata_mask (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_wrdata_en (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_ref_zq_wip (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
tempmon_sample_en (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
idle (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_cmd_wren (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_ctl_wren (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_cmd (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_cas_slot (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_data_offset (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_data_offset_1 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_data_offset_2 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_aux_out0 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_aux_out1 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mc_rank_cnt (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
phy_mc_ctl_full (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
phy_mc_cmd_full (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
phy_mc_data_full (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
phy_rd_data (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
phy_rddata_valid (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
calib_rd_data_offset_0 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
calib_rd_data_offset_1 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
calib_rd_data_offset_2 (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
init_calib_complete_w (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
init_wrcal_complete_w (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mux_rst (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CWL_T (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
CLK_PERIOD (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
nCL (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
nCWL (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
TCQ (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
PAYLOAD_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ADDR_CMD_MODE (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
AL (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
BANK_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
BM_CNT_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
BURST_MODE (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
BURST_TYPE (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CA_MIRROR (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CK_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CL (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
COL_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CMD_PIPE_PLUS1 (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CS_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CKE_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CWL (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA_BUF_ADDR_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA_BUF_OFFSET_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DDR2_DQSN_ENABLE (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DM_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DQ_CNT_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DQ_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DQS_CNT_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DQS_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DRAM_TYPE (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DRAM_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ECC (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ECC_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ECC_TEST (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
MC_ERR_ADDR_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
MASTER_PHY_CTL (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
nAL (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
nBANK_MACHS (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
nCK_PER_CLK (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
nCS_PER_RANK (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ORDERING (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
IBUF_LPWR_MODE (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
IODELAY_HP_MODE (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
BANK_TYPE (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA_IO_PRIM_TYPE (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA_IO_IDLE_PWRDWN (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
IODELAY_GRP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
OUTPUT_DRV (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
REG_CTRL (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
RTT_NOM (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
RTT_WR (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
STARVE_LIMIT (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
tCK (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
tCKE (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
tFAW (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
tPRDI (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
tRAS (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
tRCD (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
tREFI (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
tRFC (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
tRP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
tRRD (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
tRTP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
tWTR (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
tZQI (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
tZQCS (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
USER_REFRESH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
TEMP_MON_EN (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
WRLVL (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DEBUG_PORT (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CAL_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
RANK_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
RANKS (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ODT_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ROW_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ADDR_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
APP_MASK_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
APP_DATA_WIDTH (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
BYTE_LANES_B0 (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
BYTE_LANES_B1 (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
BYTE_LANES_B2 (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
BYTE_LANES_B3 (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
BYTE_LANES_B4 (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA_CTL_B0 (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA_CTL_B1 (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA_CTL_B2 (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA_CTL_B3 (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA_CTL_B4 (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
PHY_0_BITLANES (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
PHY_1_BITLANES (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
PHY_2_BITLANES (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CK_BYTE_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ADDR_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
BANK_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CAS_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CKE_ODT_BYTE_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CKE_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ODT_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CKE_ODT_AUX (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CS_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
PARITY_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
RAS_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
WE_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DQS_BYTE_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA0_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA1_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA2_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA3_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA4_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA5_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA6_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA7_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA8_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA9_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA10_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA11_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA12_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA13_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA14_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA15_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA16_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
DATA17_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
MASK0_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
MASK1_MAP (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
SLOT_0_CONFIG (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
SLOT_1_CONFIG (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
MEM_ADDR_ORDER (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CALIB_ROW_ADD (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CALIB_COL_ADD (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
CALIB_BA_ADD (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
SIM_BYPASS_INIT_CAL (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
REFCLK_FREQ (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
USE_CS_PORT (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
USE_DM_PORT (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
USE_ODT_PORT (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
clk (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
clk_ref (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
mem_refclk (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
freq_refclk (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
pll_lock (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
sync_pulse (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
rst (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ddr_dq (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ddr_dqs_n (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ddr_dqs (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ddr_addr (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ddr_ba (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ddr_cas_n (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ddr_ck_n (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ddr_ck (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ddr_cke (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ddr_cs_n (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ddr_dm (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ddr_odt (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ddr_ras_n (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ddr_reset_n (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ddr_parity (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ddr_we_n (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
bank_mach_next (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_addr (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_cmd (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_en (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_hi_pri (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_wdf_data (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_wdf_end (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_wdf_mask (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_wdf_wren (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_correct_en_i (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_raw_not_ecc (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_ecc_multiple_err (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_rd_data (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_rd_data_end (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_rd_data_valid (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_rdy (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_wdf_rdy (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_sr_req (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_sr_active (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_ref_req (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_ref_ack (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_zq_req (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_zq_ack (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
device_temp (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_idel_down_all (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_idel_down_cpt (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_idel_up_all (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_idel_up_cpt (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_sel_all_idel_cpt (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_sel_idel_cpt (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_cpt_first_edge_cnt (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_cpt_second_edge_cnt (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_rd_data_edge_detect (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_rddata (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_rdlvl_done (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_rdlvl_err (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_rdlvl_start (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_tap_cnt_during_wrlvl (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_wl_edge_detect_valid (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_wrlvl_done (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_wrlvl_err (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_wrlvl_start (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_final_po_fine_tap_cnt (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_final_po_coarse_tap_cnt (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
init_calib_complete (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_sel_pi_incdec (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_sel_po_incdec (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_byte_sel (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_pi_f_inc (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_pi_f_dec (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_po_f_inc (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_po_f_stg23_sel (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_po_f_dec (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_cpt_tap_cnt (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_dq_idelay_tap_cnt (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_rddata_valid (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_wrlvl_fine_tap_cnt (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_wrlvl_coarse_tap_cnt (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ref_dll_lock (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
rst_phaser_ref (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_rd_data_offset (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_calib_top (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_phy_wrlvl (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_phy_rdlvl (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_phy_wrcal (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_phy_init (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_prbs_rdlvl (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_dqs_found_cal (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_pi_counter_read_val (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_po_counter_read_val (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_pi_phaselock_start (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_pi_phaselocked_done (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_pi_phaselock_err (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_pi_dqsfound_start (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_pi_dqsfound_done (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_pi_dqsfound_err (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_wrcal_start (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_wrcal_done (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_wrcal_err (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_pi_dqs_found_lanes_phy4lanes (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_pi_phase_locked_phy4lanes (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_calib_rd_data_offset_1 (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_calib_rd_data_offset_2 (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_data_offset (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_data_offset_1 (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_data_offset_2 (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_oclkdelay_calib_start (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_oclkdelay_calib_done (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_phy_oclkdelay_cal (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
dbg_oclkdelay_rd_data (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
correct_en (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
raw_not_ecc (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ecc_single (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ecc_multiple (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
ecc_err_addr (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
wr_data_offset (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
wr_data_en (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
wr_data_addr (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
rd_data_offset (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
rd_data_en (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
rd_data_addr (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
accept (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
accept_ns (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
rd_data (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
rd_data_end (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
use_addr (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
size (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
row (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
rank (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
hi_priority (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
data_buf_addr (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
col (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
cmd (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
bank (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
wr_data (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
wr_data_mask (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_sr_req_i (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_sr_active_i (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_ref_req_i (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_ref_ack_i (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_zq_req_i (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
app_zq_ack_i (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
rst_tg_mc (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
error (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
init_wrcal_complete (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
TCQ (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
APP_DATA_WIDTH (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
APP_MASK_WIDTH (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
BANK_WIDTH (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
COL_WIDTH (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
CWL (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
DATA_BUF_ADDR_WIDTH (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
ECC (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
ECC_TEST (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
ORDERING (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
nCK_PER_CLK (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
RANKS (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
REG_CTRL (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
RANK_WIDTH (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
ROW_WIDTH (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
MEM_ADDR_ORDER (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
accept (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
ADDR_WIDTH (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
CWL_M (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_correct_en (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
correct_en (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_sr_req (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
sr_req (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
sr_active (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_sr_active (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_ref_req (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
ref_req (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
ref_ack (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_ref_ack (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_zq_req (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
zq_req (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
zq_ack (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_zq_ack (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
accept_ns (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_addr (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_cmd (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_en (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_hi_pri (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_raw_not_ecc (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_sz (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_wdf_data (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_wdf_end (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_wdf_mask (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_wdf_wren (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
clk (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
ecc_multiple (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
rd_data (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
rd_data_addr (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
rd_data_en (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
rd_data_end (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
rd_data_offset (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
rst (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
wr_data_addr (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
wr_data_en (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
wr_data_offset (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_ecc_multiple_err (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_rd_data (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_rd_data_end (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_rd_data_valid (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_rdy (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
app_wdf_rdy (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
bank (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
cmd (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
col (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
data_buf_addr (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
hi_priority (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
rank (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
raw_not_ecc (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
row (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
size (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
use_addr (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
wr_data (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
wr_data_mask (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
ram_init_addr (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
ram_init_done_r (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
rd_accepted (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
rd_buf_full (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
rd_data_buf_addr_r (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
wr_accepted (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
wr_data_buf_addr (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
wr_req_16 (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
mig_7series_v1_9_mc (defined in mig_7series_v1_9_mem_intfc)mig_7series_v1_9_mem_intfcClass
mig_7series_v1_9_mem_intfc (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
mig_7series_v1_9_ui_cmd (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
mig_7series_v1_9_ui_rd_data (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
mig_7series_v1_9_ui_top (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
mig_7series_v1_9_ui_wr_data (defined in mig_7series_v1_9_ui_top)mig_7series_v1_9_ui_topClass
PROCESS_487clk (defined in mig_7series_v1_9_memc_ui_top_std)mig_7series_v1_9_memc_ui_top_stdClass
RAM32M (defined in mig_7series_v1_9_ui_wr_data)mig_7series_v1_9_ui_wr_dataClass
RAM32M (defined in mig_7series_v1_9_ui_rd_data)mig_7series_v1_9_ui_rd_dataClass