AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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mig_7series_v1_9_ddr_phy_init Member List

This is the complete list of members for mig_7series_v1_9_ddr_phy_init, including all inherited members.

TCQ (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
nCK_PER_CLK (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
CLK_PERIOD (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
USE_ODT_PORT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PRBS_WIDTH (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
BANK_WIDTH (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
CA_MIRROR (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
COL_WIDTH (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
nCS_PER_RANK (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
DQ_WIDTH (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
DQS_WIDTH (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
DQS_CNT_WIDTH (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
ROW_WIDTH (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
CS_WIDTH (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
RANKS (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
CKE_WIDTH (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
DRAM_TYPE (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
REG_CTRL (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
ADDR_CMD_MODE (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
CALIB_ROW_ADD (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
CALIB_COL_ADD (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
CALIB_BA_ADD (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
AL (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
BURST_MODE (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
BURST_TYPE (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
nCL (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
nCWL (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
tRFC (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
OUTPUT_DRV (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
RTT_NOM (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
RTT_WR (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
WRLVL (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
DDR2_DQSN_ENABLE (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
nSLOTS (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
SIM_INIT_OPTION (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
SIM_CAL_OPTION (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
CKE_ODT_AUX (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PRE_REV3ES (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
TEST_AL (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rst (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
prbs_o (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
delay_incdec_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
ck_addr_cmd_delay_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_phase_locked_all (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_dqs_found_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
dqsfound_retry (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
dqs_found_prech_req (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_phaselock_start (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_phase_locked_err (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_calib_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_if_empty (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_rank_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_byte_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_byte_redo (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_final (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_final_if_rst (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
oclkdelay_calib_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
oclk_prech_req (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
oclk_calib_resume (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
oclkdelay_calib_start (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
done_dqs_tap_inc (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rd_data_offset_0 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rd_data_offset_1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rd_data_offset_2 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rd_data_offset_ranks_0 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rd_data_offset_ranks_1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rd_data_offset_ranks_2 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_dqs_found_rank_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrcal_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrcal_prech_req (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrcal_read_req (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrcal_act_req (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
temp_wrcal_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
slot_0_present (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
slot_1_present (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wl_sm_start (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wr_lvl_start (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrcal_start (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrcal_rd_wait (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrcal_sanity_chk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
tg_timer_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
no_rst_tg_mc (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rdlvl_stg1_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rdlvl_stg1_rank_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rdlvl_stg1_start (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_dqs_found_start (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
detect_pi_found_dqs (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rdlvl_prech_req (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rdlvl_last_byte_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrcal_resume (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrcal_sanity_chk_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
mpr_rdlvl_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
mpr_rnk_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
mpr_last_byte_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
mpr_rdlvl_start (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
mpr_end_if_reset (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
prbs_rdlvl_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
prbs_last_byte_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
prbs_rdlvl_prech_req (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
prbs_rdlvl_start (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
prbs_gen_clk_en (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
prech_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
init_calib_complete (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
calib_writes (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_address (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_bank (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_ras_n (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_cas_n (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_we_n (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_reset_n (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_cs_n (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_ctl_ready (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_ctl_full (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_cmd_full (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_data_full (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
calib_ctl_wren (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
calib_cmd_wren (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
calib_seq (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
write_calib (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
read_calib (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
calib_cmd (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
calib_aux_out (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
calib_odt (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
calib_cke (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
calib_rank_cnt (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
calib_cas_slot (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
calib_data_offset_0 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
calib_data_offset_1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
calib_data_offset_2 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
calib_wrdata_en (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_wrdata (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_rddata_en (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_rddata_valid (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
dbg_phy_init (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
NUM_STG1_WR_RD (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
ADDR_INC (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
RTT_NOM2 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
RTT_NOM3 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
RTT_NOM_int (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
BURST4_FLAG (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
CLK_MEM_PERIOD (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
DDR3_RESET_DELAY_NS (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
DDR3_CKE_DELAY_NS (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
DDR2_CKE_DELAY_NS (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PWRON_RESET_DELAY_CNT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PWRON_CKE_DELAY_CNT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
DDR2_INIT_PRE_DELAY_PS (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
DDR2_INIT_PRE_CNT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
TXPR_DELAY_CNT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
TDLLK_TZQINIT_DELAY_CNT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
TWR_CYC (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
CNTNEXT_CMD (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_CNT_MR2 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_CNT_MR3 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_CNT_MR1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_CNT_MR0 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_CNT_MR_DONE (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
REG_RC0 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
REG_RC1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
REG_RC2 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
REG_RC3 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
REG_RC4 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
REG_RC5 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
nAL (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
CWL_M (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PHASELOCKED_TIMEOUT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
TG_TIMER_TIMEOUT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_IDLE (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_WAIT_CKE_EXIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_LOAD_MR (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_LOAD_MR_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_ZQCL (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_WAIT_DLLK_ZQINIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_WRLVL_START (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_WRLVL_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_WRLVL_LOAD_MR (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_WRLVL_LOAD_MR_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_WRLVL_LOAD_MR2 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_WRLVL_LOAD_MR2_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_RDLVL_ACT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_RDLVL_ACT_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_RDLVL_STG1_WRITE (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_RDLVL_STG1_WRITE_READ (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_RDLVL_STG1_READ (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_RDLVL_STG2_READ (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_RDLVL_STG2_READ_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_PRECHARGE_PREWAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_PRECHARGE (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_PRECHARGE_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_DONE (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_DDR2_PRECHARGE (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_DDR2_PRECHARGE_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_REFRESH (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_REFRESH_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_REG_WRITE (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_REG_WRITE_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_DDR2_MULTI_RANK (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_DDR2_MULTI_RANK_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_WRCAL_ACT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_WRCAL_ACT_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_WRCAL_WRITE (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_WRCAL_WRITE_READ (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_WRCAL_READ (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_WRCAL_READ_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_WRCAL_MULT_READS (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_PI_PHASELOCK_READS (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_MPR_RDEN (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_MPR_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_MPR_READ (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_MPR_DISABLE_PREWAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_MPR_DISABLE (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_MPR_DISABLE_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_OCLKDELAY_ACT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_OCLKDELAY_ACT_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_OCLKDELAY_WRITE (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_OCLKDELAY_WRITE_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_OCLKDELAY_READ (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_OCLKDELAY_READ_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
INIT_REFRESH_RNK2_WAIT (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
i (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
j (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
k (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
l (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
m (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
n (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
p (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
q (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_dqs_found_all_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_phase_locked_all_r1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_phase_locked_all_r2 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_phase_locked_all_r3 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_phase_locked_all_r4 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_calib_rank_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_phaselock_timer (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
stg1_wr_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rnk_ref_cnt (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_dqs_found_done_r1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_dqs_found_rank_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
read_calib_int (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
read_calib_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_calib_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pi_calib_done_r1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
burst_addr_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
chip_cnt_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_cmd_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_cmd_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_cmd_done_m7_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_dllk_zqinit_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_dllk_zqinit_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_init_af_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_init_af_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_init_data_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_init_mr_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_init_mr_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_init_pre_wait_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_init_pre_wait_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_pwron_ce_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_pwron_cke_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_pwron_cke_done_r1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_pwron_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_pwron_reset_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_txpr_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_txpr_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
ddr2_pre_flag_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
ddr2_refresh_flag_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
ddr3_lm_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
enable_wrlvl_cnt (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
init_complete_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
init_complete_r1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
init_complete_r2 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
init_complete_r_timing (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
init_complete_r1_timing (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
init_next_state (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
init_state_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
init_state_r1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
load_mr0 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
load_mr1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
load_mr2 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
load_mr3 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
mem_init_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
mr2_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
mr1_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
new_burst_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrcal_start_dly_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrcal_start_pre (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrcal_resume_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_tmp_odt_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_tmp_odt_r1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_tmp_cs1_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_int_cs_n (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
prech_done_pre (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
prech_done_dly_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
prech_pending_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
prech_req_posedge_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
prech_req_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
pwron_ce_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
first_rdlvl_pat_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
first_wrcal_pat_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_wrdata_en (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_wrdata_en_r1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrdata_pat_cnt (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrcal_pat_cnt (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
address_w (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
bank_w (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rdlvl_stg1_done_r1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rdlvl_stg1_start_int (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rdlvl_start_dly0_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rdlvl_start_pre (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rdlvl_last_byte_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rdlvl_rd (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rdlvl_wr (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rdlvl_wr_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
rdlvl_wr_rd (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
reg_ctrl_cnt_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
tmp_mr2_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
tmp_mr1_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_done_r1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_rank_done_r1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_rank_done_r2 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_rank_done_r3 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_rank_done_r4 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_rank_done_r5 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_rank_done_r6 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_rank_done_r7 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_rank_cntr (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_odt_ctl (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_odt (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_active (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_active_r1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
num_reads (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
temp_wrcal_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
temp_lmr_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
extend_cal_pat (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
tg_timer (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
tg_timer_go (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_wrcal_rd (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
cnt_wait (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrcal_reads (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
stg1_wr_rd_cnt (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_data_full_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wr_level_dqs_asrt (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wr_level_dqs_asrt_r1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
dqs_asrt_cnt (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
num_refresh (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
oclkdelay_calib_start_pre (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
oclkdelay_start_dly_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
oclk_wr_cnt (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrcal_wr_cnt (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrlvl_final_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
prbs_rdlvl_done_r1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
prbs_last_byte_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
phy_if_empty_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
wrcal_final_chk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_553mem_init_done_r (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_554wrlvl_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_555rdlvl_stg1_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_556mpr_rdlvl_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_557oclkdelay_calib_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_558pi_calib_done_r1 (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_559pi_dqs_found_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_560wrcal_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_561clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_562clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_563clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_564clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_565clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_566clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_567clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_568clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_569clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_570clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_571clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_572clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_573clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_574clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_575clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_576clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_577clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_578clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_579clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_580clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_581clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_582clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_583clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_584clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_585clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_586clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_587clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_588clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_589clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_590clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_591clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_592clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_593clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_594clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_595clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_596clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_597clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_598clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_599clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_600clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_601clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_602clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_603clk orrst (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_604clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_605clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_606clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_607clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_608clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_609clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_610clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_611clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_612clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_613clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_614clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_615burst_addr_r or chip_cnt_r or cnt_cmd_done_r or cnt_dllk_zqinit_done_r or cnt_init_af_done_r or cnt_init_mr_done_r or phy_ctl_ready or phy_ctl_full or stg1_wr_done or rdlvl_last_byte_doneor phy_cmd_full or num_reads or rnk_ref_cnt or mpr_last_byte_doneor oclk_wr_cnt or mpr_rdlvl_done or mpr_rnk_done or num_refreshor oclkdelay_calib_done or oclk_prech_req or oclk_calib_resume or wrlvl_byte_redo or wrlvl_byte_done or wrlvl_final or wrlvl_final_r or cnt_init_pre_wait_done_r or cnt_pwron_cke_done_ror delay_incdec_done or wrcal_wr_cntor ck_addr_cmd_delay_done or wrcal_read_req or wrcal_reads or cnt_wrcal_rd or wrcal_act_req or temp_wrcal_done or temp_lmr_done or cnt_txpr_done_r or ddr2_pre_flag_r or ddr2_refresh_flag_r or ddr3_lm_done_r or init_state_r or mem_init_done_r or dqsfound_retry or dqs_found_prech_req or prech_req_posedge_r or prech_req_r or wrcal_done or wrcal_resume_ror rdlvl_stg1_done or rdlvl_stg1_done_r1 or rdlvl_stg1_rank_done or rdlvl_stg1_start_int or prbs_rdlvl_done or prbs_last_byte_done or prbs_rdlvl_done_r1 or stg1_wr_rd_cnt or rdlvl_prech_req or wrcal_prech_req or read_calib_int or read_calib_r or pi_calib_done_r1 or pi_phase_locked_all_r3 or pi_phase_locked_all_r4 or pi_dqs_found_done or pi_dqs_found_rank_done or pi_dqs_found_start or reg_ctrl_cnt_r or wrlvl_done_r1 or wrlvl_rank_done_r7or wrcal_final_chk or wrcal_sanity_chk_done (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_616clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_617clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_618clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_619clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_620clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_621clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_622clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_623clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_624clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_625clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_626clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_627clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_628clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_629clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_630clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_631clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_632clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_633clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_634clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_635clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_636clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_637clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_638clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_639clk (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
PROCESS_640burst_addr_r or cnt_init_mr_r or chip_cnt_r or wrcal_wr_cnt or ddr2_refresh_flag_r or init_state_r or load_mr0 or phy_data_full_r or load_mr1 or load_mr2 or load_mr3 or new_burst_r or phy_address or mr1_r[0][0] or mr1_r[0][1] or mr1_r[0][2] or mr1_r[1][0] or mr1_r[1][1] or mr1_r[1][2] or mr1_r[2][0] or mr1_r[2][1] or mr1_r[2][2] or mr1_r[3][0] or mr1_r[3][1] or mr1_r[3][2] or mr2_r[chip_cnt_r] or reg_ctrl_cnt_r or stg1_wr_rd_cnt or oclk_wr_cnt or rdlvl_stg1_done or prbs_rdlvl_done or pi_dqs_found_done or rdlvl_wr_rd (defined in mig_7series_v1_9_ddr_phy_init)mig_7series_v1_9_ddr_phy_initClass
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