AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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mig_7series_v1_9_ddr_mc_phy_wrapper Member List

This is the complete list of members for mig_7series_v1_9_ddr_mc_phy_wrapper, including all inherited members.

BYTE_LANES_B0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
BYTE_LANES_B1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
BYTE_LANES_B2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
BYTE_LANES_B3 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
BYTE_LANES_B4 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
DATA_CTL_B0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
DATA_CTL_B1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
DATA_CTL_B2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
DATA_CTL_B3 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
DATA_CTL_B4 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
RCLK_SELECT_BANK (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
RCLK_SELECT_LANE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
RCLK_SELECT_EDGE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
GENERATE_DDR_CK_MAP (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
BYTELANES_DDR_CK (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
USE_PRE_POST_FIFO (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
SYNTHESIS (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PO_CTL_COARSE_BYPASS (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PI_SEL_CLK_OFFSET (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHYCTL_CMD_FIFO (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_CLK_RATIO (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_FOUR_WINDOW_CLOCKS (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_EVENTS_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_COUNT_EN (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_SYNC_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_DISABLE_SEQ_MATCH (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
MASTER_PHY_CTL (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_BITLANES (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_BITLANES_OUTONLY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_LANE_REMAP (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_GENERATE_IDELAYCTRL (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_IODELAY_GRP (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
BANK_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
NUM_DDR_CK (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_DATA_CTL (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_CMD_OFFSET (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_RD_CMD_OFFSET_0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_RD_CMD_OFFSET_1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_RD_CMD_OFFSET_2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_RD_CMD_OFFSET_3 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_RD_DURATION_0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_RD_DURATION_1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_RD_DURATION_2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_RD_DURATION_3 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_WR_CMD_OFFSET_0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_WR_CMD_OFFSET_1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_WR_CMD_OFFSET_2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_WR_CMD_OFFSET_3 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_WR_DURATION_0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_WR_DURATION_1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_WR_DURATION_2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_WR_DURATION_3 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_AO_WRLVL_EN (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_AO_TOGGLE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_OF_ALMOST_FULL_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_IF_ALMOST_EMPTY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_A_PI_FREQ_REF_DIV (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_A_PI_CLKOUT_DIV (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_A_PO_CLKOUT_DIV (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_A_BURST_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_A_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_A_PO_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_A_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_B_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_C_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_D_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_A_PO_OCLKDELAY_INV (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_A_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_B_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_C_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_D_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_A_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_B_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_C_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_D_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_A_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_A_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_B_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_B_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_C_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_C_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_D_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_D_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_A_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_A_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_B_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_B_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_C_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_C_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_D_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_D_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_BITLANES (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_BITLANES_OUTONLY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_LANE_REMAP (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_GENERATE_IDELAYCTRL (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_IODELAY_GRP (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_DATA_CTL (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_CMD_OFFSET (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_RD_CMD_OFFSET_0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_RD_CMD_OFFSET_1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_RD_CMD_OFFSET_2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_RD_CMD_OFFSET_3 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_RD_DURATION_0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_RD_DURATION_1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_RD_DURATION_2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_RD_DURATION_3 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_WR_CMD_OFFSET_0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_WR_CMD_OFFSET_1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_WR_CMD_OFFSET_2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_WR_CMD_OFFSET_3 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_WR_DURATION_0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_WR_DURATION_1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_WR_DURATION_2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_WR_DURATION_3 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_AO_WRLVL_EN (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_AO_TOGGLE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_OF_ALMOST_FULL_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_IF_ALMOST_EMPTY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_A_PI_FREQ_REF_DIV (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_A_PI_CLKOUT_DIV (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_A_PO_CLKOUT_DIV (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_A_BURST_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_A_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_A_PO_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_A_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_B_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_C_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_D_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_A_PO_OCLKDELAY_INV (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_A_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_A_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_B_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_B_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_C_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_C_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_D_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_D_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_A_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_B_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_C_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_D_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_A_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_B_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_C_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_D_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_A_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_A_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_B_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_B_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_C_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_C_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_D_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_D_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_BITLANES (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_BITLANES_OUTONLY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_LANE_REMAP (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_GENERATE_IDELAYCTRL (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_IODELAY_GRP (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_DATA_CTL (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_CMD_OFFSET (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_RD_CMD_OFFSET_0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_RD_CMD_OFFSET_1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_RD_CMD_OFFSET_2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_RD_CMD_OFFSET_3 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_RD_DURATION_0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_RD_DURATION_1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_RD_DURATION_2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_RD_DURATION_3 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_WR_CMD_OFFSET_0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_WR_CMD_OFFSET_1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_WR_CMD_OFFSET_2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_WR_CMD_OFFSET_3 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_WR_DURATION_0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_WR_DURATION_1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_WR_DURATION_2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_WR_DURATION_3 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_AO_WRLVL_EN (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_AO_TOGGLE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_OF_ALMOST_FULL_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_IF_ALMOST_EMPTY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_A_PI_FREQ_REF_DIV (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_A_PI_CLKOUT_DIV (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_A_PO_CLKOUT_DIV (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_A_BURST_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_A_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_A_PO_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_A_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_B_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_C_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_D_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_A_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_B_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_C_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_D_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_A_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_B_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_C_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_D_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_A_PO_OCLKDELAY_INV (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_A_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_A_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_B_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_B_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_C_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_C_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_D_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_D_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_A_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_A_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_B_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_B_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_C_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_C_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_D_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_D_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_0_IS_LAST_BANK (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_1_IS_LAST_BANK (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_2_IS_LAST_BANK (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
TCK (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
N_LANES (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
HIGHEST_BANK (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
HIGHEST_LANE_B0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
HIGHEST_LANE_B1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
HIGHEST_LANE_B2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
HIGHEST_LANE_B3 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
HIGHEST_LANE_B4 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
HIGHEST_LANE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
LP_DDR_CK_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
GENERATE_SIGNAL_SPLIT (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
CKE_ODT_AUX (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
rst (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
ddr_rst_in_n (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_clk (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
freq_refclk (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
mem_refclk (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
mem_refclk_div4 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pll_lock (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
sync_pulse (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
auxout_clk (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
idelayctrl_refclk (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_dout (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_cmd_wr_en (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_data_wr_en (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_rd_en (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_wd (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
aux_in_1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
aux_in_2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
data_offset_1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
data_offset_2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_wr (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_rst (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_empty_def (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
cke_in (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
idelay_ce (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
idelay_ld (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
idelay_inc (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phyGo (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
input_sink (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_a_empty (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_empty (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_empty_or (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_empty_and (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
of_ctl_a_full (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
of_data_a_full (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
of_ctl_full (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
of_data_full (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pre_data_a_full (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_din (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_a_full (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_full (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
mem_dq_out (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
mem_dq_ts (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
mem_dq_in (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
mem_dqs_out (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
mem_dqs_ts (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
mem_dqs_in (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
aux_out (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_ready (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
rst_out (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
ddr_clk (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
mcGo (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
ref_dll_lock (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_write_calib (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_read_calib (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
calib_sel (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
calib_zero_inputs (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
calib_zero_ctrl (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
calib_zero_lanes (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
calib_in_common (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
po_fine_enable (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
po_coarse_enable (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
po_fine_inc (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
po_coarse_inc (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
po_counter_load_en (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
po_sel_fine_oclk_delay (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
po_counter_load_val (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
po_counter_read_en (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
po_coarse_overflow (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
po_fine_overflow (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
po_counter_read_val (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_rst_dqs_find (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_fine_enable (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_fine_inc (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_counter_load_en (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_counter_read_en (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_counter_load_val (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_fine_overflow (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_counter_read_val (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_phase_locked (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_phase_locked_all (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_dqs_found (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_dqs_found_all (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_dqs_found_any (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_phase_locked_lanes (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_dqs_found_lanes (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_dqs_out_of_range (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
calib_zero_inputs_int (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
calib_zero_lanes_int (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
calib_sel_byte0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
calib_sel_byte1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
calib_sel_byte2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
po_coarse_overflow_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
po_fine_overflow_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
po_counter_read_val_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_fine_overflow_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_counter_read_val_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_dqs_found_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_dqs_found_all_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_dqs_found_any_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_dqs_out_of_range_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_phase_locked_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pi_phase_locked_all_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
rclk_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_ready_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
ddr_clk_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
aux_out_ (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_q0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_q1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_q2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_q3 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_q4 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_q5 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_q6 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_q7 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_q8 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_q9 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
_phy_ctl_wd (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
aux_in_ (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
rst_out_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
freq_refclk_split (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
mem_refclk_split (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
mem_refclk_div4_split (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
sync_pulse_split (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_clk_split0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_clk_split0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_wd_split0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_wr_split0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_clk_split1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_clk_split1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_wd_split1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_wr_split1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_data_offset_1_split1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_clk_split2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_clk_split2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_wd_split2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_wr_split2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_data_offset_2_split2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_dout_split0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_cmd_wr_en_split0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_data_wr_en_split0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_rd_en_split0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_dout_split1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_cmd_wr_en_split1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_data_wr_en_split1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_rd_en_split1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_dout_split2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_cmd_wr_en_split2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_data_wr_en_split2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_rd_en_split2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_mstr_empty (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
phy_ctl_empty (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
_phy_ctl_a_full_f (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
_phy_ctl_a_empty_f (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
_phy_ctl_full_f (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
_phy_ctl_empty_f (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
_phy_ctl_a_full_p (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
_phy_ctl_full_p (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
of_ctl_a_full_v (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
of_ctl_full_v (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
of_data_a_full_v (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
of_data_full_v (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
pre_data_a_full_v (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_empty_v (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
byte_rd_en_v (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
byte_rd_en_oth_banks (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_empty_or_v (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_empty_and_v (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
if_a_empty_v (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
IF_SYNCHRONOUS_MODE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
IF_SLOW_WR_CLK (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
IF_SLOW_RD_CLK (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PHY_MULTI_REGION (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
RCLK_NEG_EDGE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
RCLK_POS_EDGE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
LP_PHY_0_BYTELANES_DDR_CK (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
LP_PHY_1_BYTELANES_DDR_CK (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
LP_PHY_2_BYTELANES_DDR_CK (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PC_DATA_OFFSET_RANGE_HI (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PC_DATA_OFFSET_RANGE_LO (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
RCLK_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
DDR_TCK (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
FREQ_REF_PERIOD (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_FREQ_REF_PERIOD_NS (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PO_S3_TAPS (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PI_S2_TAPS (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PO_S2_TAPS (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PI_STG1_INTRINSIC_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PI_STG2_INTRINSIC_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PO_STG1_INTRINSIC_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PO_STG2_FINE_INTRINSIC_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PO_STG2_COARSE_INTRINSIC_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PO_STG2_INTRINSIC_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PO_S2_TAPS_SIZE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PO_CIRC_BUF_META_ZONE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PO_CIRC_BUF_EARLY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PO_CIRC_BUF_OFFSET (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PO_CIRC_BUF_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PI_S2_TAPS_SIZE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PI_MAX_STG2_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PI_INTRINSIC_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PO_INTRINSIC_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PO_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
RCLK_BUFIO_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
RCLK_DELAY_INT (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PO_DELAY_INT (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PI_OFFSET (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PI_STG2_DELAY_CAND (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PI_STG2_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
DEFAULT_RCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
LP_RCLK_SELECT_EDGE (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_0_PO_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_1_PO_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_2_PO_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_0_A_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_0_B_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_0_C_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_0_D_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_1_A_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_1_B_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_1_C_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_1_D_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_2_A_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_2_B_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_2_C_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_2_D_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_0_A_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_0_B_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_0_C_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_0_D_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_1_A_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_1_B_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_1_C_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_1_D_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_2_A_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_2_B_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_2_C_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
L_PHY_2_D_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
_phy_clk (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
mcGo_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
ref_dll_lock_w (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
mcGo_r (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
blb0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
blb1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
blb2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
dcb0 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
dcb1 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
dcb2 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
rst_auxout (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
rst_auxout_r (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
rst_auxout_rr (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
aux_in1_reg (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
aux_in2_reg (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
sfifo_ready (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
TCQ (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
tCK (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
BANK_TYPE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA_IO_PRIM_TYPE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA_IO_IDLE_PWRDWN (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IODELAY_GRP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
nCK_PER_CLK (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
nCS_PER_RANK (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
BANK_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CKE_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CS_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CK_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CWL (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DDR2_DQSN_ENABLE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DM_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DQ_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DQS_CNT_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DQS_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DRAM_TYPE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
RANKS (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ODT_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
REG_CTRL (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ROW_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
USE_CS_PORT (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
USE_DM_PORT (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
USE_ODT_PORT (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IBUF_LPWR_MODE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
LP_DDR_CK_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
PHYCTL_CMD_FIFO (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA_CTL_B0 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA_CTL_B1 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA_CTL_B2 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA_CTL_B3 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA_CTL_B4 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
BYTE_LANES_B0 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
BYTE_LANES_B1 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
BYTE_LANES_B2 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
BYTE_LANES_B3 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
BYTE_LANES_B4 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
PHY_0_BITLANES (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
PHY_1_BITLANES (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
PHY_2_BITLANES (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
HIGHEST_BANK (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
HIGHEST_LANE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CK_BYTE_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ADDR_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
BANK_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CAS_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CKE_ODT_BYTE_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CKE_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ODT_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CKE_ODT_AUX (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CS_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
PARITY_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
RAS_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
WE_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DQS_BYTE_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA0_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA1_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA2_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA3_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA4_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA5_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA6_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA7_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA8_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA9_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA10_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA11_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA12_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA13_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA14_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA15_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA16_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA17_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
MASK0_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
MASK1_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
SIM_CAL_OPTION (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
MASTER_PHY_CTL (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
rst (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
clk (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
freq_refclk (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mem_refclk (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pll_lock (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
sync_pulse (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
idelayctrl_refclk (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_cmd_wr_en (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_data_wr_en (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_ctl_wd (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_ctl_wr (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_if_empty_def (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_if_reset (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
data_offset_1 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
data_offset_2 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
aux_in_1 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
aux_in_2 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
idelaye2_init_val (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
oclkdelay_init_val (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
if_empty (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_ctl_full (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_cmd_full (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_data_full (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_pre_data_a_full (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_clk (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_mc_go (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_write_calib (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_read_calib (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
calib_in_common (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
calib_sel (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
calib_zero_inputs (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
calib_zero_ctrl (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_fine_enable (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_coarse_enable (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_fine_inc (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_coarse_inc (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_counter_load_en (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_counter_read_en (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_sel_fine_oclk_delay (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_counter_load_val (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_counter_read_val (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_counter_read_val (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_rst_dqs_find (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_fine_enable (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_fine_inc (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_counter_load_en (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_counter_load_val (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
idelay_ce (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
idelay_inc (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
idelay_ld (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
idle (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_phase_locked (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_phase_locked_all (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_dqs_found (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_dqs_found_all (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_dqs_out_of_range (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_init_data_sel (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_address (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_bank (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_cas_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_cs_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_ras_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_odt (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_cke (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_we_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
parity_in (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_wrdata (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_wrdata_mask (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_reset_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
rd_data (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_addr (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_ba (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_cas_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_cke (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_cs_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_dm (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_odt (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_parity (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_ras_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_we_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_reset_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_dq (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_dqs (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_dqs_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
dbg_pi_counter_read_en (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ref_dll_lock (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
rst_phaser_ref (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
dbg_pi_phase_locked_phy4lanes (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
dbg_pi_dqs_found_lanes_phy4lanes (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
TCQ (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
DEPTH (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
WIDTH (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
clk (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
rst (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
full_in (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
wr_en_in (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
d_in (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
wr_en_out (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
d_out (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
afull (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
PTR_BITS (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
ALMOST_FULL_VALUE (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
i (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
mem (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
entry_cnt (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
nxt_rd_ptr (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
nxt_wr_ptr (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
mem_out (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
wr_en (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
calc_phy_bitlanes_outonlydata_mask_in (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
generate_bytelanes_ddr_ckck_byte_map (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
generate_ddr_ck_map (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUF_DCIEN (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUF_DCIEN (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUF_INTERMDISABLE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUF_INTERMDISABLE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUFDS (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUFDS_DCIEN (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUFDS_INTERMDISABLE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mig_7series_v1_9_ddr_mc_phy (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mig_7series_v1_9_ddr_of_pre_fifo (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mig_7series_v1_9_ddr_of_pre_fifo (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mig_7series_v1_9_ddr_of_pre_fifo (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUFT (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_dqs_out_of_range (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
PROCESS_504auxout_clk orrst (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PROCESS_505phy_clk (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PROCESS_506auxout_clk orrst_auxout (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PROCESS_507 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PROCESS_508auxout_clk orrst_auxout (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PROCESS_509 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PROCESS_510 (defined in mig_7series_v1_9_ddr_mc_phy)mig_7series_v1_9_ddr_mc_phyClass
PROCESS_511clk (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
PROCESS_512clk (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
PROCESS_513clk (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
PROCESS_514clk (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
PROCESS_515clk (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
PROCESS_516clk (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
PROCESS_517clk (defined in mig_7series_v1_9_ddr_of_pre_fifo)mig_7series_v1_9_ddr_of_pre_fifoClass
Generated on Wed Apr 18 2018 10:55:30 for AMC13 by   doxygen 1.8.1