mig_7series_v1_9_ddr_mc_phy Member List

This is the complete list of members for mig_7series_v1_9_ddr_mc_phy, including all inherited members.

BYTE_LANES_B0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
BYTE_LANES_B1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
BYTE_LANES_B2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
BYTE_LANES_B3 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
BYTE_LANES_B4 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
DATA_CTL_B0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
DATA_CTL_B1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
DATA_CTL_B2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
DATA_CTL_B3 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
DATA_CTL_B4 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
RCLK_SELECT_BANK (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
RCLK_SELECT_LANE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
RCLK_SELECT_EDGE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
GENERATE_DDR_CK_MAP (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
BYTELANES_DDR_CK (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
USE_PRE_POST_FIFO (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
SYNTHESIS (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PO_CTL_COARSE_BYPASS (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PI_SEL_CLK_OFFSET (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHYCTL_CMD_FIFO (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_CLK_RATIO (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_FOUR_WINDOW_CLOCKS (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_EVENTS_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_COUNT_EN (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_SYNC_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_DISABLE_SEQ_MATCH (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
MASTER_PHY_CTL (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_BITLANES (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_BITLANES_OUTONLY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_LANE_REMAP (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_GENERATE_IDELAYCTRL (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_IODELAY_GRP (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
BANK_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
NUM_DDR_CK (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_DATA_CTL (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_CMD_OFFSET (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_RD_CMD_OFFSET_0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_RD_CMD_OFFSET_1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_RD_CMD_OFFSET_2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_RD_CMD_OFFSET_3 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_RD_DURATION_0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_RD_DURATION_1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_RD_DURATION_2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_RD_DURATION_3 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_WR_CMD_OFFSET_0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_WR_CMD_OFFSET_1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_WR_CMD_OFFSET_2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_WR_CMD_OFFSET_3 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_WR_DURATION_0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_WR_DURATION_1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_WR_DURATION_2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_WR_DURATION_3 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_AO_WRLVL_EN (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_AO_TOGGLE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_OF_ALMOST_FULL_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_IF_ALMOST_EMPTY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_A_PI_FREQ_REF_DIV (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_A_PI_CLKOUT_DIV (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_A_PO_CLKOUT_DIV (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_A_BURST_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_A_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_A_PO_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_A_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_B_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_C_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_D_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_A_PO_OCLKDELAY_INV (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_A_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_B_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_C_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_D_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_A_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_B_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_C_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_D_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_A_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_A_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_B_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_B_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_C_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_C_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_D_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_D_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_A_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_A_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_B_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_B_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_C_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_C_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_D_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_D_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_BITLANES (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_BITLANES_OUTONLY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_LANE_REMAP (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_GENERATE_IDELAYCTRL (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_IODELAY_GRP (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_DATA_CTL (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_CMD_OFFSET (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_RD_CMD_OFFSET_0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_RD_CMD_OFFSET_1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_RD_CMD_OFFSET_2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_RD_CMD_OFFSET_3 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_RD_DURATION_0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_RD_DURATION_1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_RD_DURATION_2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_RD_DURATION_3 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_WR_CMD_OFFSET_0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_WR_CMD_OFFSET_1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_WR_CMD_OFFSET_2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_WR_CMD_OFFSET_3 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_WR_DURATION_0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_WR_DURATION_1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_WR_DURATION_2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_WR_DURATION_3 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_AO_WRLVL_EN (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_AO_TOGGLE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_OF_ALMOST_FULL_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_IF_ALMOST_EMPTY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_A_PI_FREQ_REF_DIV (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_A_PI_CLKOUT_DIV (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_A_PO_CLKOUT_DIV (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_A_BURST_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_A_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_A_PO_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_A_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_B_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_C_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_D_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_A_PO_OCLKDELAY_INV (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_A_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_A_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_B_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_B_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_C_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_C_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_D_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_D_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_A_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_B_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_C_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_D_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_A_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_B_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_C_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_D_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_A_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_A_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_B_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_B_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_C_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_C_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_D_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_D_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_BITLANES (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_BITLANES_OUTONLY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_LANE_REMAP (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_GENERATE_IDELAYCTRL (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_IODELAY_GRP (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_DATA_CTL (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_CMD_OFFSET (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_RD_CMD_OFFSET_0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_RD_CMD_OFFSET_1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_RD_CMD_OFFSET_2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_RD_CMD_OFFSET_3 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_RD_DURATION_0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_RD_DURATION_1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_RD_DURATION_2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_RD_DURATION_3 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_WR_CMD_OFFSET_0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_WR_CMD_OFFSET_1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_WR_CMD_OFFSET_2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_WR_CMD_OFFSET_3 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_WR_DURATION_0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_WR_DURATION_1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_WR_DURATION_2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_WR_DURATION_3 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_AO_WRLVL_EN (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_AO_TOGGLE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_OF_ALMOST_FULL_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_IF_ALMOST_EMPTY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_A_PI_FREQ_REF_DIV (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_A_PI_CLKOUT_DIV (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_A_PO_CLKOUT_DIV (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_A_BURST_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_A_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_A_PO_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_A_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_B_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_C_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_D_OF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_A_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_B_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_C_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_D_IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_A_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_B_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_C_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_D_PO_OCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_A_PO_OCLKDELAY_INV (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_A_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_A_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_B_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_B_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_C_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_C_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_D_OSERDES_DATA_RATE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_D_OSERDES_DATA_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_A_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_A_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_B_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_B_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_C_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_C_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_D_IDELAYE2_IDELAY_TYPE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_D_IDELAYE2_IDELAY_VALUE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_0_IS_LAST_BANK (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_1_IS_LAST_BANK (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_2_IS_LAST_BANK (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
TCK (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
N_LANES (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
HIGHEST_BANK (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
HIGHEST_LANE_B0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
HIGHEST_LANE_B1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
HIGHEST_LANE_B2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
HIGHEST_LANE_B3 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
HIGHEST_LANE_B4 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
HIGHEST_LANE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
LP_DDR_CK_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
GENERATE_SIGNAL_SPLIT (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
CKE_ODT_AUX (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
rst (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
ddr_rst_in_n (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_clk (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
freq_refclk (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
mem_refclk (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
mem_refclk_div4 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pll_lock (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
sync_pulse (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
auxout_clk (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
idelayctrl_refclk (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_dout (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_cmd_wr_en (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_data_wr_en (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_rd_en (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_wd (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
aux_in_1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
aux_in_2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
data_offset_1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
data_offset_2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_wr (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_rst (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_empty_def (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
cke_in (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
idelay_ce (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
idelay_ld (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
idelay_inc (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phyGo (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
input_sink (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_a_empty (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_empty (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_empty_or (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_empty_and (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
of_ctl_a_full (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
of_data_a_full (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
of_ctl_full (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
of_data_full (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pre_data_a_full (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_din (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_a_full (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_full (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
mem_dq_out (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
mem_dq_ts (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
mem_dq_in (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
mem_dqs_out (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
mem_dqs_ts (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
mem_dqs_in (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
aux_out (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_ready (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
rst_out (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
ddr_clk (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
mcGo (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
ref_dll_lock (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_write_calib (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_read_calib (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
calib_sel (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
calib_zero_inputs (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
calib_zero_ctrl (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
calib_zero_lanes (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
calib_in_common (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
po_fine_enable (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
po_coarse_enable (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
po_fine_inc (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
po_coarse_inc (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
po_counter_load_en (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
po_sel_fine_oclk_delay (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
po_counter_load_val (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
po_counter_read_en (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
po_coarse_overflow (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
po_fine_overflow (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
po_counter_read_val (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_rst_dqs_find (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_fine_enable (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_fine_inc (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_counter_load_en (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_counter_read_en (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_counter_load_val (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_fine_overflow (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_counter_read_val (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_phase_locked (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_phase_locked_all (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_dqs_found (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_dqs_found_all (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_dqs_found_any (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_phase_locked_lanes (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_dqs_found_lanes (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_dqs_out_of_range (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
calib_zero_inputs_int (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
calib_zero_lanes_int (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
calib_sel_byte0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
calib_sel_byte1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
calib_sel_byte2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
po_coarse_overflow_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
po_fine_overflow_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
po_counter_read_val_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_fine_overflow_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_counter_read_val_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_dqs_found_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_dqs_found_all_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_dqs_found_any_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_dqs_out_of_range_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_phase_locked_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pi_phase_locked_all_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
rclk_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_ready_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
ddr_clk_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
aux_out_ (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_q0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_q1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_q2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_q3 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_q4 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_q5 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_q6 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_q7 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_q8 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_q9 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
_phy_ctl_wd (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
aux_in_ (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
rst_out_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
freq_refclk_split (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
mem_refclk_split (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
mem_refclk_div4_split (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
sync_pulse_split (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_clk_split0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_clk_split0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_wd_split0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_wr_split0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_clk_split1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_clk_split1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_wd_split1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_wr_split1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_data_offset_1_split1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_clk_split2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_clk_split2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_wd_split2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_wr_split2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_data_offset_2_split2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_dout_split0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_cmd_wr_en_split0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_data_wr_en_split0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_rd_en_split0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_dout_split1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_cmd_wr_en_split1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_data_wr_en_split1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_rd_en_split1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_dout_split2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_cmd_wr_en_split2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_data_wr_en_split2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_rd_en_split2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_mstr_empty (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
phy_ctl_empty (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
_phy_ctl_a_full_f (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
_phy_ctl_a_empty_f (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
_phy_ctl_full_f (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
_phy_ctl_empty_f (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
_phy_ctl_a_full_p (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
_phy_ctl_full_p (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
of_ctl_a_full_v (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
of_ctl_full_v (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
of_data_a_full_v (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
of_data_full_v (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
pre_data_a_full_v (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_empty_v (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
byte_rd_en_v (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
byte_rd_en_oth_banks (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_empty_or_v (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_empty_and_v (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
if_a_empty_v (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
IF_ARRAY_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
IF_SYNCHRONOUS_MODE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
IF_SLOW_WR_CLK (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
IF_SLOW_RD_CLK (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PHY_MULTI_REGION (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
RCLK_NEG_EDGE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
RCLK_POS_EDGE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
LP_PHY_0_BYTELANES_DDR_CK (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
LP_PHY_1_BYTELANES_DDR_CK (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
LP_PHY_2_BYTELANES_DDR_CK (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PC_DATA_OFFSET_RANGE_HI (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PC_DATA_OFFSET_RANGE_LO (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
RCLK_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
DDR_TCK (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
FREQ_REF_PERIOD (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_FREQ_REF_PERIOD_NS (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PO_S3_TAPS (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PI_S2_TAPS (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PO_S2_TAPS (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PI_STG1_INTRINSIC_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PI_STG2_INTRINSIC_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PO_STG1_INTRINSIC_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PO_STG2_FINE_INTRINSIC_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PO_STG2_COARSE_INTRINSIC_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PO_STG2_INTRINSIC_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PO_S2_TAPS_SIZE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PO_CIRC_BUF_META_ZONE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PO_CIRC_BUF_EARLY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PO_CIRC_BUF_OFFSET (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PO_CIRC_BUF_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PI_S2_TAPS_SIZE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PI_MAX_STG2_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PI_INTRINSIC_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PO_INTRINSIC_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PO_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
RCLK_BUFIO_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
RCLK_DELAY_INT (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PO_DELAY_INT (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PI_OFFSET (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PI_STG2_DELAY_CAND (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PI_STG2_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
DEFAULT_RCLK_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
LP_RCLK_SELECT_EDGE (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_0_PO_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_1_PO_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_2_PO_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_0_A_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_0_B_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_0_C_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_0_D_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_1_A_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_1_B_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_1_C_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_1_D_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_2_A_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_2_B_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_2_C_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_2_D_PI_FINE_DELAY (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_0_A_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_0_B_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_0_C_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_0_D_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_1_A_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_1_B_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_1_C_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_1_D_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_2_A_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_2_B_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_2_C_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
L_PHY_2_D_PI_OUTPUT_CLK_SRC (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
_phy_clk (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
mcGo_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
ref_dll_lock_w (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
mcGo_r (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
blb0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
blb1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
blb2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
dcb0 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
dcb1 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
dcb2 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
rst_auxout (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
rst_auxout_r (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
rst_auxout_rr (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
aux_in1_reg (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
aux_in2_reg (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
sfifo_ready (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PROCESS_504auxout_clk orrst (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PROCESS_505phy_clk (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PROCESS_506auxout_clk orrst_auxout (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PROCESS_507 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PROCESS_508auxout_clk orrst_auxout (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PROCESS_509 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class
PROCESS_510 (defined in mig_7series_v1_9_ddr_mc_phy)	mig_7series_v1_9_ddr_mc_phy	Class